245 lines
6.4 KiB
C
245 lines
6.4 KiB
C
/*
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* linux/arch/arm/mach-omap2/timer-gp.c
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*
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* OMAP2 GP timer support.
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*
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* Copyright (C) 2009 Nokia Corporation
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*
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* Update to use new clocksource/clockevent layers
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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*
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* Original driver:
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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* Juha Yrjölä <juha.yrjola@nokia.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* Some parts based off of TI's 24xx code:
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*
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* Copyright (C) 2004-2009 Texas Instruments, Inc.
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*
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* Roughly modelled after the OMAP1 MPU timer code.
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/mach/time.h>
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#include <mach/dmtimer.h>
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#include <asm/localtimer.h>
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/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
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#define MAX_GPTIMER_ID 12
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static struct omap_dm_timer *gptimer;
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static struct clock_event_device clockevent_gpt;
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static u8 __initdata gptimer_id = 1;
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static u8 __initdata inited;
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static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
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{
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struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
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struct clock_event_device *evt = &clockevent_gpt;
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omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction omap2_gp_timer_irq = {
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.name = "gp timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = omap2_gp_timer_interrupt,
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};
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static int omap2_gp_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
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return 0;
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}
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static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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u32 period;
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omap_dm_timer_stop(gptimer);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
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period -= 1;
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if (cpu_is_omap44xx())
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period = 0xff; /* FIXME: */
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omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device clockevent_gpt = {
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.name = "gp timer",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_next_event = omap2_gp_timer_set_next_event,
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.set_mode = omap2_gp_timer_set_mode,
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};
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/**
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* omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
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* @id: GPTIMER to use (1..MAX_GPTIMER_ID)
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*
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* Define the GPTIMER that the system should use for the tick timer.
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* Meant to be called from board-*.c files in the event that GPTIMER1, the
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* default, is unsuitable. Returns -EINVAL on error or 0 on success.
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*/
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int __init omap2_gp_clockevent_set_gptimer(u8 id)
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{
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if (id < 1 || id > MAX_GPTIMER_ID)
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return -EINVAL;
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BUG_ON(inited);
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gptimer_id = id;
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return 0;
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}
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static void __init omap2_gp_clockevent_init(void)
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{
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u32 tick_rate;
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int src;
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inited = 1;
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gptimer = omap_dm_timer_request_specific(gptimer_id);
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BUG_ON(gptimer == NULL);
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#if defined(CONFIG_OMAP_32K_TIMER)
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src = OMAP_TIMER_SRC_32_KHZ;
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#else
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src = OMAP_TIMER_SRC_SYS_CLK;
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WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
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"secure 32KiHz clock source\n");
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#endif
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if (gptimer_id != 12)
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WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
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"timer-gp: omap_dm_timer_set_source() failed\n");
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tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
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if (cpu_is_omap44xx())
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/* Assuming 32kHz clk is driving GPT1 */
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tick_rate = 32768; /* FIXME: */
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pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
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gptimer_id, tick_rate);
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omap2_gp_timer_irq.dev_id = (void *)gptimer;
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setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
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clockevent_gpt.shift);
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clockevent_gpt.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &clockevent_gpt);
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clockevent_gpt.min_delta_ns =
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clockevent_delta2ns(3, &clockevent_gpt);
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/* Timer internal resynch latency. */
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clockevent_gpt.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_gpt);
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}
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/* Clocksource code */
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#ifdef CONFIG_OMAP_32K_TIMER
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/*
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* When 32k-timer is enabled, don't use GPTimer for clocksource
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* instead, just leave default clocksource which uses the 32k
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* sync counter. See clocksource setup in see plat-omap/common.c.
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*/
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static inline void __init omap2_gp_clocksource_init(void) {}
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#else
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/*
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* clocksource
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*/
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static struct omap_dm_timer *gpt_clocksource;
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static cycle_t clocksource_read_cycles(struct clocksource *cs)
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{
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return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
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}
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static struct clocksource clocksource_gpt = {
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.name = "gp timer",
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.rating = 300,
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.read = clocksource_read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 24,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/* Setup free-running counter for clocksource */
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static void __init omap2_gp_clocksource_init(void)
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{
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static struct omap_dm_timer *gpt;
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u32 tick_rate, tick_period;
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static char err1[] __initdata = KERN_ERR
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"%s: failed to request dm-timer\n";
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static char err2[] __initdata = KERN_ERR
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"%s: can't register clocksource!\n";
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gpt = omap_dm_timer_request();
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if (!gpt)
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printk(err1, clocksource_gpt.name);
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gpt_clocksource = gpt;
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omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
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tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
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tick_period = (tick_rate / HZ) - 1;
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omap_dm_timer_set_load_start(gpt, 1, 0);
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clocksource_gpt.mult =
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clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
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if (clocksource_register(&clocksource_gpt))
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printk(err2, clocksource_gpt.name);
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}
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#endif
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static void __init omap2_gp_timer_init(void)
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{
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
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#endif
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omap_dm_timer_init();
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omap2_gp_clockevent_init();
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omap2_gp_clocksource_init();
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}
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struct sys_timer omap_timer = {
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.init = omap2_gp_timer_init,
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};
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