46 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			46 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * stmp378x: DRI register definitions
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|  *
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|  * Copyright (c) 2008 Freescale Semiconductor
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|  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; either version 2 of the License, or
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|  * (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
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|  */
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| #define REGS_DRI_BASE	(STMP3XXX_REGS_BASE + 0x74000)
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| #define REGS_DRI_PHYS	0x80074000
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| #define REGS_DRI_SIZE	0x2000
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| 
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| #define HW_DRI_CTRL		0x0
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| #define BM_DRI_CTRL_RUN		0x00000001
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| #define BP_DRI_CTRL_RUN		0
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| #define BM_DRI_CTRL_ATTENTION_IRQ	0x00000002
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| #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ	0x00000004
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| #define BM_DRI_CTRL_OVERFLOW_IRQ	0x00000008
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| #define BM_DRI_CTRL_ATTENTION_IRQ_EN	0x00000200
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| #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN	0x00000400
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| #define BM_DRI_CTRL_OVERFLOW_IRQ_EN	0x00000800
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| #define BM_DRI_CTRL_REACQUIRE_PHASE	0x00008000
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| #define BM_DRI_CTRL_STOP_ON_PILOT_ERROR	0x02000000
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| #define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR	0x04000000
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| #define BM_DRI_CTRL_ENABLE_INPUTS	0x20000000
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| #define BM_DRI_CTRL_CLKGATE	0x40000000
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| #define BM_DRI_CTRL_SFTRST	0x80000000
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| 
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| #define HW_DRI_TIMING		0x10
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| #define BM_DRI_TIMING_GAP_DETECTION_INTERVAL	0x000000FF
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| #define BP_DRI_TIMING_GAP_DETECTION_INTERVAL	0
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| #define BM_DRI_TIMING_PILOT_REP_RATE	0x000F0000
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| #define BP_DRI_TIMING_PILOT_REP_RATE	16
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