185 lines
5.6 KiB
C
185 lines
5.6 KiB
C
/* arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* The MSM peripherals are spread all over across 768MB of physical
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* space, which makes just having a simple IO_ADDRESS macro to slide
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* them into the right virtual location rough. Instead, we will
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* provide a master phys->virt mapping for peripherals here.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
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#define __ASM_ARCH_MSM_IOMAP_8X50_H
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#define MSM_VIC_BASE IOMEM(0xF8000000)
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#define MSM_VIC_PHYS 0xAC000000
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#define MSM_VIC_SIZE SZ_4K
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#define MSM_CSR_BASE IOMEM(0xF8001000)
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#define MSM_CSR_PHYS 0xAC100000
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#define MSM_CSR_SIZE SZ_4K
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#define MSM_GPT_PHYS MSM_CSR_PHYS
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#define MSM_GPT_BASE MSM_CSR_BASE
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#define MSM_GPT_SIZE SZ_4K
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#define MSM_DMOV_BASE IOMEM(0xF8002000)
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#define MSM_DMOV_PHYS 0xA9700000
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#define MSM_DMOV_SIZE SZ_4K
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#define MSM_GPIO1_BASE IOMEM(0xF8003000)
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#define MSM_GPIO1_PHYS 0xA9000000
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#define MSM_GPIO1_SIZE SZ_4K
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#define MSM_GPIO2_BASE IOMEM(0xF8004000)
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#define MSM_GPIO2_PHYS 0xA9100000
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#define MSM_GPIO2_SIZE SZ_4K
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#define MSM_GPIOCFG1_BASE IOMEM(0xF9004000)
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#define MSM_GPIOCFG1_PHYS 0xA8E00000
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#define MSM_GPIOCFG1_SIZE SZ_4K
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#define MSM_GPIOCFG2_BASE IOMEM(0xF9005000)
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#define MSM_GPIOCFG2_PHYS 0xA8F00000
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#define MSM_GPIOCFG2_SIZE SZ_4K
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#define MSM_CLK_CTL_BASE IOMEM(0xF8005000)
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#define MSM_CLK_CTL_PHYS 0xA8600000
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#define MSM_CLK_CTL_SIZE SZ_4K
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#define MSM_CLK_CTL_SH2_BASE IOMEM(0xF8006000)
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#define MSM_CLK_CTL_SH2_PHYS 0xABA01000
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#define MSM_CLK_CTL_SH2_SIZE SZ_4K
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#define MSM_TS_BASE IOMEM(0xF9006000)
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#define MSM_TS_PHYS 0xAA300000
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#define MSM_TS_SIZE SZ_4K
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#define MSM_SSBI_BASE IOMEM(0xF9008000)
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#define MSM_SSBI_PHYS 0xA8100000
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#define MSM_SSBI_SIZE SZ_4K
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#define MSM_TSSC_BASE IOMEM(0xF9009000)
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#define MSM_TSSC_PHYS 0xAA300000
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#define MSM_TSSC_SIZE SZ_4K
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#define MSM_SHARED_RAM_BASE IOMEM(0xF8100000)
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#define MSM_SHARED_RAM_PHYS 0x00100000
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#define MSM_SHARED_RAM_SIZE SZ_1M
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#define MSM_UART1_PHYS 0xA9A00000
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#define MSM_UART1_SIZE SZ_4K
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#define MSM_UART2_PHYS 0xA9B00000
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#define MSM_UART2_SIZE SZ_4K
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#define MSM_UART3_PHYS 0xA9C00000
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#define MSM_UART3_SIZE SZ_4K
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#ifdef CONFIG_MSM_DEBUG_UART
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#define MSM_DEBUG_UART_BASE 0xF9000000
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#if CONFIG_MSM_DEBUG_UART == 1
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#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
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#elif CONFIG_MSM_DEBUG_UART == 2
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#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
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#elif CONFIG_MSM_DEBUG_UART == 3
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#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
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#endif
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#define MSM_DEBUG_UART_SIZE SZ_4K
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#endif
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#define MSM_SDC1_PHYS 0xA0300000
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#define MSM_SDC1_SIZE SZ_4K
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#define MSM_SDC2_BASE IOMEM(0xF800C000)
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#define MSM_SDC2_PHYS 0xA0400000
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#define MSM_SDC2_SIZE SZ_4K
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#define MSM_SDC3_PHYS 0xA0500000
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#define MSM_SDC3_SIZE SZ_4K
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#define MSM_SDC4_PHYS 0xA0600000
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#define MSM_SDC4_SIZE SZ_4K
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#define MSM_I2C_PHYS 0xA9900000
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#define MSM_I2C_SIZE SZ_4K
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#define MSM_HSUSB_PHYS 0xA0800000
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#define MSM_HSUSB_SIZE SZ_4K
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#define MSM_PMDH_PHYS 0xAA600000
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#define MSM_PMDH_SIZE SZ_4K
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#define MSM_EMDH_PHYS 0xAA700000
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#define MSM_EMDH_SIZE SZ_4K
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#define MSM_MDP_PHYS 0xAA200000
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#define MSM_MDP_SIZE 0x000F0000
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#define MSM_MDC_BASE IOMEM(0xF8200000)
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#define MSM_MDC_PHYS 0xAA500000
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#define MSM_MDC_SIZE SZ_1M
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#define MSM_AD5_BASE IOMEM(0xF8300000)
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#define MSM_AD5_PHYS 0xAC000000
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#define MSM_AD5_SIZE (SZ_1M*13)
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#define MSM_VFE_PHYS 0xA0F00000
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#define MSM_VFE_SIZE SZ_1M
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#define MSM_UART1DM_PHYS 0xA0200000
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#define MSM_UART2DM_PHYS 0xA0300000
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#define MSM_SIRC_BASE IOMEM(0xF8006000)
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#define MSM_SIRC_PHYS 0xAC200000
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#define MSM_SIRC_SIZE SZ_4K
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#define MSM_SCPLL_BASE IOMEM(0xF8007000)
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#define MSM_SCPLL_PHYS 0xA8800000
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#define MSM_SCPLL_SIZE SZ_4K
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#if defined(CONFIG_CACHE_L2X0)
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#define MSM_L2CC_BASE IOMEM(0xF8008000)
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#define MSM_L2CC_PHYS 0xC0400000
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#define MSM_L2CC_SIZE SZ_4K
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#endif
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#define MSM_GPU_REG_PHYS 0xA0000000
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#define MSM_GPU_REG_SIZE 0x00020000
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#define MSM_SPI_PHYS 0xA1200000
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#define MSM_SPI_SIZE SZ_4K
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#define MSM_TCSR_BASE IOMEM(0xF8008000)
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#define MSM_TCSR_PHYS 0xA8700000
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#define MSM_TCSR_SIZE SZ_4K
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#endif
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// Originally this does not need to be defined,
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// but is required to make early_ramconsole work.
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// These values must match the values used in
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// the defconfig.
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#define MSM_RAM_CONSOLE_BASE IOMEM(0xF9100000)
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#if defined(CONFIG_USING_BRAVOS_DSP)
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#define MSM_RAM_CONSOLE_PHYS 0x2E7C0000
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#else
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#define MSM_RAM_CONSOLE_PHYS 0x2FFC0000
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#endif
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#define MSM_RAM_CONSOLE_SIZE 0x00040000
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// For reading the real WiFi MAC address
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#define MSM_SPLHOOD_BASE IOMEM(0xF9200000)
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#define MSM_SPLHOOD_PHYS 0x0
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#define MSM_SPLHOOD_SIZE SZ_1M
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