214 lines
8.5 KiB
C
214 lines
8.5 KiB
C
/*
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* Include file private to the SOC Interconnect support files.
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*
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* Copyright (C) 1999-2010, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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* $Id: siutils_priv.h,v 1.3.10.5.4.2 2009/09/22 13:28:16 Exp $
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*/
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#ifndef _siutils_priv_h_
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#define _siutils_priv_h_
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/* debug/trace */
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#define SI_ERROR(args)
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#define SI_MSG(args)
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#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
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typedef uint32 (*si_intrsoff_t)(void *intr_arg);
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typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
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typedef bool (*si_intrsenabled_t)(void *intr_arg);
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typedef struct gpioh_item {
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void *arg;
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bool level;
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gpio_handler_t handler;
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uint32 event;
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struct gpioh_item *next;
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} gpioh_item_t;
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/* misc si info needed by some of the routines */
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typedef struct si_common_info {
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void *regs[SI_MAXCORES]; /* other regs va */
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void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
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uint coreid[SI_MAXCORES]; /* id of each core */
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uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
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uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
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uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
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uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
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uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
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uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
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void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
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uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
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uint32 oob_router; /* oob router registers for axi */
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uint8 attach_count;
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} si_common_info_t;
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typedef struct si_info {
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struct si_pub pub; /* back plane public state (must be first field) */
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void *osh; /* osl os handle */
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void *sdh; /* bcmsdh handle */
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void *pch; /* PCI/E core handle */
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uint dev_coreid; /* the core provides driver functions */
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void *intr_arg; /* interrupt callback function arg */
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si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
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si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
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si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
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gpioh_item_t *gpioh_head; /* GPIO event handlers list */
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bool memseg; /* flag to toggle MEM_SEG register */
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char *vars;
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uint varsz;
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void *curmap; /* current regs va */
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uint curidx; /* current core index */
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uint numcores; /* # discovered cores */
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void *curwrap; /* current wrapper va */
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si_common_info_t *common_info; /* Common information for all the cores in a chip */
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} si_info_t;
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#define SI_INFO(sih) (si_info_t *)(uintptr)sih
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#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
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ISALIGNED((x), SI_CORE_SIZE))
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#define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
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#define BADCOREADDR 0
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#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
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#define BADIDX (SI_MAXCORES + 1)
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#define NOREV -1 /* Invalid rev */
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#define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
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((si)->pub.buscoretype == PCI_CORE_ID))
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#define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
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((si)->pub.buscoretype == PCIE_CORE_ID))
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#define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
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/* Newer chips can access PCI/PCIE and CC core without requiring to change
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* PCI BAR0 WIN
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*/
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#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
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(((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
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#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
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#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
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/*
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* Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
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* after core switching to avoid invalid register accesss inside ISR.
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*/
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#define INTR_OFF(si, intr_val) \
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if ((si)->intrsoff_fn && (si)->common_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
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intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
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#define INTR_RESTORE(si, intr_val) \
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if ((si)->intrsrestore_fn && (si)->common_info->coreid[(si)->curidx] == (si)->dev_coreid) {\
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(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
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/* dynamic clock control defines */
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#define LPOMINFREQ 25000 /* low power oscillator min */
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#define LPOMAXFREQ 43000 /* low power oscillator max */
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#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
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#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
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#define PCIMINFREQ 25000000 /* 25 MHz */
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#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
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#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
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#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
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#define PCI_FORCEHT(si) \
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(((PCIE(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \
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((PCI(si) || PCIE(si)) && (si->pub.chip == BCM4321_CHIP_ID)))
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/* GPIO Based LED powersave defines */
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#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
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#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
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#ifndef DEFAULT_GPIOTIMERVAL
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#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
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#endif
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/* Silicon Backplane externs */
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extern void sb_scan(si_t *sih, void *regs, uint devid);
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extern uint sb_coreid(si_t *sih);
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extern uint sb_flag(si_t *sih);
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extern void sb_setint(si_t *sih, int siflag);
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extern uint sb_corevendor(si_t *sih);
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extern uint sb_corerev(si_t *sih);
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extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
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extern bool sb_iscoreup(si_t *sih);
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extern void *sb_setcoreidx(si_t *sih, uint coreidx);
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extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
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extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
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extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
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extern void sb_commit(si_t *sih);
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extern uint32 sb_base(uint32 admatch);
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extern uint32 sb_size(uint32 admatch);
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extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
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extern void sb_core_tofixup(si_t *sih);
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extern void sb_core_disable(si_t *sih, uint32 bits);
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extern uint32 sb_addrspace(si_t *sih, uint asidx);
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extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
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extern int sb_numaddrspaces(si_t *sih);
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extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
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/* Wake-on-wireless-LAN (WOWL) */
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extern bool sb_pci_pmecap(si_t *sih);
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struct osl_info;
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extern bool sb_pci_fastpmecap(struct osl_info *osh);
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extern bool sb_pci_pmeclr(si_t *sih);
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extern void sb_pci_pmeen(si_t *sih);
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extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
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/* AMBA Interconnect exported externs */
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extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
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void *sdh, char **vars, uint *varsz);
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extern si_t *ai_kattach(osl_t *osh);
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extern void ai_scan(si_t *sih, void *regs, uint devid);
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extern uint ai_flag(si_t *sih);
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extern void ai_setint(si_t *sih, int siflag);
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extern uint ai_coreidx(si_t *sih);
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extern uint ai_corevendor(si_t *sih);
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extern uint ai_corerev(si_t *sih);
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extern bool ai_iscoreup(si_t *sih);
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extern void *ai_setcoreidx(si_t *sih, uint coreidx);
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extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
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extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
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extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
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extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
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extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
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extern void ai_core_disable(si_t *sih, uint32 bits);
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extern int ai_numaddrspaces(si_t *sih);
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extern uint32 ai_addrspace(si_t *sih, uint asidx);
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extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
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extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val);
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#endif /* _siutils_priv_h_ */
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