386 lines
9.8 KiB
C
386 lines
9.8 KiB
C
/*
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* SL82C105/Winbond 553 IDE driver
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*
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* Maintainer unknown.
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*
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* Drive tuning added from Rebel.com's kernel sources
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* -- Russell King (15/11/98) linux@arm.linux.org.uk
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*
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* Merge in Russell's HW workarounds, fix various problems
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* with the timing registers setup.
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* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
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*
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* Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#define DRV_NAME "sl82c105"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(arg) printk arg
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#else
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#define DBG(fmt,...)
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#endif
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/*
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* SL82C105 PCI config register 0x40 bits.
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*/
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#define CTRL_IDE_IRQB (1 << 30)
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#define CTRL_IDE_IRQA (1 << 28)
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#define CTRL_LEGIRQ (1 << 11)
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#define CTRL_P1F16 (1 << 5)
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#define CTRL_P1EN (1 << 4)
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#define CTRL_P0F16 (1 << 1)
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#define CTRL_P0EN (1 << 0)
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/*
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* Convert a PIO mode and cycle time to the required on/off times
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* for the interface. This has protection against runaway timings.
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*/
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static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
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{
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struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
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unsigned int cmd_on, cmd_off;
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u8 iordy = 0;
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cmd_on = (t->active + 29) / 30;
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cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
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if (cmd_on == 0)
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cmd_on = 1;
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if (cmd_off == 0)
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cmd_off = 1;
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if (ide_pio_need_iordy(drive, pio))
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iordy = 0x40;
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return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
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}
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/*
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* Configure the chipset for PIO mode.
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*/
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static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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unsigned long timings = (unsigned long)ide_get_drivedata(drive);
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int reg = 0x44 + drive->dn * 4;
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u16 drv_ctrl;
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drv_ctrl = get_pio_timings(drive, pio);
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/*
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* Store the PIO timings so that we can restore them
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* in case DMA will be turned off...
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*/
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timings &= 0xffff0000;
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timings |= drv_ctrl;
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ide_set_drivedata(drive, (void *)timings);
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pci_write_config_word(dev, reg, drv_ctrl);
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pci_read_config_word (dev, reg, &drv_ctrl);
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printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
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ide_xfer_verbose(pio + XFER_PIO_0),
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ide_pio_cycle_time(drive, pio), drv_ctrl);
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}
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/*
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* Configure the chipset for DMA mode.
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*/
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static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
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unsigned long timings = (unsigned long)ide_get_drivedata(drive);
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u16 drv_ctrl;
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DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
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drive->name, ide_xfer_verbose(speed)));
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drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
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/*
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* Store the DMA timings so that we can actually program
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* them when DMA will be turned on...
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*/
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timings &= 0x0000ffff;
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timings |= (unsigned long)drv_ctrl << 16;
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ide_set_drivedata(drive, (void *)timings);
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}
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static int sl82c105_test_irq(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
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pci_read_config_dword(dev, 0x40, &val);
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return (val & mask) ? 1 : 0;
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}
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/*
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* The SL82C105 holds off all IDE interrupts while in DMA mode until
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* all DMA activity is completed. Sometimes this causes problems (eg,
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* when the drive wants to report an error condition).
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*
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* 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
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* state machine. We need to kick this to work around various bugs.
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*/
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static inline void sl82c105_reset_host(struct pci_dev *dev)
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{
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u16 val;
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pci_read_config_word(dev, 0x7e, &val);
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pci_write_config_word(dev, 0x7e, val | (1 << 2));
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pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
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}
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/*
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* If we get an IRQ timeout, it might be that the DMA state machine
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* got confused. Fix from Todd Inglett. Details from Winbond.
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*
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* This function is called when the IDE timer expires, the drive
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* indicates that it is READY, and we were waiting for DMA to complete.
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*/
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static void sl82c105_dma_lost_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
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u8 dma_cmd;
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printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n");
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/*
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* Check the raw interrupt from the drive.
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*/
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pci_read_config_dword(dev, 0x40, &val);
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if (val & mask)
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printk(KERN_INFO "sl82c105: drive was requesting IRQ, "
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"but host lost it\n");
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/*
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* Was DMA enabled? If so, disable it - we're resetting the
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* host. The IDE layer will be handling the drive for us.
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*/
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dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
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if (dma_cmd & 1) {
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outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
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printk(KERN_INFO "sl82c105: DMA was enabled\n");
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}
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sl82c105_reset_host(dev);
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}
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/*
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* ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
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* Winbond recommend that the DMA state machine is reset prior to
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* setting the bus master DMA enable bit.
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*
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* The generic IDE core will have disabled the BMEN bit before this
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* function is called.
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*/
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static void sl82c105_dma_start(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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int reg = 0x44 + drive->dn * 4;
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DBG(("%s(drive:%s)\n", __func__, drive->name));
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pci_write_config_word(dev, reg,
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(unsigned long)ide_get_drivedata(drive) >> 16);
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sl82c105_reset_host(dev);
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ide_dma_start(drive);
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}
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static void sl82c105_dma_clear(ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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DBG(("sl82c105_dma_clear(drive:%s)\n", drive->name));
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sl82c105_reset_host(dev);
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}
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static int sl82c105_dma_end(ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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int reg = 0x44 + drive->dn * 4;
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int ret;
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DBG(("%s(drive:%s)\n", __func__, drive->name));
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ret = ide_dma_end(drive);
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pci_write_config_word(dev, reg,
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(unsigned long)ide_get_drivedata(drive));
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return ret;
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}
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/*
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* ATA reset will clear the 16 bits mode in the control
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* register, we need to reprogram it
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*/
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static void sl82c105_resetproc(ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u32 val;
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DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
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pci_read_config_dword(dev, 0x40, &val);
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val |= (CTRL_P1F16 | CTRL_P0F16);
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pci_write_config_dword(dev, 0x40, val);
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}
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/*
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* Return the revision of the Winbond bridge
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* which this function is part of.
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*/
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static u8 sl82c105_bridge_revision(struct pci_dev *dev)
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{
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struct pci_dev *bridge;
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/*
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* The bridge should be part of the same device, but function 0.
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*/
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bridge = pci_get_bus_and_slot(dev->bus->number,
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PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
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if (!bridge)
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return -1;
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/*
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* Make sure it is a Winbond 553 and is an ISA bridge.
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*/
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if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
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bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
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bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
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pci_dev_put(bridge);
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return -1;
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}
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/*
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* We need to find function 0's revision, not function 1
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*/
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pci_dev_put(bridge);
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return bridge->revision;
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}
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/*
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* Enable the PCI device
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*
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* --BenH: It's arch fixup code that should enable channels that
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* have not been enabled by firmware. I decided we can still enable
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* channel 0 here at least, but channel 1 has to be enabled by
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* firmware or arch code. We still set both to 16 bits mode.
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*/
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static int init_chipset_sl82c105(struct pci_dev *dev)
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{
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u32 val;
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DBG(("init_chipset_sl82c105()\n"));
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pci_read_config_dword(dev, 0x40, &val);
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val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
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pci_write_config_dword(dev, 0x40, val);
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return 0;
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}
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static const struct ide_port_ops sl82c105_port_ops = {
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.set_pio_mode = sl82c105_set_pio_mode,
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.set_dma_mode = sl82c105_set_dma_mode,
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.resetproc = sl82c105_resetproc,
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.test_irq = sl82c105_test_irq,
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};
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static const struct ide_dma_ops sl82c105_dma_ops = {
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.dma_host_set = ide_dma_host_set,
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.dma_setup = ide_dma_setup,
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.dma_start = sl82c105_dma_start,
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.dma_end = sl82c105_dma_end,
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.dma_test_irq = ide_dma_test_irq,
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.dma_lost_irq = sl82c105_dma_lost_irq,
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.dma_timer_expiry = ide_dma_sff_timer_expiry,
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.dma_clear = sl82c105_dma_clear,
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.dma_sff_read_status = ide_dma_sff_read_status,
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};
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static const struct ide_port_info sl82c105_chipset __devinitdata = {
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.name = DRV_NAME,
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.init_chipset = init_chipset_sl82c105,
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.enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
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.port_ops = &sl82c105_port_ops,
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.dma_ops = &sl82c105_dma_ops,
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.host_flags = IDE_HFLAG_IO_32BIT |
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IDE_HFLAG_UNMASK_IRQS |
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IDE_HFLAG_SERIALIZE_DMA |
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IDE_HFLAG_NO_AUTODMA,
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.pio_mask = ATA_PIO5,
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.mwdma_mask = ATA_MWDMA2,
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};
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static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct ide_port_info d = sl82c105_chipset;
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u8 rev = sl82c105_bridge_revision(dev);
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if (rev <= 5) {
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/*
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* Never ever EVER under any circumstances enable
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* DMA when the bridge is this old.
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*/
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printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge "
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"revision %d, BM-DMA disabled\n", rev);
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d.dma_ops = NULL;
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d.mwdma_mask = 0;
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d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA;
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}
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return ide_pci_init_one(dev, &d, NULL);
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}
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static const struct pci_device_id sl82c105_pci_tbl[] = {
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{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
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static struct pci_driver sl82c105_pci_driver = {
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.name = "W82C105_IDE",
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.id_table = sl82c105_pci_tbl,
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.probe = sl82c105_init_one,
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.remove = ide_pci_remove,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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static int __init sl82c105_ide_init(void)
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{
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return ide_pci_register_driver(&sl82c105_pci_driver);
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}
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static void __exit sl82c105_ide_exit(void)
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{
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pci_unregister_driver(&sl82c105_pci_driver);
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}
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module_init(sl82c105_ide_init);
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module_exit(sl82c105_ide_exit);
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MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
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MODULE_LICENSE("GPL");
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