56 lines
1.9 KiB
C
56 lines
1.9 KiB
C
/*
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* Copyright 2007-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_BLACKFIN_H_
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#define _MACH_BLACKFIN_H_
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#include "bf527.h"
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#include "defBF522.h"
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#include "anomaly.h"
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#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
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#include "defBF527.h"
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#endif
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#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
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#include "defBF525.h"
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#endif
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#if !defined(__ASSEMBLY__)
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#include "cdefBF522.h"
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#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
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#include "cdefBF527.h"
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#endif
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#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
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#include "cdefBF525.h"
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#endif
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#endif
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#define BFIN_UART_NR_PORTS 2
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#define OFFSET_THR 0x00 /* Transmit Holding register */
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#define OFFSET_RBR 0x00 /* Receive Buffer register */
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#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
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#define OFFSET_IER 0x04 /* Interrupt Enable Register */
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#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
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#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
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#define OFFSET_LCR 0x0C /* Line Control Register */
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#define OFFSET_MCR 0x10 /* Modem Control Register */
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#define OFFSET_LSR 0x14 /* Line Status Register */
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#define OFFSET_MSR 0x18 /* Modem Status Register */
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#define OFFSET_SCR 0x1C /* SCR Scratch Register */
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#define OFFSET_GCTL 0x24 /* Global Control Register */
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/* PLL_DIV Masks */
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#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
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#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
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#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
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#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
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#endif
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