325 lines
7.8 KiB
C
325 lines
7.8 KiB
C
/*
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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* Added mmcra[slot] support:
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* Copyright (C) 2006-2007 Will Schmidt <willschm@us.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/oprofile.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/firmware.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/rtas.h>
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#include <asm/oprofile_impl.h>
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#include <asm/reg.h>
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#define dbg(args...)
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static unsigned long reset_value[OP_MAX_COUNTER];
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static int oprofile_running;
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static int use_slot_nums;
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/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
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static u32 mmcr0_val;
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static u64 mmcr1_val;
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static u64 mmcra_val;
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static int power4_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys,
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int num_ctrs)
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{
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int i;
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/*
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* The performance counter event settings are given in the mmcr0,
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* mmcr1 and mmcra values passed from the user in the
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* op_system_config structure (sys variable).
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*/
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mmcr0_val = sys->mmcr0;
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mmcr1_val = sys->mmcr1;
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mmcra_val = sys->mmcra;
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for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
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reset_value[i] = 0x80000000UL - ctr[i].count;
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/* setup user and kernel profiling */
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if (sys->enable_kernel)
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mmcr0_val &= ~MMCR0_KERNEL_DISABLE;
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else
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mmcr0_val |= MMCR0_KERNEL_DISABLE;
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if (sys->enable_user)
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mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;
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else
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mmcr0_val |= MMCR0_PROBLEM_DISABLE;
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if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
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__is_processor(PV_970) || __is_processor(PV_970FX) ||
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__is_processor(PV_970MP) || __is_processor(PV_970GX) ||
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__is_processor(PV_POWER5) || __is_processor(PV_POWER5p))
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use_slot_nums = 1;
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return 0;
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}
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extern void ppc_enable_pmcs(void);
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/*
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* Older CPUs require the MMCRA sample bit to be always set, but newer
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* CPUs only want it set for some groups. Eventually we will remove all
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* knowledge of this bit in the kernel, oprofile userspace should be
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* setting it when required.
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*
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* In order to keep current installations working we force the bit for
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* those older CPUs. Once everyone has updated their oprofile userspace we
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* can remove this hack.
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*/
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static inline int mmcra_must_set_sample(void)
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{
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if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
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__is_processor(PV_970) || __is_processor(PV_970FX) ||
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__is_processor(PV_970MP) || __is_processor(PV_970GX))
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return 1;
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return 0;
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}
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static int power4_cpu_setup(struct op_counter_config *ctr)
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{
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unsigned int mmcr0 = mmcr0_val;
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unsigned long mmcra = mmcra_val;
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ppc_enable_pmcs();
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/* set the freeze bit */
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mmcr0 |= MMCR0_FC;
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mtspr(SPRN_MMCR0, mmcr0);
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mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
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mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
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mtspr(SPRN_MMCR0, mmcr0);
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mtspr(SPRN_MMCR1, mmcr1_val);
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if (mmcra_must_set_sample())
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mmcra |= MMCRA_SAMPLE_ENABLE;
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mtspr(SPRN_MMCRA, mmcra);
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dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
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mfspr(SPRN_MMCR0));
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dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
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mfspr(SPRN_MMCR1));
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dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
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mfspr(SPRN_MMCRA));
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return 0;
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}
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static int power4_start(struct op_counter_config *ctr)
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{
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int i;
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unsigned int mmcr0;
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/* set the PMM bit (see comment below) */
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mtmsrd(mfmsr() | MSR_PMM);
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for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
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if (ctr[i].enabled) {
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classic_ctr_write(i, reset_value[i]);
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} else {
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classic_ctr_write(i, 0);
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}
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}
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mmcr0 = mfspr(SPRN_MMCR0);
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/*
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* We must clear the PMAO bit on some (GQ) chips. Just do it
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* all the time
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*/
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mmcr0 &= ~MMCR0_PMAO;
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/*
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* now clear the freeze bit, counting will not start until we
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* rfid from this excetion, because only at that point will
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* the PMM bit be cleared
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*/
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mmcr0 &= ~MMCR0_FC;
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mtspr(SPRN_MMCR0, mmcr0);
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oprofile_running = 1;
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dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
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return 0;
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}
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static void power4_stop(void)
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{
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unsigned int mmcr0;
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/* freeze counters */
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mmcr0 = mfspr(SPRN_MMCR0);
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mmcr0 |= MMCR0_FC;
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mtspr(SPRN_MMCR0, mmcr0);
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oprofile_running = 0;
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dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
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mb();
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}
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/* Fake functions used by canonicalize_pc */
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static void __used hypervisor_bucket(void)
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{
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}
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static void __used rtas_bucket(void)
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{
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}
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static void __used kernel_unknown_bucket(void)
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{
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}
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/*
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* On GQ and newer the MMCRA stores the HV and PR bits at the time
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* the SIAR was sampled. We use that to work out if the SIAR was sampled in
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* the hypervisor, our exception vectors or RTAS.
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* If the MMCRA_SAMPLE_ENABLE bit is set, we can use the MMCRA[slot] bits
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* to more accurately identify the address of the sampled instruction. The
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* mmcra[slot] bits represent the slot number of a sampled instruction
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* within an instruction group. The slot will contain a value between 1
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* and 5 if MMCRA_SAMPLE_ENABLE is set, otherwise 0.
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*/
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static unsigned long get_pc(struct pt_regs *regs)
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{
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unsigned long pc = mfspr(SPRN_SIAR);
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unsigned long mmcra;
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unsigned long slot;
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/* Cant do much about it */
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if (!cur_cpu_spec->oprofile_mmcra_sihv)
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return pc;
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mmcra = mfspr(SPRN_MMCRA);
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if (use_slot_nums && (mmcra & MMCRA_SAMPLE_ENABLE)) {
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slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
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if (slot > 1)
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pc += 4 * (slot - 1);
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}
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/* Were we in the hypervisor? */
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if (firmware_has_feature(FW_FEATURE_LPAR) &&
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(mmcra & cur_cpu_spec->oprofile_mmcra_sihv))
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/* function descriptor madness */
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return *((unsigned long *)hypervisor_bucket);
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/* We were in userspace, nothing to do */
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if (mmcra & cur_cpu_spec->oprofile_mmcra_sipr)
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return pc;
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#ifdef CONFIG_PPC_RTAS
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/* Were we in RTAS? */
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if (pc >= rtas.base && pc < (rtas.base + rtas.size))
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/* function descriptor madness */
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return *((unsigned long *)rtas_bucket);
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#endif
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/* Were we in our exception vectors or SLB real mode miss handler? */
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if (pc < 0x1000000UL)
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return (unsigned long)__va(pc);
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/* Not sure where we were */
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if (!is_kernel_addr(pc))
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/* function descriptor madness */
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return *((unsigned long *)kernel_unknown_bucket);
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return pc;
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}
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static int get_kernel(unsigned long pc, unsigned long mmcra)
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{
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int is_kernel;
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if (!cur_cpu_spec->oprofile_mmcra_sihv) {
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is_kernel = is_kernel_addr(pc);
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} else {
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is_kernel = ((mmcra & cur_cpu_spec->oprofile_mmcra_sipr) == 0);
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}
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return is_kernel;
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}
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static void power4_handle_interrupt(struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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unsigned long pc;
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int is_kernel;
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int val;
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int i;
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unsigned int mmcr0;
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unsigned long mmcra;
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mmcra = mfspr(SPRN_MMCRA);
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pc = get_pc(regs);
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is_kernel = get_kernel(pc, mmcra);
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/* set the PMM bit (see comment below) */
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mtmsrd(mfmsr() | MSR_PMM);
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for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
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val = classic_ctr_read(i);
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if (val < 0) {
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if (oprofile_running && ctr[i].enabled) {
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oprofile_add_ext_sample(pc, regs, i, is_kernel);
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classic_ctr_write(i, reset_value[i]);
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} else {
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classic_ctr_write(i, 0);
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}
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}
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}
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mmcr0 = mfspr(SPRN_MMCR0);
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/* reset the perfmon trigger */
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mmcr0 |= MMCR0_PMXE;
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/*
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* We must clear the PMAO bit on some (GQ) chips. Just do it
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* all the time
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*/
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mmcr0 &= ~MMCR0_PMAO;
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/* Clear the appropriate bits in the MMCRA */
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mmcra &= ~cur_cpu_spec->oprofile_mmcra_clear;
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mtspr(SPRN_MMCRA, mmcra);
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/*
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* now clear the freeze bit, counting will not start until we
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* rfid from this exception, because only at that point will
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* the PMM bit be cleared
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*/
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mmcr0 &= ~MMCR0_FC;
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mtspr(SPRN_MMCR0, mmcr0);
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}
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struct op_powerpc_model op_model_power4 = {
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.reg_setup = power4_reg_setup,
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.cpu_setup = power4_cpu_setup,
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.start = power4_start,
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.stop = power4_stop,
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.handle_interrupt = power4_handle_interrupt,
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};
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