644 lines
16 KiB
ArmAsm
644 lines
16 KiB
ArmAsm
/* head.S: kernel entry point for FR-V kernel
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*
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* Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/ptrace.h>
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#include <asm/page.h>
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#include <asm/spr-regs.h>
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#include <asm/mb86943a.h>
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#include <asm/cache.h>
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#include "head.inc"
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###############################################################################
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#
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# void _boot(unsigned long magic, char *command_line) __attribute__((noreturn))
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#
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# - if magic is 0xdead1eaf, then command_line is assumed to point to the kernel
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# command line string
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#
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###############################################################################
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__HEAD
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.balign 4
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.globl _boot, __head_reference
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.type _boot,@function
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_boot:
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__head_reference:
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sethi.p %hi(LED_ADDR),gr30
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setlo %lo(LED_ADDR),gr30
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LEDS 0x0000
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# calculate reference address for PC-relative stuff
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call 0f
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0: movsg lr,gr26
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addi gr26,#__head_reference-0b,gr26
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# invalidate and disable both of the caches and turn off the memory access checking
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dcef @(gr0,gr0),1
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bar
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sethi.p %hi(~(HSR0_ICE|HSR0_DCE|HSR0_CBM|HSR0_EIMMU|HSR0_EDMMU)),gr4
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setlo %lo(~(HSR0_ICE|HSR0_DCE|HSR0_CBM|HSR0_EIMMU|HSR0_EDMMU)),gr4
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movsg hsr0,gr5
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and gr4,gr5,gr5
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movgs gr5,hsr0
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movsg hsr0,gr5
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LEDS 0x0001
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icei @(gr0,gr0),1
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dcei @(gr0,gr0),1
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bar
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# turn the instruction cache back on
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sethi.p %hi(HSR0_ICE),gr4
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setlo %lo(HSR0_ICE),gr4
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movsg hsr0,gr5
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or gr4,gr5,gr5
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movgs gr5,hsr0
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movsg hsr0,gr5
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bar
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LEDS 0x0002
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# retrieve the parameters (including command line) before we overwrite them
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sethi.p %hi(0xdead1eaf),gr7
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setlo %lo(0xdead1eaf),gr7
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subcc gr7,gr8,gr0,icc0
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bne icc0,#0,__head_no_parameters
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sethi.p %hi(redboot_command_line-1),gr6
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setlo %lo(redboot_command_line-1),gr6
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sethi.p %hi(__head_reference),gr4
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setlo %lo(__head_reference),gr4
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sub gr6,gr4,gr6
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add.p gr6,gr26,gr6
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subi gr9,#1,gr9
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setlos.p #511,gr4
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setlos #1,gr5
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__head_copy_cmdline:
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ldubu.p @(gr9,gr5),gr16
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subicc gr4,#1,gr4,icc0
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stbu.p gr16,@(gr6,gr5)
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subicc gr16,#0,gr0,icc1
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bls icc0,#0,__head_end_cmdline
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bne icc1,#1,__head_copy_cmdline
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__head_end_cmdline:
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stbu gr0,@(gr6,gr5)
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__head_no_parameters:
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###############################################################################
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#
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# we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
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# - note that we're going to have to run entirely out of the icache whilst
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# fiddling with the SDRAM controller registers
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#
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###############################################################################
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#ifdef CONFIG_MMU
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call __head_fr451_describe_sdram
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#else
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movsg psr,gr5
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srli gr5,#28,gr5
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subicc gr5,#3,gr0,icc0
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beq icc0,#0,__head_fr551_sdram
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call __head_fr401_describe_sdram
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bra __head_do_sdram
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__head_fr551_sdram:
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call __head_fr555_describe_sdram
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LEDS 0x000d
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__head_do_sdram:
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#endif
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# preload the registers with invalid values in case any DBR/DARS are marked not present
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sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
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setlo %lo(0xfe000000),gr17
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or.p gr17,gr0,gr20
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or gr17,gr0,gr21
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or.p gr17,gr0,gr22
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or gr17,gr0,gr23
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# consult the SDRAM controller CS address registers
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cld @(gr14,gr0 ),gr20, cc0,#1 ; DBR0 / DARS0
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cld @(gr14,gr11),gr21, cc1,#1 ; DBR1 / DARS1
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cld @(gr14,gr12),gr22, cc2,#1 ; DBR2 / DARS2
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cld.p @(gr14,gr13),gr23, cc3,#1 ; DBR3 / DARS3
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sll gr20,gr15,gr20 ; shift values up for FR551
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sll gr21,gr15,gr21
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sll gr22,gr15,gr22
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sll gr23,gr15,gr23
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LEDS 0x0003
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# assume the lowest valid CS line to be the SDRAM base and get its address
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subcc gr20,gr17,gr0,icc0
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subcc.p gr21,gr17,gr0,icc1
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subcc gr22,gr17,gr0,icc2
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subcc.p gr23,gr17,gr0,icc3
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ckne icc0,cc4 ; T if DBR0 != 0xfe000000
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ckne icc1,cc5
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ckne icc2,cc6
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ckne icc3,cc7
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cor gr23,gr0,gr24, cc7,#1 ; GR24 = SDRAM base
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cor gr22,gr0,gr24, cc6,#1
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cor gr21,gr0,gr24, cc5,#1
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cor gr20,gr0,gr24, cc4,#1
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# calculate the displacement required to get the SDRAM into the right place in memory
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sethi.p %hi(__sdram_base),gr16
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setlo %lo(__sdram_base),gr16
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sub gr16,gr24,gr16 ; delta = __sdram_base - DBRx
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# calculate the new values to go in the controller regs
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cadd.p gr20,gr16,gr20, cc4,#1 ; DCS#0 (new) = DCS#0 (old) + delta
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cadd gr21,gr16,gr21, cc5,#1
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cadd.p gr22,gr16,gr22, cc6,#1
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cadd gr23,gr16,gr23, cc7,#1
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srl gr20,gr15,gr20 ; shift values down for FR551
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srl gr21,gr15,gr21
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srl gr22,gr15,gr22
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srl gr23,gr15,gr23
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# work out the address at which the reg updater resides and lock it into icache
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# also work out the address the updater will jump to when finished
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sethi.p %hi(__head_move_sdram-__head_reference),gr18
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setlo %lo(__head_move_sdram-__head_reference),gr18
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sethi.p %hi(__head_sdram_moved-__head_reference),gr19
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setlo %lo(__head_sdram_moved-__head_reference),gr19
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add.p gr18,gr26,gr18
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add gr19,gr26,gr19
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add.p gr19,gr16,gr19 ; moved = addr + (__sdram_base - DBRx)
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add gr18,gr5,gr4 ; two cachelines probably required
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icpl gr18,gr0,#1 ; load and lock the cachelines
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icpl gr4,gr0,#1
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LEDS 0x0004
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membar
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bar
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jmpl @(gr18,gr0)
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.balign L1_CACHE_BYTES
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__head_move_sdram:
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cst gr20,@(gr14,gr0 ), cc4,#1
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cst gr21,@(gr14,gr11), cc5,#1
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cst gr22,@(gr14,gr12), cc6,#1
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cst gr23,@(gr14,gr13), cc7,#1
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cld @(gr14,gr0 ),gr20, cc4,#1
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cld @(gr14,gr11),gr21, cc5,#1
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cld @(gr14,gr12),gr22, cc4,#1
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cld @(gr14,gr13),gr23, cc7,#1
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bar
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membar
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jmpl @(gr19,gr0)
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.balign L1_CACHE_BYTES
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__head_sdram_moved:
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icul gr18
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add gr18,gr5,gr4
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icul gr4
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icei @(gr0,gr0),1
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dcei @(gr0,gr0),1
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LEDS 0x0005
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# recalculate reference address
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call 0f
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0: movsg lr,gr26
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addi gr26,#__head_reference-0b,gr26
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###############################################################################
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#
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# move the kernel image down to the bottom of the SDRAM
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#
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###############################################################################
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sethi.p %hi(__kernel_image_size_no_bss+15),gr4
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setlo %lo(__kernel_image_size_no_bss+15),gr4
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srli.p gr4,#4,gr4 ; count
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or gr26,gr26,gr16 ; source
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sethi.p %hi(__sdram_base),gr17 ; destination
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setlo %lo(__sdram_base),gr17
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setlos #8,gr5
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sub.p gr16,gr5,gr16 ; adjust src for LDDU
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sub gr17,gr5,gr17 ; adjust dst for LDDU
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sethi.p %hi(__head_move_kernel-__head_reference),gr18
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setlo %lo(__head_move_kernel-__head_reference),gr18
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sethi.p %hi(__head_kernel_moved-__head_reference+__sdram_base),gr19
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setlo %lo(__head_kernel_moved-__head_reference+__sdram_base),gr19
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add gr18,gr26,gr18
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icpl gr18,gr0,#1
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jmpl @(gr18,gr0)
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.balign 32
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__head_move_kernel:
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lddu @(gr16,gr5),gr10
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lddu @(gr16,gr5),gr12
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stdu.p gr10,@(gr17,gr5)
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subicc gr4,#1,gr4,icc0
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stdu.p gr12,@(gr17,gr5)
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bhi icc0,#0,__head_move_kernel
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jmpl @(gr19,gr0)
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.balign 32
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__head_kernel_moved:
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icul gr18
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icei @(gr0,gr0),1
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dcei @(gr0,gr0),1
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LEDS 0x0006
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# recalculate reference address
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call 0f
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0: movsg lr,gr26
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addi gr26,#__head_reference-0b,gr26
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###############################################################################
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#
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# rearrange the iomem map and set the protection registers
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#
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###############################################################################
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#ifdef CONFIG_MMU
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LEDS 0x3301
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call __head_fr451_set_busctl
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LEDS 0x3303
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call __head_fr451_survey_sdram
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LEDS 0x3305
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call __head_fr451_set_protection
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#else
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movsg psr,gr5
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srli gr5,#PSR_IMPLE_SHIFT,gr5
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subicc gr5,#PSR_IMPLE_FR551,gr0,icc0
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beq icc0,#0,__head_fr555_memmap
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subicc gr5,#PSR_IMPLE_FR451,gr0,icc0
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beq icc0,#0,__head_fr451_memmap
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LEDS 0x3101
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call __head_fr401_set_busctl
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LEDS 0x3103
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call __head_fr401_survey_sdram
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LEDS 0x3105
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call __head_fr401_set_protection
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bra __head_done_memmap
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__head_fr451_memmap:
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LEDS 0x3301
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call __head_fr401_set_busctl
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LEDS 0x3303
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call __head_fr401_survey_sdram
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LEDS 0x3305
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call __head_fr451_set_protection
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bra __head_done_memmap
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__head_fr555_memmap:
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LEDS 0x3501
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call __head_fr555_set_busctl
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LEDS 0x3503
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call __head_fr555_survey_sdram
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LEDS 0x3505
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call __head_fr555_set_protection
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__head_done_memmap:
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#endif
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LEDS 0x0007
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###############################################################################
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#
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# turn the data cache and MMU on
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# - for the FR451 this'll mean that the window through which the kernel is
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# viewed will change
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#
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###############################################################################
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#ifdef CONFIG_MMU
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#define MMUMODE HSR0_EIMMU|HSR0_EDMMU|HSR0_EXMMU|HSR0_EDAT|HSR0_XEDAT
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#else
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#define MMUMODE HSR0_EIMMU|HSR0_EDMMU
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#endif
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movsg hsr0,gr5
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sethi.p %hi(MMUMODE),gr4
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setlo %lo(MMUMODE),gr4
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or gr4,gr5,gr5
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#if defined(CONFIG_FRV_DEFL_CACHE_WTHRU)
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sethi.p %hi(HSR0_DCE|HSR0_CBM_WRITE_THRU),gr4
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setlo %lo(HSR0_DCE|HSR0_CBM_WRITE_THRU),gr4
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#elif defined(CONFIG_FRV_DEFL_CACHE_WBACK)
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sethi.p %hi(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
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setlo %lo(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
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#elif defined(CONFIG_FRV_DEFL_CACHE_WBEHIND)
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sethi.p %hi(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
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setlo %lo(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
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movsg psr,gr6
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srli gr6,#24,gr6
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cmpi gr6,#0x50,icc0 // FR451
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beq icc0,#0,0f
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cmpi gr6,#0x40,icc0 // FR405
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bne icc0,#0,1f
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0:
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# turn off write-allocate
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sethi.p %hi(HSR0_NWA),gr6
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setlo %lo(HSR0_NWA),gr6
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or gr4,gr6,gr4
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1:
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#else
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#error No default cache configuration set
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#endif
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or gr4,gr5,gr5
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movgs gr5,hsr0
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bar
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LEDS 0x0008
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sethi.p %hi(__head_mmu_enabled),gr19
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setlo %lo(__head_mmu_enabled),gr19
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jmpl @(gr19,gr0)
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__head_mmu_enabled:
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icei @(gr0,gr0),#1
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dcei @(gr0,gr0),#1
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LEDS 0x0009
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#ifdef CONFIG_MMU
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call __head_fr451_finalise_protection
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#endif
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LEDS 0x000a
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###############################################################################
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#
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# set up the runtime environment
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#
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###############################################################################
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# clear the BSS area
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sethi.p %hi(__bss_start),gr4
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setlo %lo(__bss_start),gr4
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sethi.p %hi(_end),gr5
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setlo %lo(_end),gr5
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or.p gr0,gr0,gr18
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or gr0,gr0,gr19
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0:
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stdi gr18,@(gr4,#0)
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stdi gr18,@(gr4,#8)
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stdi gr18,@(gr4,#16)
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stdi.p gr18,@(gr4,#24)
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addi gr4,#24,gr4
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subcc gr5,gr4,gr0,icc0
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bhi icc0,#2,0b
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LEDS 0x000b
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# save the SDRAM details
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sethi.p %hi(__sdram_old_base),gr4
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setlo %lo(__sdram_old_base),gr4
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st gr24,@(gr4,gr0)
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sethi.p %hi(__sdram_base),gr5
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setlo %lo(__sdram_base),gr5
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sethi.p %hi(memory_start),gr4
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setlo %lo(memory_start),gr4
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st gr5,@(gr4,gr0)
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add gr25,gr5,gr25
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sethi.p %hi(memory_end),gr4
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setlo %lo(memory_end),gr4
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st gr25,@(gr4,gr0)
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# point the TBR at the kernel trap table
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sethi.p %hi(__entry_kerneltrap_table),gr4
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setlo %lo(__entry_kerneltrap_table),gr4
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movgs gr4,tbr
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# set up the exception frame for init
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sethi.p %hi(__kernel_frame0_ptr),gr28
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setlo %lo(__kernel_frame0_ptr),gr28
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sethi.p %hi(_gp),gr16
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setlo %lo(_gp),gr16
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sethi.p %hi(__entry_usertrap_table),gr4
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setlo %lo(__entry_usertrap_table),gr4
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lddi @(gr28,#0),gr28 ; load __frame & current
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ldi.p @(gr29,#4),gr15 ; set current_thread
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or gr0,gr0,fp
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or gr28,gr0,sp
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sti.p gr4,@(gr28,REG_TBR)
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setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
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movgs gr5,isr
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# turn on and off various CPU services
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movsg psr,gr22
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sethi.p %hi(#PSR_EM|PSR_EF|PSR_CM|PSR_NEM),gr4
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setlo %lo(#PSR_EM|PSR_EF|PSR_CM|PSR_NEM),gr4
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or gr22,gr4,gr22
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movgs gr22,psr
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andi gr22,#~(PSR_PIL|PSR_PS|PSR_S),gr22
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ori gr22,#PSR_ET,gr22
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sti gr22,@(gr28,REG_PSR)
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###############################################################################
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#
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# set up the registers and jump into the kernel
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#
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###############################################################################
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LEDS 0x000c
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# initialise the processor and the peripherals
|
|
#call SYMBOL_NAME(processor_init)
|
|
#call SYMBOL_NAME(unit_init)
|
|
#LEDS 0x0aff
|
|
|
|
sethi.p #0xe5e5,gr3
|
|
setlo #0xe5e5,gr3
|
|
or.p gr3,gr0,gr4
|
|
or gr3,gr0,gr5
|
|
or.p gr3,gr0,gr6
|
|
or gr3,gr0,gr7
|
|
or.p gr3,gr0,gr8
|
|
or gr3,gr0,gr9
|
|
or.p gr3,gr0,gr10
|
|
or gr3,gr0,gr11
|
|
or.p gr3,gr0,gr12
|
|
or gr3,gr0,gr13
|
|
or.p gr3,gr0,gr14
|
|
or gr3,gr0,gr17
|
|
or.p gr3,gr0,gr18
|
|
or gr3,gr0,gr19
|
|
or.p gr3,gr0,gr20
|
|
or gr3,gr0,gr21
|
|
or.p gr3,gr0,gr23
|
|
or gr3,gr0,gr24
|
|
or.p gr3,gr0,gr25
|
|
or gr3,gr0,gr26
|
|
or.p gr3,gr0,gr27
|
|
# or gr3,gr0,gr30
|
|
or gr3,gr0,gr31
|
|
movgs gr0,lr
|
|
movgs gr0,lcr
|
|
movgs gr0,ccr
|
|
movgs gr0,cccr
|
|
|
|
# initialise the virtual interrupt handling
|
|
subcc gr0,gr0,gr0,icc2 /* set Z, clear C */
|
|
|
|
#ifdef CONFIG_MMU
|
|
movgs gr3,scr2
|
|
movgs gr3,scr3
|
|
#endif
|
|
|
|
LEDS 0x0fff
|
|
|
|
# invoke the debugging stub if present
|
|
# - arch/frv/kernel/debug-stub.c will shift control directly to init/main.c
|
|
# (it will not return here)
|
|
break
|
|
.globl __debug_stub_init_break
|
|
__debug_stub_init_break:
|
|
|
|
# however, if you need to use an ICE, and don't care about using any userspace
|
|
# debugging tools (such as the ptrace syscall), you can just step over the break
|
|
# above and get to the kernel this way
|
|
# look at arch/frv/kernel/debug-stub.c: debug_stub_init() to see what you've missed
|
|
call start_kernel
|
|
|
|
.globl __head_end
|
|
__head_end:
|
|
.size _boot, .-_boot
|
|
|
|
# provide a point for GDB to place a break
|
|
.section .text.start,"ax"
|
|
.globl _start
|
|
.balign 4
|
|
_start:
|
|
call _boot
|
|
|
|
.previous
|
|
###############################################################################
|
|
#
|
|
# split a tile off of the region defined by GR8-GR9
|
|
#
|
|
# ENTRY: EXIT:
|
|
# GR4 - IAMPR value representing tile
|
|
# GR5 - DAMPR value representing tile
|
|
# GR6 - IAMLR value representing tile
|
|
# GR7 - DAMLR value representing tile
|
|
# GR8 region base pointer [saved]
|
|
# GR9 region top pointer updated to exclude new tile
|
|
# GR11 xAMLR mask [saved]
|
|
# GR25 SDRAM size [saved]
|
|
# GR30 LED address [saved]
|
|
#
|
|
# - GR8 and GR9 should be rounded up/down to the nearest megabyte before calling
|
|
#
|
|
###############################################################################
|
|
.globl __head_split_region
|
|
.type __head_split_region,@function
|
|
__head_split_region:
|
|
subcc.p gr9,gr8,gr4,icc0
|
|
setlos #31,gr5
|
|
scan.p gr4,gr0,gr6
|
|
beq icc0,#0,__head_region_empty
|
|
sub.p gr5,gr6,gr6 ; bit number of highest set bit (1MB=>20)
|
|
setlos #1,gr4
|
|
sll.p gr4,gr6,gr4 ; size of region (1 << bitno)
|
|
subi gr6,#17,gr6 ; 1MB => 0x03
|
|
slli.p gr6,#4,gr6 ; 1MB => 0x30
|
|
sub gr9,gr4,gr9 ; move uncovered top down
|
|
|
|
or gr9,gr6,gr4
|
|
ori gr4,#xAMPRx_S_USER|xAMPRx_C_CACHED|xAMPRx_V,gr4
|
|
or.p gr4,gr0,gr5
|
|
|
|
and gr4,gr11,gr6
|
|
and.p gr5,gr11,gr7
|
|
bralr
|
|
|
|
__head_region_empty:
|
|
or.p gr0,gr0,gr4
|
|
or gr0,gr0,gr5
|
|
or.p gr0,gr0,gr6
|
|
or gr0,gr0,gr7
|
|
bralr
|
|
.size __head_split_region, .-__head_split_region
|
|
|
|
###############################################################################
|
|
#
|
|
# write the 32-bit hex number in GR8 to ttyS0
|
|
#
|
|
###############################################################################
|
|
#if 0
|
|
.globl __head_write_to_ttyS0
|
|
.type __head_write_to_ttyS0,@function
|
|
__head_write_to_ttyS0:
|
|
sethi.p %hi(0xfeff9c00),gr31
|
|
setlo %lo(0xfeff9c00),gr31
|
|
setlos #8,gr20
|
|
|
|
0: ldubi @(gr31,#5*8),gr21
|
|
andi gr21,#0x60,gr21
|
|
subicc gr21,#0x60,gr21,icc0
|
|
bne icc0,#0,0b
|
|
|
|
1: srli gr8,#28,gr21
|
|
slli gr8,#4,gr8
|
|
|
|
addi gr21,#'0',gr21
|
|
subicc gr21,#'9',gr0,icc0
|
|
bls icc0,#2,2f
|
|
addi gr21,#'A'-'0'-10,gr21
|
|
2:
|
|
stbi gr21,@(gr31,#0*8)
|
|
subicc gr20,#1,gr20,icc0
|
|
bhi icc0,#2,1b
|
|
|
|
setlos #'\r',gr21
|
|
stbi gr21,@(gr31,#0*8)
|
|
|
|
setlos #'\n',gr21
|
|
stbi gr21,@(gr31,#0*8)
|
|
|
|
3: ldubi @(gr31,#5*8),gr21
|
|
andi gr21,#0x60,gr21
|
|
subicc gr21,#0x60,gr21,icc0
|
|
bne icc0,#0,3b
|
|
bralr
|
|
|
|
.size __head_write_to_ttyS0, .-__head_write_to_ttyS0
|
|
#endif
|