403 lines
10 KiB
C
403 lines
10 KiB
C
/*
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* linux/arch/arm/common/vic.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/sysdev.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/vic.h>
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static void vic_ack_irq(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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irq &= 31;
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writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
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/* moreover, clear the soft-triggered, in case it was the reason */
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writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
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}
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static void vic_mask_irq(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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irq &= 31;
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writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
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}
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static void vic_unmask_irq(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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irq &= 31;
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writel(1 << irq, base + VIC_INT_ENABLE);
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}
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/**
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* vic_init2 - common initialisation code
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* @base: Base of the VIC.
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*
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* Common initialisation code for registeration
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* and resume.
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*/
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static void vic_init2(void __iomem *base)
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{
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int i;
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for (i = 0; i < 16; i++) {
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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writel(VIC_VECT_CNTL_ENABLE | i, reg);
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}
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writel(32, base + VIC_PL190_DEF_VECT_ADDR);
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}
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#if defined(CONFIG_PM)
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/**
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* struct vic_device - VIC PM device
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* @sysdev: The system device which is registered.
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* @irq: The IRQ number for the base of the VIC.
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* @base: The register base for the VIC.
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* @resume_sources: A bitmask of interrupts for resume.
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* @resume_irqs: The IRQs enabled for resume.
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* @int_select: Save for VIC_INT_SELECT.
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* @int_enable: Save for VIC_INT_ENABLE.
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* @soft_int: Save for VIC_INT_SOFT.
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* @protect: Save for VIC_PROTECT.
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*/
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struct vic_device {
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struct sys_device sysdev;
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void __iomem *base;
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int irq;
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u32 resume_sources;
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u32 resume_irqs;
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u32 int_select;
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u32 int_enable;
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u32 soft_int;
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u32 protect;
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};
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/* we cannot allocate memory when VICs are initially registered */
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static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
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static inline struct vic_device *to_vic(struct sys_device *sys)
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{
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return container_of(sys, struct vic_device, sysdev);
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}
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static int vic_id;
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static int vic_class_resume(struct sys_device *dev)
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{
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struct vic_device *vic = to_vic(dev);
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void __iomem *base = vic->base;
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printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
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/* re-initialise static settings */
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vic_init2(base);
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writel(vic->int_select, base + VIC_INT_SELECT);
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writel(vic->protect, base + VIC_PROTECT);
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/* set the enabled ints and then clear the non-enabled */
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writel(vic->int_enable, base + VIC_INT_ENABLE);
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writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
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/* and the same for the soft-int register */
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writel(vic->soft_int, base + VIC_INT_SOFT);
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writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
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return 0;
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}
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static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
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{
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struct vic_device *vic = to_vic(dev);
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void __iomem *base = vic->base;
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printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
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vic->int_select = readl(base + VIC_INT_SELECT);
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vic->int_enable = readl(base + VIC_INT_ENABLE);
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vic->soft_int = readl(base + VIC_INT_SOFT);
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vic->protect = readl(base + VIC_PROTECT);
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/* set the interrupts (if any) that are used for
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* resuming the system */
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writel(vic->resume_irqs, base + VIC_INT_ENABLE);
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writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
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return 0;
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}
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struct sysdev_class vic_class = {
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.name = "vic",
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.suspend = vic_class_suspend,
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.resume = vic_class_resume,
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};
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/**
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* vic_pm_register - Register a VIC for later power management control
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* @base: The base address of the VIC.
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* @irq: The base IRQ for the VIC.
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* @resume_sources: bitmask of interrupts allowed for resume sources.
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*
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* Register the VIC with the system device tree so that it can be notified
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* of suspend and resume requests and ensure that the correct actions are
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* taken to re-instate the settings on resume.
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*/
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static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
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{
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struct vic_device *v;
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if (vic_id >= ARRAY_SIZE(vic_devices))
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printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
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else {
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v = &vic_devices[vic_id];
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v->base = base;
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v->resume_sources = resume_sources;
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v->irq = irq;
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vic_id++;
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}
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}
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/**
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* vic_pm_init - initicall to register VIC pm
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*
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* This is called via late_initcall() to register
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* the resources for the VICs due to the early
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* nature of the VIC's registration.
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*/
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static int __init vic_pm_init(void)
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{
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struct vic_device *dev = vic_devices;
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int err;
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int id;
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if (vic_id == 0)
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return 0;
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err = sysdev_class_register(&vic_class);
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if (err) {
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printk(KERN_ERR "%s: cannot register class\n", __func__);
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return err;
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}
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for (id = 0; id < vic_id; id++, dev++) {
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dev->sysdev.id = id;
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dev->sysdev.cls = &vic_class;
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err = sysdev_register(&dev->sysdev);
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if (err) {
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printk(KERN_ERR "%s: failed to register device\n",
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__func__);
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return err;
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}
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}
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return 0;
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}
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late_initcall(vic_pm_init);
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static struct vic_device *vic_from_irq(unsigned int irq)
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{
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struct vic_device *v = vic_devices;
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unsigned int base_irq = irq & ~31;
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int id;
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for (id = 0; id < vic_id; id++, v++) {
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if (v->irq == base_irq)
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return v;
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}
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return NULL;
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}
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static int vic_set_wake(unsigned int irq, unsigned int on)
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{
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struct vic_device *v = vic_from_irq(irq);
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unsigned int off = irq & 31;
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u32 bit = 1 << off;
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if (!v)
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return -EINVAL;
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if (!(bit & v->resume_sources))
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return -EINVAL;
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if (on)
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v->resume_irqs |= bit;
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else
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v->resume_irqs &= ~bit;
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return 0;
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}
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#else
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static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
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#define vic_set_wake NULL
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#endif /* CONFIG_PM */
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static struct irq_chip vic_chip = {
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.name = "VIC",
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.ack = vic_ack_irq,
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.mask = vic_mask_irq,
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.unmask = vic_unmask_irq,
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.set_wake = vic_set_wake,
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};
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/* The PL190 cell from ARM has been modified by ST, so handle both here */
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static void vik_init_st(void __iomem *base, unsigned int irq_start,
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u32 vic_sources);
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/**
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* vic_init - initialise a vectored interrupt controller
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* @base: iomem base address
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* @irq_start: starting interrupt number, must be muliple of 32
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* @vic_sources: bitmask of interrupt sources to allow
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* @resume_sources: bitmask of interrupt sources to allow for resume
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*/
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void __init vic_init(void __iomem *base, unsigned int irq_start,
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u32 vic_sources, u32 resume_sources)
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{
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unsigned int i;
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u32 cellid = 0;
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enum amba_vendor vendor;
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/* Identify which VIC cell this one is, by reading the ID */
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for (i = 0; i < 4; i++) {
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u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
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cellid |= (readl(addr) & 0xff) << (8 * i);
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}
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vendor = (cellid >> 12) & 0xff;
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printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
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base, cellid, vendor);
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switch(vendor) {
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case AMBA_VENDOR_ST:
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vik_init_st(base, irq_start, vic_sources);
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return;
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default:
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printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
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/* fall through */
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case AMBA_VENDOR_ARM:
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break;
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}
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/* Disable all interrupts initially. */
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writel(0, base + VIC_INT_SELECT);
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writel(0, base + VIC_INT_ENABLE);
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writel(~0, base + VIC_INT_ENABLE_CLEAR);
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writel(0, base + VIC_IRQ_STATUS);
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writel(0, base + VIC_ITCR);
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writel(~0, base + VIC_INT_SOFT_CLEAR);
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/*
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* Make sure we clear all existing interrupts
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*/
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writel(0, base + VIC_PL190_VECT_ADDR);
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for (i = 0; i < 19; i++) {
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unsigned int value;
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value = readl(base + VIC_PL190_VECT_ADDR);
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writel(value, base + VIC_PL190_VECT_ADDR);
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}
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vic_init2(base);
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for (i = 0; i < 32; i++) {
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if (vic_sources & (1 << i)) {
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unsigned int irq = irq_start + i;
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set_irq_chip(irq, &vic_chip);
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set_irq_chip_data(irq, base);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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}
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vic_pm_register(base, irq_start, resume_sources);
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}
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/*
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* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
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* The original cell has 32 interrupts, while the modified one has 64,
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* replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
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* the probe function is called twice, with base set to offset 000
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* and 020 within the page. We call this "second block".
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*/
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static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
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u32 vic_sources)
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{
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unsigned int i;
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int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
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/* Disable all interrupts initially. */
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writel(0, base + VIC_INT_SELECT);
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writel(0, base + VIC_INT_ENABLE);
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writel(~0, base + VIC_INT_ENABLE_CLEAR);
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writel(0, base + VIC_IRQ_STATUS);
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writel(0, base + VIC_ITCR);
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writel(~0, base + VIC_INT_SOFT_CLEAR);
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/*
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* Make sure we clear all existing interrupts. The vector registers
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* in this cell are after the second block of general registers,
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* so we can address them using standard offsets, but only from
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* the second base address, which is 0x20 in the page
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*/
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if (vic_2nd_block) {
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writel(0, base + VIC_PL190_VECT_ADDR);
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for (i = 0; i < 19; i++) {
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unsigned int value;
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value = readl(base + VIC_PL190_VECT_ADDR);
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writel(value, base + VIC_PL190_VECT_ADDR);
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}
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/* ST has 16 vectors as well, but we don't enable them by now */
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for (i = 0; i < 16; i++) {
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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writel(0, reg);
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}
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writel(32, base + VIC_PL190_DEF_VECT_ADDR);
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}
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for (i = 0; i < 32; i++) {
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if (vic_sources & (1 << i)) {
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unsigned int irq = irq_start + i;
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set_irq_chip(irq, &vic_chip);
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set_irq_chip_data(irq, base);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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}
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}
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