400 lines
12 KiB
C
400 lines
12 KiB
C
#ifndef __SIL902X_H_
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#define __SIL902X_H_
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#include <mach/msm_fb.h>
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#include "edid.h"
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struct hdmi_info {
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struct hdmi_device hdmi_dev;
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struct i2c_client *client;
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struct msm_lcdc_panel_ops hdmi_lcdc_ops;
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struct work_struct work;
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struct delayed_work hdmi_delay_work;
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struct mutex lock;
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struct mutex lock2;
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struct clk *ebi1_clk;
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int (*power)(int on);
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void (*hdmi_gpio_on)(void);
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void (*hdmi_gpio_off)(void);
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enum hd_res res;
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// FIXME: move to edid_info_struct
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u8 edid_buf[128 * 4];
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enum {
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SLEEP,
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AWAKE,
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} sleeping;
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bool polling;
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bool cable_connected;
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bool isr_enabled;
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bool first;
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struct completion hotplug_completion;
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struct timer_list timer;
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struct work_struct polling_work;
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struct dentry *debug_dir;
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struct edid_info_struct edid_info;
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struct mutex polling_lock;
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bool suspending;
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bool user_playing;
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bool video_streaming;
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};
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enum {
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HDMI_PIXEL_DATA = 0x08,
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HDMI_AVI_INFO_FRAME = 0x0c,
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HDMI_AUDIO_INFO_FRAME = 0xbf,
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HDMI_SYS_CTL = 0x1a,
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HDMI_POWER = 0x1e,
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HDMI_IDENTIFY = 0x1b,
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HDMI_INT_EN = 0x3c,
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HDMI_INT_STAT = 0x3d,
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HDMI_EN_REG = 0xc7,
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};
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/* flag bitmap for register HDMI_INT_STAT */
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enum {
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HOT_PLUG_PENDING = (1U << 0),
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RX_PENDING = (1U << 1),
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HOT_PLUG_STATE = (1U << 2),
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RX_STATE = (1U << 3),
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AUDIO_ERR = (1U << 4),
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SECURITY_STATE = (1U << 5),
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HDCP_VALUE = (1U << 6),
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HDCP_AUTH = (1U << 7),
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};
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enum ErrorMessages {
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INIT_SYSTEM_SUCCESSFUL, // 0
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BLACK_BOX_OPEN_FAILURE,
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BLACK_BOX_OPENED_SUCCESSFULLY,
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HW_RESET_FAILURE,
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TPI_ENABLE_FAILURE,
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INTERRUPT_EN_FAILURE,
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INTERRUPT_POLLING_FAILED,
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NO_SINK_CONNECTED,
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DDC_BUS_REQ_FAILURE,
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HDCP_FAILURE,
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HDCP_OK, // 10
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RX_AUTHENTICATED,
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SINK_DOES_NOT_SUPPORT_HDCP,
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TX_DOES_NOT_SUPPORT_HDCP,
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ILLEGAL_AKSV,
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SET_PROTECTION_FAILURE,
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REVOKED_KEYS_FOUND,
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REPEATER_AUTHENTICATED,
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INT_STATUS_READ_FAILURE,
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PROTECTION_OFF_FAILED,
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PROTECTION_ON_FAILED, // 20
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INTERRUPT_POLLING_OK,
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EDID_PARSING_FAILURE,
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VIDEO_SETUP_FAILURE,
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TPI_READ_FAILURE,
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TPI_WRITE_FAILURE,
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INIT_VIDEO_FAILURE,
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DE_CANNOT_BE_SET_WITH_EMBEDDED_SYNC,
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SET_EMBEDDED_SYC_FAILURE,
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V_MODE_NOT_SUPPORTED,
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AUD_MODE_NOT_SUPPORTED, // 30
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I2S_NOT_SET,
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EDID_READ_FAILURE,
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EDID_CHECKSUM_ERROR,
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INCORRECT_EDID_HEADER,
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EDID_EXT_TAG_ERROR,
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EDID_REV_ADDR_ERROR,
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EDID_V_DESCR_OVERFLOW,
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INCORRECT_EDID_FILE,
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UNKNOWN_EDID_TAG_CODE,
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NO_DETAILED_DESCRIPTORS_IN_THIS_EDID_BLOCK, // 40
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CONFIG_DATA_VALID,
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CONFIG_DATA_INVALID,
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GPIO_ACCESS_FAILED,
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GPIO_CONFIG_ERROR,
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HP_EVENT_GOING_TO_SERVICE_LOOP,
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EDID_PARSED_OK,
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VIDEO_MODE_SET_OK,
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AUDIO_MODE_SET_OK,
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I2S_MAPPING_SUCCESSFUL,
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I2S_INPUT_CONFIG_SUCCESSFUL, // 50
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I2S_HEADER_SET_SUCCESSFUL,
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INTERRUPT_POLLING_SUCCESSFUL,
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HPD_LOOP_EXITED_SUCCESSFULY,
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HPD_LOOP_FAILED,
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SINK_CONNECTED,
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HP_EVENT_RETURNING_FROM_SERVICE_LOOP,
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AVI_INFOFRAMES_SETTING_FAILED,
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TMDS_ENABLING_FAILED,
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DE_SET_OK,
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DE_SET_FAILED,
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NO_861_EXTENSIONS,
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GO_OK,
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IMAGE_PKTS_UPDATED_OK,
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MONITORING_BLOCKED,
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LINK_NORMAL,
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LINK_LOST,
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RENEGOTIATION_REQUIRED,
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LINK_SUSPENDED,
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EDID_SHORT_DESCRIPTORS_PARSED_OK,
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EDID_LONG_DESCRIPTORS_PARSED_OK,
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DDC_BUS_RELEASE_FAILURE,
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FAILED_GETTING_BKSV,
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PLL_SETUP_FAILUE,
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ERR_RX_QUEUE_FULL,
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ERR_TX_QUEUE_FULL,
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GBD_SET_SUCCESSFULLY,
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BACKDOOR_SETTING_FAILED,
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ERR_TX_QUEUE_EMPTY
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};
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#define BIT_0 0x01
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#define BIT_1 0x02
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#define BIT_2 0x04
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#define BIT_3 0x08
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#define BIT_4 0x10
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#define BIT_5 0x20
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#define BIT_6 0x40
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#define BIT_7 0x80
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#define INTERVAL_HDCP_POLLING (HZ / 25)
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#define REQUEST_RELEASE_DDC_BEFORE_HDCP
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#define T_HDCP_ACTIVATION 500
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#define T_HDCP_DEACTIVATION 200
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#define T_HPD_DELAY 10
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#define TPI_INTERRUPT_EN 0x3c
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#define ALL 0xff
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#define DUMMY 0xFD
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#define SiI_DEVICE_ID 0xB0
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#define T_DDC_ACCESS 50
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// TPI Control Masks
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// =================
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#define BIT_OUTPUT_MODE 0x01
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#define BIT_DDC_BUS_GRANT 0x02
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#define BIT_DDC_BUS_REQ 0x04
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#define BIT_TMDS_OUTPUT 0x10
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#define TPI_INTERNAL_PAGE_REG 0xBC
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#define TPI_REGISTER_OFFSET_REG 0xBD
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#define TPI_REGISTER_VALUE_REG 0xBE
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/* HDCP Control Masks */
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#define BIT_PROTECT_LEVEL 0x01
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#define BIT_PROTECT_TYPE 0x02
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#define BIT_REPEATER 0x08
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#define BIT_LOCAL_PROTECT 0x40
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#define BIT_EXT_PROTECT 0x80
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#define BITS_LINK_LOST 0x10
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#define BITS_RENEGOTIATION 0x20
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#define BIT_TMDS_OUTPUT 0x10
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#define BIT_AUDIO_MUTE 0x10
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#define TPI_HDCP_REVISION_DATA_REG (0x30)
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#define HDCP_MAJOR_REVISION_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4)
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#define HDCP_MAJOR_REVISION_VALUE (0x10)
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#define HDCP_MINOR_REVISION_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
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#define HDCP_MINOR_REVISION_VALUE (0x02)
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#define HDCP_REVISION 0x12
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#define SET_PROT_ATTEMPTS 0x05
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#define AKSV_SIZE 5
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#define BYTE_SIZE 8
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#define NUM_OF_ONES_IN_KSV 20
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// Interrupt Masks
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//================
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#define HOT_PLUG_EVENT 0x01
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#define RX_SENSE_EVENT 0x02
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#define TPI_HOT_PLUG_STATE 0x04
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#define RX_SENSE_STATE 0x08
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#define AUDIO_ERROR_EVENT 0x10
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#define SECURITY_CHANGE_EVENT 0x20
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#define V_READY_EVENT 0x40
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#define HDCP_CHANGE_EVENT 0x80
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#define NON_MASKABLE_INT 0xFF
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/* Protection Levels */
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#define NO_PROTECTION 0x00
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#define LOCAL_PROTECTION 0x01
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#define EXTENDED_PROTECTION 0x03
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#define LINK_NORMAL 0
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#define MAX_V_DESCRIPTORS 20
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#define MAX_A_DESCRIPTORS 10
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#define MAX_SPEAKER_CONFIGURATIONS 4
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#define HDMI_DEBUGFS_ROOT "hdmi"
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/// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ///
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/*\
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| | HDCP Implementation
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| | HDCP link security logic is implemented in certain transmitters; unique
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| | keys are embedded in each chip as part of the solution. The security
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| | scheme is fully automatic and handled completely by the hardware.
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\*/
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/// HDCP Query Data Register ============================================== ///
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#define TPI_HDCP_QUERY_DATA_REG (0x29)
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#define EXTENDED_LINK_PROTECTION_MASK (BIT_7)
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#define EXTENDED_LINK_PROTECTION_NONE (0x00)
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#define EXTENDED_LINK_PROTECTION_SECURE (0x80)
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#define LOCAL_LINK_PROTECTION_MASK (BIT_6)
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#define LOCAL_LINK_PROTECTION_NONE (0x00)
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#define LOCAL_LINK_PROTECTION_SECURE (0x40)
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#define LINK_STATUS_MASK (BIT_5 | BIT_4)
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#define LINK_STATUS_NORMAL (0x00)
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#define LINK_STATUS_LINK_LOST (0x10)
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#define LINK_STATUS_RENEGOTIATION_REQ (0x20)
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#define LINK_STATUS_LINK_SUSPENDED (0x30)
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#define HDCP_REPEATER_MASK (BIT_3)
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#define HDCP_REPEATER_NO (0x00)
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#define HDCP_REPEATER_YES (0x08)
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#define CONNECTOR_TYPE_MASK (BIT_2 | BIT_0)
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#define CONNECTOR_TYPE_DVI (0x00)
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#define CONNECTOR_TYPE_RSVD (0x01)
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#define CONNECTOR_TYPE_HDMI (0x04)
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#define CONNECTOR_TYPE_FUTURE (0x05)
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#define PROTECTION_TYPE_MASK (BIT_1)
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#define PROTECTION_TYPE_NONE (0x00)
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#define PROTECTION_TYPE_HDCP (0x02)
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/// HDCP Control Data Register ============================================ ///
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#define TPI_HDCP_CONTROL_DATA_REG (0x2A)
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#define PROTECTION_LEVEL_MASK (BIT_0)
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#define PROTECTION_LEVEL_MIN (0x00)
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#define PROTECTION_LEVEL_MAX (0x01)
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/*---------------------------------------------------------------------------*/
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#if 0
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/* Caller: ChangeVideoMode(), HDCP_Poll(), HotPlugServiceLoop(), RestartHDCP()
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*/
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#define EnableTMDS(hdmi) ReadClearWriteTPI(hdmi, TPI_SYSTEM_CONTROL, BIT_TMDS_OUTPUT) // 0x1A[4] = 0
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/* Caller: ChangeVideoMode(), HDCP_Poll(), TPI_Poll(), RestartHDCP(),
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* OnHdmiCableDisconnected()
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*/
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#define DisableTMDS(hdmi) ReadSetWriteTPI(hdmi, TPI_SYSTEM_CONTROL, BIT_TMDS_OUTPUT) // 0x1A[4] = 1
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#else
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void EnableTMDS(struct hdmi_info *hdmi);
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void DisableTMDS(struct hdmi_info *hdmi);
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#endif
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// FIXME: fix the global variables
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extern u8 pvid_mode, vid_mode;
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extern u8 LinkProtectionLevel;
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extern u8 systemInitialized;
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/*---------------------------------------------------------------------------*/
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int hdmi_read(struct i2c_client *client, u8 cmd);
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int hdmi_write_byte(struct i2c_client *client, u8 reg, u8 val);
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int hdmi_enable_int(struct i2c_client *client);
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int hdmi_disable_int(struct i2c_client *client);
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int hdmi_read_edid(struct hdmi_info *info, struct i2c_client *client);
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int hdmi_standby(struct hdmi_info *hdmi);
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int hdmi_wakeup(struct hdmi_info *hdmi);
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int read_backdoor_register(struct hdmi_info *hdmi, u8 PageNum, u8 RegOffset);
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void ReadSetWriteTPI(struct hdmi_info *hdmi, u8 Offset, u8 Pattern);
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void ReadModifyWriteTPI(struct hdmi_info *hdmi, u8 Offset, u8 Mask, u8 Value);
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void tpi_clear_interrupt(struct hdmi_info *hdmi, u8 pattern);
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bool tpi_init(struct hdmi_info *hdmi);
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void ReadClearWriteTPI(struct hdmi_info *hdmi, u8 Offset, u8 Pattern);
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s32 ReadBlockTPI(struct hdmi_info *hdmi, u8 TPI_Offset, u16 NBytes, u8 *pData);
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bool IsRepeater(struct hdmi_info *hdmi);
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bool GetDDC_Access(struct hdmi_info *hdmi, u8* SysCtrlRegVal);
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bool ReleaseDDC(struct hdmi_info *hdmi, u8 SysCtrlRegVal);
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int tpi_read_backdoor_register(struct hdmi_info *hdmi, u8 PageNum, u8 RegOffset)
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;
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void tpi_write_backdoor_register(struct hdmi_info *hdmi, u8 PageNum, u8 RegOffset, u8 RegValue);
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int HotPlugServiceLoop(struct hdmi_info *hdmi);
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int hdmi_active9022(struct i2c_client *client);
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int hdmi_active9022_dup(struct i2c_client *client);
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bool avc_send_avi_info_frames(struct hdmi_info *hdmi);
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bool avc_init_video(struct hdmi_info *hdmi, u8 mode, u8 TclkSel, bool Init);
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//void hdcp_on(struct hdmi_info *hdmi);
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void hdcp_off(struct hdmi_info *hdmi);
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void hdcp_check_status(struct hdmi_info *hdmi, u8 InterruptStatusImage);
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void hdcp_init(struct hdmi_info *hdmi);
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int hdcp_debugfs_init(struct hdmi_info *hdmi);
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extern u8 EDID_TempData[];
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u8 edid_simple_parsing(struct hdmi_info *hdmi);
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int edid_dump_hex(u8 *src, int src_size, char *output, int output_size);
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bool edid_is_video_mode_supported(struct video_mode *vmode);
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int edid_debugfs_init(struct hdmi_info *hdmi);
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bool edid_check_sink_type(struct hdmi_info *hdmi);
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int HotPlugServiceLoop(struct hdmi_info *hdmi);
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int tpi_prepare(struct hdmi_info *hdmi);
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//bool InitVideo(struct hdmi_info *hdmi, u8 Mode, u8 TclkSel, bool Init);
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void avc_set_basic_audio(struct hdmi_info *hdmi);
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int hdmi_debugfs_init(struct hdmi_info *hdmi);
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int tpi_debugfs_init(struct hdmi_info *hdmi);
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ssize_t hdmi_dbgfs_open(struct inode *inode, struct file *file);
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void SetAudioMute(struct hdmi_info *hdmi, u8 audioMute);
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void SetInputColorSpace(struct hdmi_info *hdmi, u8 inputColorSpace);
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void WriteBackDoorRegister(struct hdmi_info *hdmi, u8 PageNum, u8 RegOffset, u8 RegValue);
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#define TPI_INPUT_FORMAT 0x09
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#define TPI_OUTPUT_FORMAT 0x0A
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#define TPI_SYSTEM_CONTROL 0x1A
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#define TPI_DEVICE_POWER_STATE_CTRL_REG (0x1E)
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#define CTRL_PIN_CONTROL_MASK (BIT_4)
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#define CTRL_PIN_TRISTATE (0x00)
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#define CTRL_PIN_DRIVEN_TX_BRIDGE (0x10)
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#define TX_POWER_STATE_D0 (0x00)
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#define TX_POWER_STATE_D1 (0x01)
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#define TX_POWER_STATE_D2 (0x02)
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#define TX_POWER_STATE_D3 (0x03)
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#define TPI_AUDIO_INTERFACE 0x26
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#define TPI_HDCP_QUERY_DATA 0x29
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#define TPI_HDCP_CTRL 0x2A
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#endif
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