680 lines
20 KiB
C
680 lines
20 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef HW_H
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#define HW_H
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#include <linux/if_ether.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "mac.h"
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#include "ani.h"
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#include "eeprom.h"
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#include "calib.h"
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#include "reg.h"
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#include "phy.h"
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#include "../regd.h"
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#define ATHEROS_VENDOR_ID 0x168c
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#define AR5416_DEVID_PCI 0x0023
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#define AR5416_DEVID_PCIE 0x0024
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#define AR9160_DEVID_PCI 0x0027
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#define AR9280_DEVID_PCI 0x0029
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#define AR9280_DEVID_PCIE 0x002a
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#define AR9285_DEVID_PCIE 0x002b
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#define AR5416_AR9100_DEVID 0x000b
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#define AR_SUBVENDOR_ID_NOG 0x0e11
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#define AR_SUBVENDOR_ID_NEW_A 0x7065
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#define AR5416_MAGIC 0x19641014
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#define AR5416_DEVID_AR9287_PCI 0x002D
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#define AR5416_DEVID_AR9287_PCIE 0x002E
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#define AR9280_COEX2WIRE_SUBSYSID 0x309b
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#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
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#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
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/* Register read/write primitives */
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#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
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#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
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#define SM(_v, _f) (((_v) << _f##_S) & _f)
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#define MS(_v, _f) (((_v) & _f) >> _f##_S)
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#define REG_RMW(_a, _r, _set, _clr) \
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REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
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#define REG_RMW_FIELD(_a, _r, _f, _v) \
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REG_WRITE(_a, _r, \
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(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
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#define REG_SET_BIT(_a, _r, _f) \
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REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
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#define REG_CLR_BIT(_a, _r, _f) \
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REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
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#define DO_DELAY(x) do { \
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if ((++(x) % 64) == 0) \
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udelay(1); \
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} while (0)
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#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
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int r; \
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for (r = 0; r < ((iniarray)->ia_rows); r++) { \
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REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
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INI_RA((iniarray), r, (column))); \
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DO_DELAY(regWr); \
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} \
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} while (0)
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#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
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#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
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#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
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#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
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#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
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#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
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#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
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#define AR_GPIOD_MASK 0x00001FFF
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#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
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#define BASE_ACTIVATE_DELAY 100
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#define RTC_PLL_SETTLE_DELAY 1000
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#define COEF_SCALE_S 24
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#define HT40_CHANNEL_CENTER_SHIFT 10
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#define ATH9K_ANTENNA0_CHAINMASK 0x1
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#define ATH9K_ANTENNA1_CHAINMASK 0x2
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#define ATH9K_NUM_DMA_DEBUG_REGS 8
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#define ATH9K_NUM_QUEUES 10
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#define MAX_RATE_POWER 63
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#define AH_WAIT_TIMEOUT 100000 /* (us) */
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#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
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#define AH_TIME_QUANTUM 10
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#define AR_KEYTABLE_SIZE 128
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#define POWER_UP_TIME 10000
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#define SPUR_RSSI_THRESH 40
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#define CAB_TIMEOUT_VAL 10
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#define BEACON_TIMEOUT_VAL 10
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#define MIN_BEACON_TIMEOUT_VAL 1
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#define SLEEP_SLOP 3
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#define INIT_CONFIG_STATUS 0x00000000
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#define INIT_RSSI_THR 0x00000700
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#define INIT_BCON_CNTRL_REG 0x00000000
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#define TU_TO_USEC(_tu) ((_tu) << 10)
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enum wireless_mode {
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ATH9K_MODE_11A = 0,
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ATH9K_MODE_11G,
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ATH9K_MODE_11NA_HT20,
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ATH9K_MODE_11NG_HT20,
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ATH9K_MODE_11NA_HT40PLUS,
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ATH9K_MODE_11NA_HT40MINUS,
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ATH9K_MODE_11NG_HT40PLUS,
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ATH9K_MODE_11NG_HT40MINUS,
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ATH9K_MODE_MAX,
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};
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enum ath9k_ant_setting {
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ATH9K_ANT_VARIABLE = 0,
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ATH9K_ANT_FIXED_A,
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ATH9K_ANT_FIXED_B
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};
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enum ath9k_hw_caps {
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ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
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ATH9K_HW_CAP_MIC_CKIP = BIT(1),
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ATH9K_HW_CAP_MIC_TKIP = BIT(2),
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ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
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ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
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ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
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ATH9K_HW_CAP_VEOL = BIT(6),
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ATH9K_HW_CAP_BSSIDMASK = BIT(7),
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ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
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ATH9K_HW_CAP_HT = BIT(9),
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ATH9K_HW_CAP_GTT = BIT(10),
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ATH9K_HW_CAP_FASTCC = BIT(11),
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ATH9K_HW_CAP_RFSILENT = BIT(12),
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ATH9K_HW_CAP_CST = BIT(13),
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ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
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ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
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ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
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};
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enum ath9k_capability_type {
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ATH9K_CAP_CIPHER = 0,
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ATH9K_CAP_TKIP_MIC,
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ATH9K_CAP_TKIP_SPLIT,
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ATH9K_CAP_DIVERSITY,
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ATH9K_CAP_TXPOW,
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ATH9K_CAP_MCAST_KEYSRCH,
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ATH9K_CAP_DS
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};
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struct ath9k_hw_capabilities {
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u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
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DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
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u16 total_queues;
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u16 keycache_size;
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u16 low_5ghz_chan, high_5ghz_chan;
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u16 low_2ghz_chan, high_2ghz_chan;
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u16 rts_aggr_limit;
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u8 tx_chainmask;
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u8 rx_chainmask;
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u16 tx_triglevel_max;
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u16 reg_cap;
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u8 num_gpio_pins;
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u8 num_antcfg_2ghz;
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u8 num_antcfg_5ghz;
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};
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struct ath9k_ops_config {
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int dma_beacon_response_time;
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int sw_beacon_response_time;
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int additional_swba_backoff;
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int ack_6mb;
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int cwm_ignore_extcca;
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u8 pcie_powersave_enable;
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u8 pcie_clock_req;
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u32 pcie_waen;
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u8 analog_shiftreg;
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u8 ht_enable;
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u32 ofdm_trig_low;
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u32 ofdm_trig_high;
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u32 cck_trig_high;
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u32 cck_trig_low;
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u32 enable_ani;
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enum ath9k_ant_setting diversity_control;
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u16 antenna_switch_swap;
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int serialize_regmode;
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bool intr_mitigation;
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#define SPUR_DISABLE 0
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#define SPUR_ENABLE_IOCTL 1
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#define SPUR_ENABLE_EEPROM 2
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#define AR_EEPROM_MODAL_SPURS 5
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#define AR_SPUR_5413_1 1640
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#define AR_SPUR_5413_2 1200
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#define AR_NO_SPUR 0x8000
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#define AR_BASE_FREQ_2GHZ 2300
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#define AR_BASE_FREQ_5GHZ 4900
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#define AR_SPUR_FEEQ_BOUND_HT40 19
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#define AR_SPUR_FEEQ_BOUND_HT20 10
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int spurmode;
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u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
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u8 max_txtrig_level;
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};
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enum ath9k_int {
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ATH9K_INT_RX = 0x00000001,
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ATH9K_INT_RXDESC = 0x00000002,
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ATH9K_INT_RXNOFRM = 0x00000008,
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ATH9K_INT_RXEOL = 0x00000010,
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ATH9K_INT_RXORN = 0x00000020,
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ATH9K_INT_TX = 0x00000040,
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ATH9K_INT_TXDESC = 0x00000080,
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ATH9K_INT_TIM_TIMER = 0x00000100,
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ATH9K_INT_TXURN = 0x00000800,
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ATH9K_INT_MIB = 0x00001000,
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ATH9K_INT_RXPHY = 0x00004000,
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ATH9K_INT_RXKCM = 0x00008000,
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ATH9K_INT_SWBA = 0x00010000,
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ATH9K_INT_BMISS = 0x00040000,
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ATH9K_INT_BNR = 0x00100000,
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ATH9K_INT_TIM = 0x00200000,
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ATH9K_INT_DTIM = 0x00400000,
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ATH9K_INT_DTIMSYNC = 0x00800000,
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ATH9K_INT_GPIO = 0x01000000,
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ATH9K_INT_CABEND = 0x02000000,
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ATH9K_INT_TSFOOR = 0x04000000,
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ATH9K_INT_GENTIMER = 0x08000000,
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ATH9K_INT_CST = 0x10000000,
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ATH9K_INT_GTT = 0x20000000,
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ATH9K_INT_FATAL = 0x40000000,
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ATH9K_INT_GLOBAL = 0x80000000,
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ATH9K_INT_BMISC = ATH9K_INT_TIM |
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ATH9K_INT_DTIM |
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ATH9K_INT_DTIMSYNC |
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ATH9K_INT_TSFOOR |
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ATH9K_INT_CABEND,
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ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
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ATH9K_INT_RXDESC |
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ATH9K_INT_RXEOL |
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ATH9K_INT_RXORN |
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ATH9K_INT_TXURN |
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ATH9K_INT_TXDESC |
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ATH9K_INT_MIB |
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ATH9K_INT_RXPHY |
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ATH9K_INT_RXKCM |
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ATH9K_INT_SWBA |
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ATH9K_INT_BMISS |
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ATH9K_INT_GPIO,
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ATH9K_INT_NOCARD = 0xffffffff
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};
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#define CHANNEL_CW_INT 0x00002
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#define CHANNEL_CCK 0x00020
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#define CHANNEL_OFDM 0x00040
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#define CHANNEL_2GHZ 0x00080
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#define CHANNEL_5GHZ 0x00100
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#define CHANNEL_PASSIVE 0x00200
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#define CHANNEL_DYN 0x00400
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#define CHANNEL_HALF 0x04000
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#define CHANNEL_QUARTER 0x08000
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#define CHANNEL_HT20 0x10000
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#define CHANNEL_HT40PLUS 0x20000
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#define CHANNEL_HT40MINUS 0x40000
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#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
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#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
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#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
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#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
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#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
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#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
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#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
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#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
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#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
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#define CHANNEL_ALL \
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(CHANNEL_OFDM| \
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CHANNEL_CCK| \
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CHANNEL_2GHZ | \
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CHANNEL_5GHZ | \
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CHANNEL_HT20 | \
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CHANNEL_HT40PLUS | \
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CHANNEL_HT40MINUS)
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struct ath9k_channel {
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struct ieee80211_channel *chan;
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u16 channel;
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u32 channelFlags;
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u32 chanmode;
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int32_t CalValid;
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bool oneTimeCalsDone;
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int8_t iCoff;
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int8_t qCoff;
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int16_t rawNoiseFloor;
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};
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#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
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(((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
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(((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
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(((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
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#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
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#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
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#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
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#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
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#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
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#define IS_CHAN_A_5MHZ_SPACED(_c) \
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((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
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(((_c)->channel % 20) != 0) && \
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(((_c)->channel % 10) != 0))
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/* These macros check chanmode and not channelFlags */
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#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
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#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
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((_c)->chanmode == CHANNEL_G_HT20))
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#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
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((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
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((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
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((_c)->chanmode == CHANNEL_G_HT40MINUS))
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#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
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enum ath9k_power_mode {
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ATH9K_PM_AWAKE = 0,
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ATH9K_PM_FULL_SLEEP,
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ATH9K_PM_NETWORK_SLEEP,
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ATH9K_PM_UNDEFINED
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};
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enum ath9k_tp_scale {
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ATH9K_TP_SCALE_MAX = 0,
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ATH9K_TP_SCALE_50,
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ATH9K_TP_SCALE_25,
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ATH9K_TP_SCALE_12,
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ATH9K_TP_SCALE_MIN
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};
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enum ser_reg_mode {
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SER_REG_MODE_OFF = 0,
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SER_REG_MODE_ON = 1,
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SER_REG_MODE_AUTO = 2,
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};
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struct ath9k_beacon_state {
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u32 bs_nexttbtt;
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u32 bs_nextdtim;
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u32 bs_intval;
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#define ATH9K_BEACON_PERIOD 0x0000ffff
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#define ATH9K_BEACON_ENA 0x00800000
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#define ATH9K_BEACON_RESET_TSF 0x01000000
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#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
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u32 bs_dtimperiod;
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u16 bs_cfpperiod;
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u16 bs_cfpmaxduration;
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u32 bs_cfpnext;
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u16 bs_timoffset;
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u16 bs_bmissthreshold;
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u32 bs_sleepduration;
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u32 bs_tsfoor_threshold;
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};
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struct chan_centers {
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u16 synth_center;
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u16 ctl_center;
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u16 ext_center;
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};
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enum {
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ATH9K_RESET_POWER_ON,
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ATH9K_RESET_WARM,
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ATH9K_RESET_COLD,
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};
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struct ath9k_hw_version {
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u32 magic;
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u16 devid;
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u16 subvendorid;
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u32 macVersion;
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u16 macRev;
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u16 phyRev;
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u16 analog5GhzRev;
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u16 analog2GhzRev;
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u16 subsysid;
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};
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/* Generic TSF timer definitions */
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#define ATH_MAX_GEN_TIMER 16
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#define AR_GENTMR_BIT(_index) (1 << (_index))
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/*
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* Using de Bruijin sequence to to look up 1's index in a 32 bit number
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* debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
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*/
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#define debruijn32 0x077CB531U
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struct ath_gen_timer_configuration {
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u32 next_addr;
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u32 period_addr;
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u32 mode_addr;
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u32 mode_mask;
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};
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struct ath_gen_timer {
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void (*trigger)(void *arg);
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void (*overflow)(void *arg);
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void *arg;
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u8 index;
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};
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struct ath_gen_timer_table {
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u32 gen_timer_index[32];
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struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
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union {
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unsigned long timer_bits;
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u16 val;
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} timer_mask;
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};
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struct ath_hw {
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struct ath_softc *ah_sc;
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struct ath9k_hw_version hw_version;
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struct ath9k_ops_config config;
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struct ath9k_hw_capabilities caps;
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struct ath9k_channel channels[38];
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struct ath9k_channel *curchan;
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union {
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struct ar5416_eeprom_def def;
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struct ar5416_eeprom_4k map4k;
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struct ar9287_eeprom map9287;
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} eeprom;
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const struct eeprom_ops *eep_ops;
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enum ath9k_eep_map eep_map;
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bool sw_mgmt_crypto;
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bool is_pciexpress;
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u8 macaddr[ETH_ALEN];
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u16 tx_trig_level;
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u16 rfsilent;
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u32 rfkill_gpio;
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u32 rfkill_polarity;
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u32 ah_flags;
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bool htc_reset_init;
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enum nl80211_iftype opmode;
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enum ath9k_power_mode power_mode;
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struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
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struct ath9k_pacal_info pacal_info;
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struct ar5416Stats stats;
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struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
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int16_t curchan_rad_index;
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u32 mask_reg;
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u32 txok_interrupt_mask;
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u32 txerr_interrupt_mask;
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u32 txdesc_interrupt_mask;
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u32 txeol_interrupt_mask;
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u32 txurn_interrupt_mask;
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bool chip_fullsleep;
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u32 atim_window;
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/* Calibration */
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enum ath9k_cal_types supp_cals;
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struct ath9k_cal_list iq_caldata;
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struct ath9k_cal_list adcgain_caldata;
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struct ath9k_cal_list adcdc_calinitdata;
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struct ath9k_cal_list adcdc_caldata;
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struct ath9k_cal_list *cal_list;
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struct ath9k_cal_list *cal_list_last;
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struct ath9k_cal_list *cal_list_curr;
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#define totalPowerMeasI meas0.unsign
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#define totalPowerMeasQ meas1.unsign
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#define totalIqCorrMeas meas2.sign
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#define totalAdcIOddPhase meas0.unsign
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#define totalAdcIEvenPhase meas1.unsign
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#define totalAdcQOddPhase meas2.unsign
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#define totalAdcQEvenPhase meas3.unsign
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#define totalAdcDcOffsetIOddPhase meas0.sign
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#define totalAdcDcOffsetIEvenPhase meas1.sign
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#define totalAdcDcOffsetQOddPhase meas2.sign
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#define totalAdcDcOffsetQEvenPhase meas3.sign
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union {
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u32 unsign[AR5416_MAX_CHAINS];
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int32_t sign[AR5416_MAX_CHAINS];
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} meas0;
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union {
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u32 unsign[AR5416_MAX_CHAINS];
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int32_t sign[AR5416_MAX_CHAINS];
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} meas1;
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union {
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u32 unsign[AR5416_MAX_CHAINS];
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int32_t sign[AR5416_MAX_CHAINS];
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} meas2;
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union {
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u32 unsign[AR5416_MAX_CHAINS];
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int32_t sign[AR5416_MAX_CHAINS];
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} meas3;
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u16 cal_samples;
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u32 sta_id1_defaults;
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u32 misc_mode;
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enum {
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AUTO_32KHZ,
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USE_32KHZ,
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DONT_USE_32KHZ,
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} enable_32kHz_clock;
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/* RF */
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u32 *analogBank0Data;
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u32 *analogBank1Data;
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u32 *analogBank2Data;
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u32 *analogBank3Data;
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u32 *analogBank6Data;
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u32 *analogBank6TPCData;
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u32 *analogBank7Data;
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u32 *addac5416_21;
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u32 *bank6Temp;
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int16_t txpower_indexoffset;
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u32 beacon_interval;
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u32 slottime;
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u32 acktimeout;
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u32 ctstimeout;
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u32 globaltxtimeout;
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u8 gbeacon_rate;
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/* ANI */
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u32 proc_phyerr;
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u32 aniperiod;
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struct ar5416AniState *curani;
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struct ar5416AniState ani[255];
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int totalSizeDesired[5];
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int coarse_high[5];
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int coarse_low[5];
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int firpwr[5];
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enum ath9k_ani_cmd ani_function;
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u32 intr_txqs;
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enum ath9k_ht_extprotspacing extprotspacing;
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u8 txchainmask;
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u8 rxchainmask;
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u32 originalGain[22];
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int initPDADC;
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int PDADCdelta;
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u8 led_pin;
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struct ar5416IniArray iniModes;
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struct ar5416IniArray iniCommon;
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struct ar5416IniArray iniBank0;
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struct ar5416IniArray iniBB_RfGain;
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struct ar5416IniArray iniBank1;
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struct ar5416IniArray iniBank2;
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struct ar5416IniArray iniBank3;
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struct ar5416IniArray iniBank6;
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struct ar5416IniArray iniBank6TPC;
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struct ar5416IniArray iniBank7;
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struct ar5416IniArray iniAddac;
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struct ar5416IniArray iniPcieSerdes;
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struct ar5416IniArray iniModesAdditional;
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struct ar5416IniArray iniModesRxGain;
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struct ar5416IniArray iniModesTxGain;
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u32 intr_gen_timer_trigger;
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u32 intr_gen_timer_thresh;
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struct ath_gen_timer_table hw_gen_timers;
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};
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/* Initialization, Detach, Reset */
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const char *ath9k_hw_probe(u16 vendorid, u16 devid);
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void ath9k_hw_detach(struct ath_hw *ah);
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int ath9k_hw_init(struct ath_hw *ah);
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void ath9k_hw_rf_free(struct ath_hw *ah);
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int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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bool bChannelChange);
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void ath9k_hw_fill_cap_info(struct ath_hw *ah);
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bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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u32 capability, u32 *result);
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bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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u32 capability, u32 setting, int *status);
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/* Key Cache Management */
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bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
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bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
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bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
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const struct ath9k_keyval *k,
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const u8 *mac);
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bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
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/* GPIO / RFKILL / Antennae */
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void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
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u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
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void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
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u32 ah_signal_type);
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void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
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u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
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void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
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bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
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enum ath9k_ant_setting settings,
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struct ath9k_channel *chan,
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u8 *tx_chainmask, u8 *rx_chainmask,
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u8 *antenna_cfgd);
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/* General Operation */
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n);
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bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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const struct ath_rate_table *rates,
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u32 frameLen, u16 rateix, bool shortPreamble);
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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struct ath9k_channel *chan,
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struct chan_centers *centers);
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u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
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void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
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bool ath9k_hw_phy_disable(struct ath_hw *ah);
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bool ath9k_hw_disable(struct ath_hw *ah);
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void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
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void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
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void ath9k_hw_setopmode(struct ath_hw *ah);
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void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
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void ath9k_hw_setbssidmask(struct ath_softc *sc);
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void ath9k_hw_write_associd(struct ath_softc *sc);
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u64 ath9k_hw_gettsf64(struct ath_hw *ah);
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void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
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void ath9k_hw_reset_tsf(struct ath_hw *ah);
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void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
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bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
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void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
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void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
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void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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const struct ath9k_beacon_state *bs);
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bool ath9k_hw_setpower(struct ath_hw *ah,
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enum ath9k_power_mode mode);
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void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
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/* Interrupt Handling */
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bool ath9k_hw_intrpend(struct ath_hw *ah);
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bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
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enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
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/* Generic hw timer primitives */
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struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
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void (*trigger)(void *),
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void (*overflow)(void *),
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void *arg,
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u8 timer_index);
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void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer,
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u32 timer_next, u32 timer_period);
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void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
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void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
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void ath_gen_timer_isr(struct ath_hw *hw);
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u32 ath9k_hw_gettsf32(struct ath_hw *ah);
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#define ATH_PCIE_CAP_LINK_CTRL 0x70
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#define ATH_PCIE_CAP_LINK_L0S 1
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#define ATH_PCIE_CAP_LINK_L1 2
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void ath_pcie_aspm_disable(struct ath_softc *sc);
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#endif
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