549 lines
16 KiB
C
549 lines
16 KiB
C
/*
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* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
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* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/********************************************\
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Queue Control Unit, DFS Control Unit Functions
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\********************************************/
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#include "ath5k.h"
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#include "reg.h"
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#include "debug.h"
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#include "base.h"
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/*
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* Get properties for a transmit queue
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*/
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int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
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struct ath5k_txq_info *queue_info)
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{
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ATH5K_TRACE(ah->ah_sc);
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memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
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return 0;
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}
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/*
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* Set properties for a transmit queue
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*/
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int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
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const struct ath5k_txq_info *queue_info)
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{
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
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if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
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return -EIO;
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memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
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/*XXX: Is this supported on 5210 ?*/
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if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
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((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
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(queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
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queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
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ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
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return 0;
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}
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/*
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* Initialize a transmit queue
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*/
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int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
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struct ath5k_txq_info *queue_info)
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{
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unsigned int queue;
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int ret;
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ATH5K_TRACE(ah->ah_sc);
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/*
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* Get queue by type
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*/
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/*5210 only has 2 queues*/
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if (ah->ah_version == AR5K_AR5210) {
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switch (queue_type) {
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case AR5K_TX_QUEUE_DATA:
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queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
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break;
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case AR5K_TX_QUEUE_BEACON:
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case AR5K_TX_QUEUE_CAB:
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queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
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break;
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default:
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return -EINVAL;
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}
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} else {
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switch (queue_type) {
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case AR5K_TX_QUEUE_DATA:
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for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
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ah->ah_txq[queue].tqi_type !=
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AR5K_TX_QUEUE_INACTIVE; queue++) {
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if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
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return -EINVAL;
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}
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break;
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case AR5K_TX_QUEUE_UAPSD:
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queue = AR5K_TX_QUEUE_ID_UAPSD;
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break;
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case AR5K_TX_QUEUE_BEACON:
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queue = AR5K_TX_QUEUE_ID_BEACON;
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break;
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case AR5K_TX_QUEUE_CAB:
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queue = AR5K_TX_QUEUE_ID_CAB;
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break;
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case AR5K_TX_QUEUE_XR_DATA:
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if (ah->ah_version != AR5K_AR5212)
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ATH5K_ERR(ah->ah_sc,
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"XR data queues only supported in"
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" 5212!\n");
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queue = AR5K_TX_QUEUE_ID_XR_DATA;
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break;
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default:
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return -EINVAL;
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}
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}
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/*
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* Setup internal queue structure
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*/
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memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
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ah->ah_txq[queue].tqi_type = queue_type;
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if (queue_info != NULL) {
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queue_info->tqi_type = queue_type;
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ret = ath5k_hw_set_tx_queueprops(ah, queue, queue_info);
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if (ret)
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return ret;
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}
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/*
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* We use ah_txq_status to hold a temp value for
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* the Secondary interrupt mask registers on 5211+
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* check out ath5k_hw_reset_tx_queue
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*/
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AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
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return queue;
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}
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/*
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* Get number of pending frames
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* for a specific queue [5211+]
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*/
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u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
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{
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u32 pending;
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
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/* Return if queue is declared inactive */
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if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
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return false;
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/* XXX: How about AR5K_CFG_TXCNT ? */
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if (ah->ah_version == AR5K_AR5210)
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return false;
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pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
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pending &= AR5K_QCU_STS_FRMPENDCNT;
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/* It's possible to have no frames pending even if TXE
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* is set. To indicate that q has not stopped return
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* true */
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if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
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return true;
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return pending;
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}
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/*
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* Set a transmit queue inactive
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*/
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void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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{
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ATH5K_TRACE(ah->ah_sc);
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if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
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return;
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/* This queue will be skipped in further operations */
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ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
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/*For SIMR setup*/
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AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
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}
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/*
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* Set DFS properties for a transmit queue on DCU
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*/
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int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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{
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u32 cw_min, cw_max, retry_lg, retry_sh;
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struct ath5k_txq_info *tq = &ah->ah_txq[queue];
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
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tq = &ah->ah_txq[queue];
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if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
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return 0;
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if (ah->ah_version == AR5K_AR5210) {
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/* Only handle data queues, others will be ignored */
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if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
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return 0;
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/* Set Slot time */
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
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AR5K_SLOT_TIME);
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/* Set ACK_CTS timeout */
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
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AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
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/* Set Transmit Latency */
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_TRANSMIT_LATENCY_TURBO :
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AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
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/* Set IFS0 */
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if (ah->ah_turbo) {
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ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
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(ah->ah_aifs + tq->tqi_aifs) *
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AR5K_INIT_SLOT_TIME_TURBO) <<
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AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
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AR5K_IFS0);
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} else {
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ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
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(ah->ah_aifs + tq->tqi_aifs) *
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AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
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AR5K_INIT_SIFS, AR5K_IFS0);
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}
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/* Set IFS1 */
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
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AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
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/* Set AR5K_PHY_SETTLING */
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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(ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
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| 0x38 :
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(ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
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| 0x1C,
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AR5K_PHY_SETTLING);
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/* Set Frame Control Register */
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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(AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
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AR5K_PHY_TURBO_SHORT | 0x2020) :
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(AR5K_PHY_FRAME_CTL_INI | 0x1020),
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AR5K_PHY_FRAME_CTL_5210);
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}
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/*
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* Calculate cwmin/max by channel mode
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*/
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cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
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cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
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ah->ah_aifs = AR5K_TUNE_AIFS;
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/*XR is only supported on 5212*/
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if (IS_CHAN_XR(ah->ah_current_channel) &&
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ah->ah_version == AR5K_AR5212) {
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cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
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cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
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ah->ah_aifs = AR5K_TUNE_AIFS_XR;
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/*B mode is not supported on 5210*/
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} else if (IS_CHAN_B(ah->ah_current_channel) &&
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ah->ah_version != AR5K_AR5210) {
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cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
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cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
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ah->ah_aifs = AR5K_TUNE_AIFS_11B;
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}
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cw_min = 1;
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while (cw_min < ah->ah_cw_min)
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cw_min = (cw_min << 1) | 1;
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cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
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((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
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cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
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((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
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/*
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* Calculate and set retry limits
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*/
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if (ah->ah_software_retry) {
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/* XXX Need to test this */
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retry_lg = ah->ah_limit_tx_retries;
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retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
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AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
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} else {
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retry_lg = AR5K_INIT_LG_RETRY;
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retry_sh = AR5K_INIT_SH_RETRY;
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}
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/*No QCU/DCU [5210]*/
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if (ah->ah_version == AR5K_AR5210) {
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ath5k_hw_reg_write(ah,
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(cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
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| AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
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AR5K_NODCU_RETRY_LMT_SLG_RETRY)
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| AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
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AR5K_NODCU_RETRY_LMT_SSH_RETRY)
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| AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
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| AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
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AR5K_NODCU_RETRY_LMT);
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} else {
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/*QCU/DCU [5211+]*/
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ath5k_hw_reg_write(ah,
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AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
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AR5K_DCU_RETRY_LMT_SLG_RETRY) |
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AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
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AR5K_DCU_RETRY_LMT_SSH_RETRY) |
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AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
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AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
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AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
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/*===Rest is also for QCU/DCU only [5211+]===*/
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/*
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* Set initial content window (cw_min/cw_max)
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* and arbitrated interframe space (aifs)...
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*/
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ath5k_hw_reg_write(ah,
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AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
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AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
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AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
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AR5K_DCU_LCL_IFS_AIFS),
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AR5K_QUEUE_DFS_LOCAL_IFS(queue));
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/*
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* Set misc registers
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*/
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/* Enable DCU early termination for this queue */
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AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
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AR5K_QCU_MISC_DCU_EARLY);
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/* Enable DCU to wait for next fragment from QCU */
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AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
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AR5K_DCU_MISC_FRAG_WAIT);
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/* On Maui and Spirit use the global seqnum on DCU */
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if (ah->ah_mac_version < AR5K_SREV_AR5211)
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AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
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AR5K_DCU_MISC_SEQNUM_CTL);
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if (tq->tqi_cbr_period) {
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ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
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AR5K_QCU_CBRCFG_INTVAL) |
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AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
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AR5K_QCU_CBRCFG_ORN_THRES),
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AR5K_QUEUE_CBRCFG(queue));
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AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
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AR5K_QCU_MISC_FRSHED_CBR);
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if (tq->tqi_cbr_overflow_limit)
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AR5K_REG_ENABLE_BITS(ah,
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AR5K_QUEUE_MISC(queue),
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AR5K_QCU_MISC_CBR_THRES_ENABLE);
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}
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if (tq->tqi_ready_time &&
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(tq->tqi_type != AR5K_TX_QUEUE_CAB))
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ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
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AR5K_QCU_RDYTIMECFG_INTVAL) |
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AR5K_QCU_RDYTIMECFG_ENABLE,
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AR5K_QUEUE_RDYTIMECFG(queue));
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if (tq->tqi_burst_time) {
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ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
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AR5K_DCU_CHAN_TIME_DUR) |
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AR5K_DCU_CHAN_TIME_ENABLE,
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AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
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if (tq->tqi_flags
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& AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
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AR5K_REG_ENABLE_BITS(ah,
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AR5K_QUEUE_MISC(queue),
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AR5K_QCU_MISC_RDY_VEOL_POLICY);
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}
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if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
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ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
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AR5K_QUEUE_DFS_MISC(queue));
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if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
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ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
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AR5K_QUEUE_DFS_MISC(queue));
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/*
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* Set registers by queue type
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*/
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switch (tq->tqi_type) {
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case AR5K_TX_QUEUE_BEACON:
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AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
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AR5K_QCU_MISC_FRSHED_DBA_GT |
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AR5K_QCU_MISC_CBREXP_BCN_DIS |
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AR5K_QCU_MISC_BCN_ENABLE);
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AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
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(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
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AR5K_DCU_MISC_ARBLOCK_CTL_S) |
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AR5K_DCU_MISC_ARBLOCK_IGNORE |
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AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
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AR5K_DCU_MISC_BCN_ENABLE);
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break;
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case AR5K_TX_QUEUE_CAB:
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AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
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AR5K_QCU_MISC_FRSHED_BCN_SENT_GT |
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AR5K_QCU_MISC_CBREXP_DIS |
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AR5K_QCU_MISC_CBREXP_BCN_DIS);
|
|
|
|
ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
|
|
(AR5K_TUNE_SW_BEACON_RESP -
|
|
AR5K_TUNE_DMA_BEACON_RESP) -
|
|
AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
|
|
AR5K_QCU_RDYTIMECFG_ENABLE,
|
|
AR5K_QUEUE_RDYTIMECFG(queue));
|
|
|
|
AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
|
|
(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
|
|
AR5K_DCU_MISC_ARBLOCK_CTL_S));
|
|
break;
|
|
|
|
case AR5K_TX_QUEUE_UAPSD:
|
|
AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
|
|
AR5K_QCU_MISC_CBREXP_DIS);
|
|
break;
|
|
|
|
case AR5K_TX_QUEUE_DATA:
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* TODO: Handle frame compression */
|
|
|
|
/*
|
|
* Enable interrupts for this tx queue
|
|
* in the secondary interrupt mask registers
|
|
*/
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
|
|
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
|
|
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
|
|
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
|
|
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
|
|
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
|
|
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
|
|
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
|
|
|
|
if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE)
|
|
AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
|
|
|
|
/* Update secondary interrupt mask registers */
|
|
|
|
/* Filter out inactive queues */
|
|
ah->ah_txq_imr_txok &= ah->ah_txq_status;
|
|
ah->ah_txq_imr_txerr &= ah->ah_txq_status;
|
|
ah->ah_txq_imr_txurn &= ah->ah_txq_status;
|
|
ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
|
|
ah->ah_txq_imr_txeol &= ah->ah_txq_status;
|
|
ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
|
|
ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
|
|
ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
|
|
ah->ah_txq_imr_nofrm &= ah->ah_txq_status;
|
|
|
|
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
|
|
AR5K_SIMR0_QCU_TXOK) |
|
|
AR5K_REG_SM(ah->ah_txq_imr_txdesc,
|
|
AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
|
|
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
|
|
AR5K_SIMR1_QCU_TXERR) |
|
|
AR5K_REG_SM(ah->ah_txq_imr_txeol,
|
|
AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
|
|
/* Update simr2 but don't overwrite rest simr2 settings */
|
|
AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
|
|
AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
|
|
AR5K_REG_SM(ah->ah_txq_imr_txurn,
|
|
AR5K_SIMR2_QCU_TXURN));
|
|
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
|
|
AR5K_SIMR3_QCBRORN) |
|
|
AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
|
|
AR5K_SIMR3_QCBRURN), AR5K_SIMR3);
|
|
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
|
|
AR5K_SIMR4_QTRIG), AR5K_SIMR4);
|
|
/* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
|
|
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
|
|
AR5K_TXNOFRM_QCU), AR5K_TXNOFRM);
|
|
/* No queue has TXNOFRM enabled, disable the interrupt
|
|
* by setting AR5K_TXNOFRM to zero */
|
|
if (ah->ah_txq_imr_nofrm == 0)
|
|
ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);
|
|
|
|
/* Set QCU mask for this DCU to save power */
|
|
AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Get slot time from DCU
|
|
*/
|
|
unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
|
|
{
|
|
ATH5K_TRACE(ah->ah_sc);
|
|
if (ah->ah_version == AR5K_AR5210)
|
|
return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
|
|
AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
|
|
else
|
|
return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
|
|
}
|
|
|
|
/*
|
|
* Set slot time on DCU
|
|
*/
|
|
int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
|
|
{
|
|
ATH5K_TRACE(ah->ah_sc);
|
|
if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
|
|
return -EINVAL;
|
|
|
|
if (ah->ah_version == AR5K_AR5210)
|
|
ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
|
|
ah->ah_turbo), AR5K_SLOT_TIME);
|
|
else
|
|
ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
|
|
|
|
return 0;
|
|
}
|
|
|