137 lines
4.0 KiB
C
137 lines
4.0 KiB
C
/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Code Aurora nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Part of this this code is based on the standard ARM spinlock
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* implementation (asm/spinlock.h) found in the 2.6.29 kernel.
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*/
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#ifndef __ASM__ARCH_QC_REMOTE_SPINLOCK_H
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#define __ASM__ARCH_QC_REMOTE_SPINLOCK_H
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#include <linux/types.h>
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#if defined(CONFIG_ARCH_MSM7X30)
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#define SMEM_DAL_SPINLOCK_BASE 0x1000
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struct dek_spinlock {
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volatile uint8_t self_lock;
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volatile uint8_t other_lock;
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volatile uint8_t next_yield;
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uint8_t pad;
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};
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typedef union {
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volatile uint32_t lock;
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struct dek_spinlock dek;
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} raw_remote_spinlock_t;
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#else
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typedef struct {
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volatile uint32_t lock;
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} raw_remote_spinlock_t;
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#endif
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typedef raw_remote_spinlock_t *_remote_spinlock_t;
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#if defined(CONFIG_ARCH_MSM7X30)
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#define remote_spin_lock_id_t const char *
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#else
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#define remote_spin_lock_id_t uint32_t
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#endif
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static inline void __raw_remote_ex_spin_lock(raw_remote_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]\n"
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" teqeq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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smp_mb();
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}
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static inline void __raw_remote_ex_spin_unlock(raw_remote_spinlock_t *lock)
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{
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smp_mb();
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__asm__ __volatile__(
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" str %1, [%0]\n"
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:
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: "r" (&lock->lock), "r" (0)
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: "cc");
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}
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static inline void __raw_remote_swp_spin_lock(raw_remote_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: swp %0, %2, [%1]\n"
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" teq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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smp_mb();
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}
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static inline void __raw_remote_swp_spin_unlock(raw_remote_spinlock_t *lock)
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{
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smp_mb();
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__asm__ __volatile__(
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" str %1, [%0]"
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:
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: "r" (&lock->lock), "r" (0)
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: "cc");
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}
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int _remote_spin_lock_init(remote_spin_lock_id_t id, _remote_spinlock_t *lock);
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/* Only use SWP-based spinlocks for ARM11 apps processors where the LDREX/STREX
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* instructions are unable to lock shared memory for exclusive access. */
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#if defined(CONFIG_ARCH_MSM7X30)
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void _remote_spin_lock(_remote_spinlock_t *lock);
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void _remote_spin_unlock(_remote_spinlock_t *lock);
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#elif defined(CONFIG_ARCH_MSM_ARM11)
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#define _remote_spin_lock(lock) __raw_remote_swp_spin_lock(*lock)
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#define _remote_spin_unlock(lock) __raw_remote_swp_spin_unlock(*lock)
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#else
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#define _remote_spin_lock(lock) __raw_remote_ex_spin_lock(*lock)
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#define _remote_spin_unlock(lock) __raw_remote_ex_spin_unlock(*lock)
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#endif /* CONFIG_ARCH_MSM_ARM11 */
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#endif /* __ASM__ARCH_QC_REMOTE_SPINLOCK_H */
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