163 lines
3.8 KiB
C
163 lines
3.8 KiB
C
/*
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* Copyright (c) 2005-2009 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*
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* Linux driver for Brocade Fibre Channel Host Bus Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <bfa_priv.h>
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#include <bfi/bfi_ctreg.h>
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#include <bfa_ioc.h>
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BFA_TRC_FILE(HAL, IOCFC_CT);
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static u32 __ct_msix_err_vec_reg[] = {
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HOST_MSIX_ERR_INDEX_FN0,
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HOST_MSIX_ERR_INDEX_FN1,
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HOST_MSIX_ERR_INDEX_FN2,
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HOST_MSIX_ERR_INDEX_FN3,
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};
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static void
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bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec)
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{
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int fn = bfa_ioc_pcifn(&bfa->ioc);
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bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc);
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if (msix)
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bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], vec);
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else
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bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], 0);
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}
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/**
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* Dummy interrupt handler for handling spurious interrupt during chip-reinit.
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*/
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static void
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bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
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{
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}
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void
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bfa_hwct_reginit(struct bfa_s *bfa)
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{
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struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
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bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc);
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int i, q, fn = bfa_ioc_pcifn(&bfa->ioc);
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if (fn == 0) {
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bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
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bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
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} else {
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bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
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bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
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}
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for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
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/*
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* CPE registers
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*/
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q = CPE_Q_NUM(fn, i);
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bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5));
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bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5));
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bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5));
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bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5));
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/*
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* RME registers
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*/
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q = CPE_Q_NUM(fn, i);
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bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5));
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bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5));
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bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5));
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bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5));
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}
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}
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void
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bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq)
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{
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u32 r32;
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r32 = bfa_reg_read(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
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bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq], r32);
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}
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void
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bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
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u32 *num_vecs, u32 *max_vec_bit)
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{
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*msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1;
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*max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1));
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*num_vecs = BFA_MSIX_CT_MAX;
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}
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/**
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* Setup MSI-X vector for catapult
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*/
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void
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bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
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{
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bfa_assert((nvecs == 1) || (nvecs == BFA_MSIX_CT_MAX));
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bfa_trc(bfa, nvecs);
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bfa->msix.nvecs = nvecs;
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bfa_hwct_msix_uninstall(bfa);
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}
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void
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bfa_hwct_msix_install(struct bfa_s *bfa)
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{
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int i;
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if (bfa->msix.nvecs == 0)
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return;
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if (bfa->msix.nvecs == 1) {
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for (i = 0; i < BFA_MSIX_CT_MAX; i++)
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bfa->msix.handler[i] = bfa_msix_all;
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return;
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}
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for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++)
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bfa->msix.handler[i] = bfa_msix_reqq;
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for (; i <= BFA_MSIX_RME_Q3; i++)
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bfa->msix.handler[i] = bfa_msix_rspq;
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bfa_assert(i == BFA_MSIX_LPU_ERR);
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bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err;
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}
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void
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bfa_hwct_msix_uninstall(struct bfa_s *bfa)
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{
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int i;
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for (i = 0; i < BFA_MSIX_CT_MAX; i++)
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bfa->msix.handler[i] = bfa_hwct_msix_dummy;
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}
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/**
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* Enable MSI-X vectors
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*/
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void
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bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
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{
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bfa_trc(bfa, 0);
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bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR);
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bfa_ioc_isr_mode_set(&bfa->ioc, msix);
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}
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