344 lines
8.7 KiB
Plaintext
344 lines
8.7 KiB
Plaintext
/*
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* Device Tree Source for AMCC Arches (dual 460GT board)
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*
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* (C) Copyright 2008 Applied Micro Circuits Corporation
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* Victor Gallardo <vgallardo@amcc.com>
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* Adam Graham <agraham@amcc.com>
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*
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* Based on the glacier.dts file
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* Stefan Roese <sr@denx.de>
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* Copyright 2008 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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model = "amcc,arches";
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compatible = "amcc,arches";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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ethernet0 = &EMAC0;
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ethernet1 = &EMAC1;
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ethernet2 = &EMAC2;
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serial0 = &UART0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,460GT";
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reg = <0x00000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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timebase-frequency = <0>; /* Filled in by U-Boot */
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
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};
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UIC0: interrupt-controller0 {
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compatible = "ibm,uic-460gt","ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-460gt","ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0x0d0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC2: interrupt-controller2 {
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compatible = "ibm,uic-460gt","ibm,uic";
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interrupt-controller;
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cell-index = <2>;
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dcr-reg = <0x0e0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC3: interrupt-controller3 {
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compatible = "ibm,uic-460gt","ibm,uic";
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interrupt-controller;
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cell-index = <3>;
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dcr-reg = <0x0f0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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SDR0: sdr {
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compatible = "ibm,sdr-460gt";
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dcr-reg = <0x00e 0x002>;
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};
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CPR0: cpr {
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compatible = "ibm,cpr-460gt";
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dcr-reg = <0x00c 0x002>;
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};
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L2C0: l2c {
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compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
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dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
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0x030 0x008>; /* L2 cache DCR's */
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cache-line-size = <32>; /* 32 bytes */
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cache-size = <262144>; /* L2, 256K */
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interrupt-parent = <&UIC1>;
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interrupts = <11 1>;
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};
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plb {
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compatible = "ibm,plb-460gt", "ibm,plb4";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; /* Filled in by U-Boot */
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SDRAM0: sdram {
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compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
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dcr-reg = <0x010 0x002>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <3>;
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num-rx-chans = <24>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-parent = <&UIC2>;
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interrupts = < /*TXEOB*/ 0x6 0x4
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/*RXEOB*/ 0x7 0x4
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/*SERR*/ 0x3 0x4
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/*TXDE*/ 0x4 0x4
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/*RXDE*/ 0x5 0x4>;
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desc-base-addr-high = <0x8>;
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};
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POB0: opb {
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compatible = "ibm,opb-460gt", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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EBC0: ebc {
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compatible = "ibm,ebc-460gt", "ibm,ebc";
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dcr-reg = <0x012 0x002>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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/* ranges property is supplied by U-Boot */
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interrupts = <0x6 0x4>;
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interrupt-parent = <&UIC1>;
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nor_flash@0,0 {
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compatible = "amd,s29gl256n", "cfi-flash";
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bank-width = <2>;
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reg = <0x00000000 0x00000000 0x02000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x001e0000>;
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};
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partition@1e0000 {
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label = "dtb";
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reg = <0x001e0000 0x00020000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x00200000 0x00200000>;
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};
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partition@400000 {
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label = "user";
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reg = <0x00400000 0x01b60000>;
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};
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partition@1f60000 {
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label = "env";
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reg = <0x01f60000 0x00040000>;
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};
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partition@1fa0000 {
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label = "u-boot";
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reg = <0x01fa0000 0x00060000>;
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};
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};
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};
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UART0: serial@ef600300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600300 0x00000008>;
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virtual-reg = <0xef600300>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>; /* Filled in by U-Boot */
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interrupt-parent = <&UIC1>;
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interrupts = <0x1 0x4>;
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};
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IIC0: i2c@ef600700 {
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compatible = "ibm,iic-460gt", "ibm,iic";
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reg = <0xef600700 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x2 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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sttm@4a {
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compatible = "ad,ad7414";
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reg = <0x4a>;
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interrupt-parent = <&UIC1>;
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interrupts = <0x0 0x8>;
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};
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};
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IIC1: i2c@ef600800 {
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compatible = "ibm,iic-460gt", "ibm,iic";
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reg = <0xef600800 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x3 0x4>;
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};
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TAH0: emac-tah@ef601350 {
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compatible = "ibm,tah-460gt", "ibm,tah";
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reg = <0xef601350 0x00000030>;
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};
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TAH1: emac-tah@ef601450 {
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compatible = "ibm,tah-460gt", "ibm,tah";
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reg = <0xef601450 0x00000030>;
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};
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EMAC0: ethernet@ef600e00 {
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device_type = "network";
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compatible = "ibm,emac-460gt", "ibm,emac4sync";
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interrupt-parent = <&EMAC0>;
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interrupts = <0x0 0x1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
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/*Wake*/ 0x1 &UIC2 0x14 0x4>;
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reg = <0xef600e00 0x000000c4>;
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local-mac-address = [000000000000]; /* Filled in by U-Boot */
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mal-device = <&MAL0>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "sgmii";
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phy-map = <0xffffffff>;
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gpcs-address = <0x0000000a>;
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tah-device = <&TAH0>;
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tah-channel = <0>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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EMAC1: ethernet@ef600f00 {
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device_type = "network";
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compatible = "ibm,emac-460gt", "ibm,emac4sync";
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interrupt-parent = <&EMAC1>;
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interrupts = <0x0 0x1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
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/*Wake*/ 0x1 &UIC2 0x15 0x4>;
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reg = <0xef600f00 0x000000c4>;
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local-mac-address = [000000000000]; /* Filled in by U-Boot */
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mal-device = <&MAL0>;
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mal-tx-channel = <1>;
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mal-rx-channel = <8>;
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cell-index = <1>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "sgmii";
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phy-map = <0x00000000>;
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gpcs-address = <0x0000000b>;
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tah-device = <&TAH1>;
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tah-channel = <1>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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mdio-device = <&EMAC0>;
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};
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EMAC2: ethernet@ef601100 {
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device_type = "network";
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compatible = "ibm,emac-460gt", "ibm,emac4sync";
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interrupt-parent = <&EMAC2>;
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interrupts = <0x0 0x1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
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/*Wake*/ 0x1 &UIC2 0x16 0x4>;
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reg = <0xef601100 0x000000c4>;
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local-mac-address = [000000000000]; /* Filled in by U-Boot */
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mal-device = <&MAL0>;
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mal-tx-channel = <2>;
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mal-rx-channel = <16>;
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cell-index = <2>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "sgmii";
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phy-map = <0x00000001>;
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gpcs-address = <0x0000000C>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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mdio-device = <&EMAC0>;
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};
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};
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};
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};
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