118 lines
3.5 KiB
C
118 lines
3.5 KiB
C
/*
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* arch/arm/mach-sa1100/include/mach/dma.h
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*
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* Generic SA1100 DMA support
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*
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* Copyright (C) 2000 Nicolas Pitre
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*
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*/
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H
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#include "hardware.h"
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/*
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* The SA1100 has six internal DMA channels.
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*/
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#define SA1100_DMA_CHANNELS 6
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/*
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* Maximum physical DMA buffer size
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*/
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#define MAX_DMA_SIZE 0x1fff
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#define CUT_DMA_SIZE 0x1000
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/*
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* All possible SA1100 devices a DMA channel can be attached to.
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*/
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typedef enum {
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DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */
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DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */
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DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */
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DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */
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DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */
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DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */
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DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */
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DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */
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DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */
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DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */
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DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */
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DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */
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DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */
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DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */
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DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */
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DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */
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DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */
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DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */
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} dma_device_t;
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typedef struct {
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volatile u_long DDAR;
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volatile u_long SetDCSR;
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volatile u_long ClrDCSR;
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volatile u_long RdDCSR;
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volatile dma_addr_t DBSA;
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volatile u_long DBTA;
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volatile dma_addr_t DBSB;
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volatile u_long DBTB;
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} dma_regs_t;
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typedef void (*dma_callback_t)(void *data);
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/*
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* DMA function prototypes
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*/
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extern int sa1100_request_dma( dma_device_t device, const char *device_id,
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dma_callback_t callback, void *data,
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dma_regs_t **regs );
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extern void sa1100_free_dma( dma_regs_t *regs );
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extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
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extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
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extern void sa1100_reset_dma(dma_regs_t *regs);
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/**
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* sa1100_stop_dma - stop DMA in progress
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* @regs: identifier for the channel to use
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*
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* This stops DMA without clearing buffer pointers. Unlike
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* sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
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* or sa1100_get_dma_pos().
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*
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* The @regs identifier is provided by a successful call to
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* sa1100_request_dma().
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**/
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#define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
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/**
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* sa1100_resume_dma - resume DMA on a stopped channel
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* @regs: identifier for the channel to use
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*
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* This resumes DMA on a channel previously stopped with
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* sa1100_stop_dma().
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*
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* The @regs identifier is provided by a successful call to
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* sa1100_request_dma().
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**/
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#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
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/**
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* sa1100_clear_dma - clear DMA pointers
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* @regs: identifier for the channel to use
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*
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* This clear any DMA state so the DMA engine is ready to restart
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* with new buffers through sa1100_start_dma(). Any buffers in flight
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* are discarded.
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*
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* The @regs identifier is provided by a successful call to
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* sa1100_request_dma().
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**/
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#define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
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#endif /* _ASM_ARCH_DMA_H */
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