150 lines
4.1 KiB
C
150 lines
4.1 KiB
C
/*
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* Copyright (C) 2004 by Basler Vision Technologies AG
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* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
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* Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/bitops.h>
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#include <asm/rm9k-ocd.h>
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#include <excite.h>
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extern struct pci_ops titan_pci_ops;
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static struct resource
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mem_resource = {
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.name = "PCI memory",
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.start = EXCITE_PHYS_PCI_MEM,
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.end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
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.flags = IORESOURCE_MEM
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},
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io_resource = {
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.name = "PCI I/O",
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.start = EXCITE_PHYS_PCI_IO,
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.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
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.flags = IORESOURCE_IO
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};
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static struct pci_controller bx_controller = {
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.pci_ops = &titan_pci_ops,
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.mem_resource = &mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &io_resource,
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.io_offset = 0x00000000UL
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};
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static char
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iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
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modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
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#define RM9000x2_OCD_HTSC 0x0604
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#define RM9000x2_OCD_HTBHL 0x060c
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#define RM9000x2_OCD_PCIHRST 0x078c
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#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
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#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
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#define PCISC_FB2B 0x00000200
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#define PCISC_MWICG 0x00000010
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#define PCISC_EMC 0x00000004
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#define PCISC_ERMA 0x00000002
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static int __init basler_excite_pci_setup(void)
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{
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const unsigned int fullbars = memsize / (256 << 20);
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unsigned int i;
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/* Check modebits to see if PCI is really enabled. */
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if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
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panic(modebits_no_pci);
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if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
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"Memory-mapped PCI I/O page"))
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panic(iopage_failed);
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/* Enable PCI 0 as master for config cycles */
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ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
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/* Set up latency timer */
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ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
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/* Setup host IO and Memory space */
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ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
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ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
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ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
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ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
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/* Set up PCI BARs to map all installed memory */
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for (i = 0; i < 6; i++) {
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const unsigned int bar = 0x610 + i * 4;
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if (i < fullbars) {
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ocd_writel(0x10000000 * i, bar);
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ocd_writel(0x01000000 * i, bar + 0x140);
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ocd_writel(0x0ffff029, bar + 0x100);
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continue;
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}
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if (i == fullbars) {
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int o;
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u32 mask;
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const unsigned long rem = memsize - i * 0x10000000;
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if (!rem) {
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ocd_writel(0x00000000, bar + 0x100);
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continue;
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}
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o = ffs(rem) - 1;
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if (rem & ~(0x1 << o))
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o++;
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mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
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ocd_writel(0x10000000 * i, bar);
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ocd_writel(0x01000000 * i, bar + 0x140);
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ocd_writel(0x00000029 | mask, bar + 0x100);
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continue;
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}
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ocd_writel(0x00000000, bar + 0x100);
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}
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/* Finally, enable the PCI interrupt */
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#if USB_IRQ > 7
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set_c0_intcontrol(1 << USB_IRQ);
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#else
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set_c0_status(1 << (USB_IRQ + 8));
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#endif
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ioport_resource.start = EXCITE_PHYS_PCI_IO;
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ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
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set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
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register_pci_controller(&bx_controller);
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return 0;
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}
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arch_initcall(basler_excite_pci_setup);
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