139 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			139 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * Copyright (C) 1994-1996  Linus Torvalds & authors
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 *
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 * Copied from i386; many of the especially older MIPS or ISA-based platforms
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 * are basically identical.  Using this file probably implies i8259 PIC
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 * support in a system but the very least interrupt numbers 0 - 15 need to
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 * be put aside for legacy devices.
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 */
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#ifndef __ASM_MACH_GENERIC_IDE_H
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#define __ASM_MACH_GENERIC_IDE_H
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#ifdef __KERNEL__
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#include <linux/pci.h>
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#include <linux/stddef.h>
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#include <asm/processor.h>
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/* MIPS port and memory-mapped I/O string operations.  */
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static inline void __ide_flush_prologue(void)
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{
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#ifdef CONFIG_SMP
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	if (cpu_has_dc_aliases)
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		preempt_disable();
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#endif
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}
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static inline void __ide_flush_epilogue(void)
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{
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#ifdef CONFIG_SMP
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	if (cpu_has_dc_aliases)
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		preempt_enable();
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#endif
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}
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static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
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{
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	if (cpu_has_dc_aliases) {
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		unsigned long end = addr + size;
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		while (addr < end) {
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			local_flush_data_cache_page((void *)addr);
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			addr += PAGE_SIZE;
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		}
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	}
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}
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/*
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 * insw() and gang might be called with interrupts disabled, so we can't
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 * send IPIs for flushing due to the potencial of deadlocks, see the comment
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 * above smp_call_function() in arch/mips/kernel/smp.c.  We work around the
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 * problem by disabling preemption so we know we actually perform the flush
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 * on the processor that actually has the lines to be flushed which hopefully
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 * is even better for performance anyway.
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 */
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static inline void __ide_insw(unsigned long port, void *addr,
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	unsigned int count)
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{
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	__ide_flush_prologue();
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	insw(port, addr, count);
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	__ide_flush_dcache_range((unsigned long)addr, count * 2);
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	__ide_flush_epilogue();
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}
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static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
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{
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	__ide_flush_prologue();
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	insl(port, addr, count);
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	__ide_flush_dcache_range((unsigned long)addr, count * 4);
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	__ide_flush_epilogue();
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}
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static inline void __ide_outsw(unsigned long port, const void *addr,
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	unsigned long count)
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{
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	__ide_flush_prologue();
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	outsw(port, addr, count);
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	__ide_flush_dcache_range((unsigned long)addr, count * 2);
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	__ide_flush_epilogue();
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}
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static inline void __ide_outsl(unsigned long port, const void *addr,
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	unsigned long count)
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{
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	__ide_flush_prologue();
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	outsl(port, addr, count);
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	__ide_flush_dcache_range((unsigned long)addr, count * 4);
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	__ide_flush_epilogue();
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}
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static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
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{
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	__ide_flush_prologue();
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	readsw(port, addr, count);
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	__ide_flush_dcache_range((unsigned long)addr, count * 2);
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	__ide_flush_epilogue();
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}
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static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
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{
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	__ide_flush_prologue();
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	readsl(port, addr, count);
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	__ide_flush_dcache_range((unsigned long)addr, count * 4);
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	__ide_flush_epilogue();
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}
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static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
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{
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	__ide_flush_prologue();
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	writesw(port, addr, count);
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	__ide_flush_dcache_range((unsigned long)addr, count * 2);
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	__ide_flush_epilogue();
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}
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static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
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{
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	__ide_flush_prologue();
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	writesl(port, addr, count);
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	__ide_flush_dcache_range((unsigned long)addr, count * 4);
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	__ide_flush_epilogue();
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}
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/* ide_insw calls insw, not __ide_insw.  Why? */
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#undef insw
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#undef insl
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#undef outsw
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#undef outsl
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#define insw(port, addr, count) __ide_insw(port, addr, count)
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#define insl(port, addr, count) __ide_insl(port, addr, count)
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#define outsw(port, addr, count) __ide_outsw(port, addr, count)
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#define outsl(port, addr, count) __ide_outsl(port, addr, count)
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#endif /* __KERNEL__ */
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#endif /* __ASM_MACH_GENERIC_IDE_H */
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