687 lines
21 KiB
C
687 lines
21 KiB
C
/*
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* Copyright (c) 2009 Google, Inc.
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* Copyright (c) 2008 QUALCOMM Incorporated.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/mutex.h>
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#include <linux/errno.h>
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#include <linux/cpufreq.h>
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#include <linux/regulator/consumer.h>
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#include <mach/board.h>
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#include <mach/msm_iomap.h>
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#include "acpuclock.h"
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#include "proc_comm.h"
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#include "clock.h"
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#if 0
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#define DEBUG(x...) pr_info(x)
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#else
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#define DEBUG(x...) do {} while (0)
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#endif
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#define SHOT_SWITCH 4
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#define HOP_SWITCH 5
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#define SIMPLE_SLEW 6
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#define COMPLEX_SLEW 7
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#define SPSS_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
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#define SPSS_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
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/* Scorpion PLL registers */
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#define SCPLL_CTL_ADDR (MSM_SCPLL_BASE + 0x4)
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#define SCPLL_STATUS_ADDR (MSM_SCPLL_BASE + 0x18)
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#define SCPLL_FSM_CTL_EXT_ADDR (MSM_SCPLL_BASE + 0x10)
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struct clkctl_acpu_speed {
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unsigned acpu_khz;
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unsigned clk_cfg;
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unsigned clk_sel;
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unsigned sc_l_value;
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unsigned lpj;
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int vdd;
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unsigned axiclk_khz;
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};
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/* clock sources */
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#define CLK_TCXO 0 /* 19.2 MHz */
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#define CLK_GLOBAL_PLL 1 /* 768 MHz */
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#define CLK_MODEM_PLL 4 /* 245 MHz (UMTS) or 235.93 MHz (CDMA) */
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#define CCTL(src, div) (((src) << 4) | (div - 1))
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/* core sources */
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#define SRC_RAW 0 /* clock from SPSS_CLK_CNTL */
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#define SRC_SCPLL 1 /* output of scpll 128-998 MHZ */
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#define SRC_AXI 2 /* 128 MHz */
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#define SRC_PLL1 3 /* 768 MHz */
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struct clkctl_acpu_speed acpu_freq_tbl[] = {
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#ifdef CONFIG_HTCLEO_UNDERVOLT_1000
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{ 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 1000, 14000 },
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{ 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 1000, 14000 },
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{ 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 1000, 29000 },
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//{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1000, 29000 },
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{ 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 1000, 58000 },
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{ 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 1000, 117000 },
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{ 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1000, 117000 },
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{ 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1025, 117000 },
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{ 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1050, 117000 },
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{ 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1050, 117000 },
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{ 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1075, 117000 },
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{ 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1100, 117000 },
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{ 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1125, 117000 },
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{ 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1150, 117000 },
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{ 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1150, 128000 },
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{ 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1175, 128000 },
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{ 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1200, 128000 },
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{ 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1200, 128000 },
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{ 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1225, 128000 },
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{ 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1225, 128000 },
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{ 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1225, 128000 },
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#elif CONFIG_HTCLEO_UNDERVOLT_925
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// should work with most of HD2s
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{ 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 925, 14000 },
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{ 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 925, 14000 },
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{ 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 925, 29000 },
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//{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 925, 29000 },
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{ 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 950, 58000 },
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{ 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 975, 117000 },
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{ 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1000, 117000 },
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{ 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1025, 117000 },
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{ 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1050, 117000 },
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{ 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1050, 117000 },
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{ 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1075, 117000 },
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{ 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1100, 117000 },
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{ 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1125, 117000 },
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{ 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1150, 117000 },
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{ 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1150, 128000 },
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{ 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1175, 128000 },
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{ 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1200, 128000 },
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{ 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1200, 128000 },
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{ 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1225, 128000 },
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{ 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1225, 128000 },
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{ 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1225, 128000 },
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#elif CONFIG_HTCLEO_UNDERVOLT_800
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// not working yet
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{ 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 850, 14000 },
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{ 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 850, 14000 },
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{ 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 850, 29000 },
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//{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 850, 29000 },
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{ 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 850, 58000 },
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{ 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 875, 117000 },
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{ 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 900, 117000 },
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{ 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 925, 117000 },
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{ 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 950, 117000 },
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{ 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 950, 117000 },
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{ 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 975, 117000 },
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{ 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1000, 117000 },
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{ 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1025, 117000 },
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{ 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1050, 117000 },
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{ 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1125, 128000 },
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{ 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1125, 128000 },
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{ 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1150, 128000 },
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{ 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1150, 128000 },
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{ 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1175, 128000 },
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{ 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1175, 128000 },
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{ 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1200, 128000 },
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#else
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{ 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 1050, 14000},
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{ 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 1050, 14000 },
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{ 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 1050, 29000 },
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/* Work arround for acpu resume hung, GPLL is turn off by arm9 */
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/*{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1050, 29000 },*/
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{ 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 1050, 58000 },
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{ 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 1050, 117000 },
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{ 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1050, 117000 },
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{ 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1075, 117000 },
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{ 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1100, 117000 },
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{ 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1100, 117000 },
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{ 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1125, 117000 },
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{ 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1150, 117000 },
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{ 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1175, 117000 },
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{ 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1200, 117000 },
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{ 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1200, 128000 },
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{ 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1225, 128000 },
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{ 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1250, 128000 },
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{ 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1275, 128000 },
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{ 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1300, 128000 },
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{ 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1300, 128000 },
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{ 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1300, 128000 },
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#endif
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#ifdef CONFIG_HTCLEO_OVERCLOCK
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#ifdef CONFIG_HTCLEO_UNDERVOLT_1000
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{ 1036800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1B, 0, 1225, 128000 },
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{ 1075200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1C, 0, 1250, 128000 },
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{ 1113600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1275, 128000 },
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#elif CONFIG_HTCLEO_UNDERVOLT_925
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{ 1036800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1B, 0, 1225, 128000 },
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{ 1075200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1C, 0, 1250, 128000 },
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{ 1113600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1275, 128000 },
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#elif CONFIG_HTCLEO_UNDERVOLT_800
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{ 1036800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1B, 0, 1225, 128000 },
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{ 1075200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1C, 0, 1250, 128000 },
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{ 1113600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1275, 128000 },
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#else
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{ 1036800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1B, 0, 1300, 128000 },
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{ 1075200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1C, 0, 1300, 128000 },
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{ 1113600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1300, 128000 },
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#endif
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#endif
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#ifdef CONFIG_HTCLEO_EXOVERCLOCK
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{ 1152000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1E, 0, 1300, 128000 },
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{ 1190400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1F, 0, 1300, 128000 },
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#endif
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{ 0 },
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};
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/* select the standby clock that is used when switching scpll
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* frequencies
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*
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* Currently: MPLL
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*/
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struct clkctl_acpu_speed *acpu_stby = &acpu_freq_tbl[2];
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#define IS_ACPU_STANDBY(x) (((x)->clk_cfg == acpu_stby->clk_cfg) && \
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((x)->clk_sel == acpu_stby->clk_sel))
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struct clkctl_acpu_speed *acpu_mpll = &acpu_freq_tbl[2];
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#ifdef CONFIG_CPU_FREQ_TABLE
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static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(acpu_freq_tbl)];
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static void __init acpuclk_init_cpufreq_table(void)
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{
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int i;
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int vdd;
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for (i = 0; acpu_freq_tbl[i].acpu_khz; i++) {
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freq_table[i].index = i;
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freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
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/* Skip speeds we don't want */
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if ( acpu_freq_tbl[i].acpu_khz == 19200 ||
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acpu_freq_tbl[i].acpu_khz == 128000 ||
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acpu_freq_tbl[i].acpu_khz == 256000)
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continue;
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vdd = acpu_freq_tbl[i].vdd;
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/* Allow mpll and the first scpll speeds */
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if (acpu_freq_tbl[i].acpu_khz == acpu_mpll->acpu_khz ||
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acpu_freq_tbl[i].acpu_khz == 384000) {
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freq_table[i].frequency = acpu_freq_tbl[i].acpu_khz;
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continue;
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}
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/* hastarin - Take every frequency. Just because it has the
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same vdd does not mean it has the same current draw */
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freq_table[i].frequency = acpu_freq_tbl[i].acpu_khz;
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}
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freq_table[i].index = i;
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freq_table[i].frequency = CPUFREQ_TABLE_END;
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cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
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}
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#else
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#define acpuclk_init_cpufreq_table() do {} while (0);
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#endif
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struct clock_state {
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struct clkctl_acpu_speed *current_speed;
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struct mutex lock;
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uint32_t acpu_switch_time_us;
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uint32_t max_speed_delta_khz;
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uint32_t vdd_switch_time_us;
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unsigned long power_collapse_khz;
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unsigned long wait_for_irq_khz;
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struct clk* clk_ebi1;
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struct regulator *regulator;
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};
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static struct clock_state drv_state = { 0 };
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struct clk *clk_get(struct device *dev, const char *id);
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unsigned long clk_get_rate(struct clk *clk);
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int clk_set_rate(struct clk *clk, unsigned long rate);
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static DEFINE_SPINLOCK(acpu_lock);
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#define PLLMODE_POWERDOWN 0
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#define PLLMODE_BYPASS 1
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#define PLLMODE_STANDBY 2
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#define PLLMODE_FULL_CAL 4
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#define PLLMODE_HALF_CAL 5
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#define PLLMODE_STEP_CAL 6
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#define PLLMODE_NORMAL 7
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#define PLLMODE_MASK 7
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static void scpll_power_down(void)
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{
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uint32_t val;
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/* Wait for any frequency switches to finish. */
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while (readl(SCPLL_STATUS_ADDR) & 0x1)
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;
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/* put the pll in standby mode */
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val = readl(SCPLL_CTL_ADDR);
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val = (val & (~PLLMODE_MASK)) | PLLMODE_STANDBY;
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writel(val, SCPLL_CTL_ADDR);
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dmb();
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/* wait to stabilize in standby mode */
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udelay(10);
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val = (val & (~PLLMODE_MASK)) | PLLMODE_POWERDOWN;
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writel(val, SCPLL_CTL_ADDR);
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dmb();
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}
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static void scpll_set_freq(uint32_t lval)
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{
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uint32_t val, ctl;
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if (lval > 33)
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lval = 33;
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if (lval < 10)
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lval = 10;
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/* wait for any calibrations or frequency switches to finish */
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while (readl(SCPLL_STATUS_ADDR) & 0x3)
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;
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ctl = readl(SCPLL_CTL_ADDR);
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if ((ctl & PLLMODE_MASK) != PLLMODE_NORMAL) {
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/* put the pll in standby mode */
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writel((ctl & (~PLLMODE_MASK)) | PLLMODE_STANDBY, SCPLL_CTL_ADDR);
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dmb();
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/* wait to stabilize in standby mode */
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udelay(10);
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/* switch to 384 MHz */
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val = readl(SCPLL_FSM_CTL_EXT_ADDR);
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val = (val & (~0x1FF)) | (0x0A << 3) | SHOT_SWITCH;
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writel(val, SCPLL_FSM_CTL_EXT_ADDR);
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dmb();
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ctl = readl(SCPLL_CTL_ADDR);
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writel(ctl | PLLMODE_NORMAL, SCPLL_CTL_ADDR);
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dmb();
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/* wait for frequency switch to finish */
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while (readl(SCPLL_STATUS_ADDR) & 0x1)
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;
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/* completion bit is not reliable for SHOT switch */
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udelay(25);
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}
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/* write the new L val and switch mode */
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val = readl(SCPLL_FSM_CTL_EXT_ADDR);
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val = (val & (~0x1FF)) | (lval << 3) | HOP_SWITCH;
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writel(val, SCPLL_FSM_CTL_EXT_ADDR);
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dmb();
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ctl = readl(SCPLL_CTL_ADDR);
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writel(ctl | PLLMODE_NORMAL, SCPLL_CTL_ADDR);
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dmb();
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/* wait for frequency switch to finish */
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while (readl(SCPLL_STATUS_ADDR) & 0x1)
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;
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}
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/* this is still a bit weird... */
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static void select_clock(unsigned src, unsigned config)
|
|
{
|
|
uint32_t val;
|
|
|
|
if (src == SRC_RAW) {
|
|
uint32_t sel = readl(SPSS_CLK_SEL_ADDR);
|
|
unsigned shift = (sel & 1) ? 8 : 0;
|
|
|
|
/* set other clock source to the new configuration */
|
|
val = readl(SPSS_CLK_CNTL_ADDR);
|
|
val = (val & (~(0x7F << shift))) | (config << shift);
|
|
writel(val, SPSS_CLK_CNTL_ADDR);
|
|
|
|
/* switch to other clock source */
|
|
writel(sel ^ 1, SPSS_CLK_SEL_ADDR);
|
|
|
|
dmb(); /* necessary? */
|
|
}
|
|
|
|
/* switch to new source */
|
|
val = readl(SPSS_CLK_SEL_ADDR) & (~6);
|
|
writel(val | ((src & 3) << 1), SPSS_CLK_SEL_ADDR);
|
|
}
|
|
|
|
static int acpuclk_set_vdd_level(int vdd)
|
|
{
|
|
if (!drv_state.regulator || IS_ERR(drv_state.regulator)) {
|
|
drv_state.regulator = regulator_get(NULL, "acpu_vcore");
|
|
if (IS_ERR(drv_state.regulator)) {
|
|
pr_info("acpuclk_set_vdd_level %d no regulator\n", vdd);
|
|
/* Assume that the PMIC supports scaling the processor
|
|
* to its maximum frequency at its default voltage.
|
|
*/
|
|
return 0;
|
|
}
|
|
pr_info("acpuclk_set_vdd_level got regulator\n");
|
|
}
|
|
vdd *= 1000; /* mV -> uV */
|
|
return regulator_set_voltage(drv_state.regulator, vdd, vdd);
|
|
}
|
|
|
|
int acpuclk_set_rate(unsigned long rate, enum setrate_reason reason)
|
|
{
|
|
struct clkctl_acpu_speed *cur, *next;
|
|
unsigned long flags;
|
|
|
|
cur = drv_state.current_speed;
|
|
|
|
/* convert to KHz */
|
|
rate /= 1000;
|
|
|
|
DEBUG("acpuclk_set_rate(%d,%d)\n", (int) rate, reason);
|
|
|
|
if (rate == cur->acpu_khz || rate == 0)
|
|
return 0;
|
|
|
|
next = acpu_freq_tbl;
|
|
for (;;) {
|
|
if (next->acpu_khz == rate)
|
|
break;
|
|
if (next->acpu_khz == 0)
|
|
return -EINVAL;
|
|
next++;
|
|
}
|
|
|
|
if (reason == SETRATE_CPUFREQ) {
|
|
mutex_lock(&drv_state.lock);
|
|
/* Increase VDD if needed. */
|
|
if (next->vdd > cur->vdd) {
|
|
if (acpuclk_set_vdd_level(next->vdd)) {
|
|
pr_err("acpuclock: Unable to increase ACPU VDD.\n");
|
|
mutex_unlock(&drv_state.lock);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
}
|
|
|
|
spin_lock_irqsave(&acpu_lock, flags);
|
|
|
|
DEBUG("sel=%d cfg=%02x lv=%02x -> sel=%d, cfg=%02x lv=%02x\n",
|
|
cur->clk_sel, cur->clk_cfg, cur->sc_l_value,
|
|
next->clk_sel, next->clk_cfg, next->sc_l_value);
|
|
|
|
if (next->clk_sel == SRC_SCPLL) {
|
|
/* curr -> standby(MPLL speed) -> target */
|
|
if (!IS_ACPU_STANDBY(cur))
|
|
select_clock(acpu_stby->clk_sel, acpu_stby->clk_cfg);
|
|
loops_per_jiffy = next->lpj;
|
|
scpll_set_freq(next->sc_l_value);
|
|
select_clock(SRC_SCPLL, 0);
|
|
} else {
|
|
loops_per_jiffy = next->lpj;
|
|
if (cur->clk_sel == SRC_SCPLL) {
|
|
select_clock(acpu_stby->clk_sel, acpu_stby->clk_cfg);
|
|
select_clock(next->clk_sel, next->clk_cfg);
|
|
scpll_power_down();
|
|
} else {
|
|
select_clock(next->clk_sel, next->clk_cfg);
|
|
}
|
|
}
|
|
|
|
drv_state.current_speed = next;
|
|
|
|
spin_unlock_irqrestore(&acpu_lock, flags);
|
|
|
|
#ifndef CONFIG_AXI_SCREEN_POLICY
|
|
if (reason == SETRATE_CPUFREQ || reason == SETRATE_PC) {
|
|
if (cur->axiclk_khz != next->axiclk_khz)
|
|
clk_set_rate(drv_state.clk_ebi1, next->axiclk_khz * 1000);
|
|
DEBUG("acpuclk_set_rate switch axi to %d\n",
|
|
clk_get_rate(drv_state.clk_ebi1));
|
|
}
|
|
#endif
|
|
if (reason == SETRATE_CPUFREQ) {
|
|
/* Drop VDD level if we can. */
|
|
if (next->vdd < cur->vdd) {
|
|
if (acpuclk_set_vdd_level(next->vdd))
|
|
pr_err("acpuclock: Unable to drop ACPU VDD.\n");
|
|
}
|
|
mutex_unlock(&drv_state.lock);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned __init acpuclk_find_speed(void)
|
|
{
|
|
uint32_t sel, val;
|
|
|
|
sel = readl(SPSS_CLK_SEL_ADDR);
|
|
switch ((sel & 6) >> 1) {
|
|
case 1:
|
|
val = readl(SCPLL_FSM_CTL_EXT_ADDR);
|
|
val = (val >> 3) & 0x3f;
|
|
return val * 38400;
|
|
case 2:
|
|
return 128000;
|
|
default:
|
|
pr_err("acpu_find_speed: failed\n");
|
|
BUG();
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
#define PCOM_MODEM_PLL 0
|
|
static int pll_request(unsigned id, unsigned on)
|
|
{
|
|
on = !!on;
|
|
return msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
|
|
}
|
|
|
|
/* Spare register populated with efuse data on max ACPU freq. */
|
|
#define CT_CSR_PHYS 0xA8700000
|
|
#define TCSR_SPARE2_ADDR (ct_csr_base + 0x60)
|
|
|
|
void __init acpu_freq_tbl_fixup(void)
|
|
{
|
|
void __iomem *ct_csr_base;
|
|
uint32_t tcsr_spare2;
|
|
unsigned int max_acpu_khz;
|
|
unsigned int i;
|
|
|
|
ct_csr_base = ioremap(CT_CSR_PHYS, PAGE_SIZE);
|
|
BUG_ON(ct_csr_base == NULL);
|
|
|
|
tcsr_spare2 = readl(TCSR_SPARE2_ADDR);
|
|
|
|
/* Check if the register is supported and meaningful. */
|
|
if ((tcsr_spare2 & 0xF000) != 0xA000) {
|
|
pr_info("Efuse data on Max ACPU freq not present.\n");
|
|
goto skip_efuse_fixup;
|
|
}
|
|
|
|
switch (tcsr_spare2 & 0xF0) {
|
|
case 0x70:
|
|
max_acpu_khz = 768000;
|
|
break;
|
|
case 0x30:
|
|
case 0x00:
|
|
#ifdef CONFIG_HTCLEO_EXOVERCLOCK
|
|
max_acpu_khz = 1190400;
|
|
#elif CONFIG_HTCLEO_OVERCLOCK
|
|
max_acpu_khz = 1113600;
|
|
#else
|
|
max_acpu_khz = 998400;
|
|
#endif
|
|
break;
|
|
case 0x10:
|
|
max_acpu_khz = 1267200;
|
|
break;
|
|
default:
|
|
pr_warning("Invalid efuse data (%x) on Max ACPU freq!\n",
|
|
tcsr_spare2);
|
|
goto skip_efuse_fixup;
|
|
}
|
|
|
|
pr_info("Max ACPU freq from efuse data is %d KHz\n", max_acpu_khz);
|
|
|
|
for (i = 0; acpu_freq_tbl[i].acpu_khz != 0; i++) {
|
|
if (acpu_freq_tbl[i].acpu_khz > max_acpu_khz) {
|
|
acpu_freq_tbl[i].acpu_khz = 0;
|
|
break;
|
|
}
|
|
}
|
|
skip_efuse_fixup:
|
|
iounmap(ct_csr_base);
|
|
}
|
|
|
|
static void __init acpuclk_init(void)
|
|
{
|
|
struct clkctl_acpu_speed *speed;
|
|
unsigned init_khz;
|
|
|
|
init_khz = acpuclk_find_speed();
|
|
|
|
/* request the modem pll, and then drop it. We don't want to keep a
|
|
* ref to it, but we do want to make sure that it is initialized at
|
|
* this point. The ARM9 will ensure that the MPLL is always on
|
|
* once it is fully booted, but it may not be up by the time we get
|
|
* to here. So, our pll_request for it will block until the mpll is
|
|
* actually up. We want it up because we will want to use it as a
|
|
* temporary step during frequency scaling. */
|
|
pll_request(PCOM_MODEM_PLL, 1);
|
|
pll_request(PCOM_MODEM_PLL, 0);
|
|
|
|
if (!(readl(MSM_CLK_CTL_BASE + 0x300) & 1)) {
|
|
pr_err("%s: MPLL IS NOT ON!!! RUN AWAY!!\n", __func__);
|
|
BUG();
|
|
}
|
|
|
|
/* Move to 768MHz for boot, which is a safe frequency
|
|
* for all versions of Scorpion at the moment.
|
|
*/
|
|
speed = acpu_freq_tbl;
|
|
for (;;) {
|
|
#ifdef CONFIG_HTCLEO_EXOVERCLOCK
|
|
if (speed->acpu_khz == 998400)
|
|
break;
|
|
#elif CONFIG_HTCLEO_OVERCLOCK
|
|
if (speed->acpu_khz == 883200)
|
|
break;
|
|
#else
|
|
if (speed->acpu_khz == 768000)
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_HTCLEO_EXOVERCLOCK
|
|
if (speed->acpu_khz == 0) {
|
|
pr_err("acpuclk_init: cannot find 998.4MHz\n");
|
|
#elif CONFIG_HTCLEO_OVERCLOCK
|
|
if (speed->acpu_khz == 0) {
|
|
pr_err("acpuclk_init: cannot find 883.2MHz\n");
|
|
#else
|
|
if (speed->acpu_khz == 0) {
|
|
pr_err("acpuclk_init: cannot find 768MHz\n");
|
|
#endif
|
|
BUG();
|
|
}
|
|
speed++;
|
|
}
|
|
|
|
if (init_khz != speed->acpu_khz) {
|
|
/* Bootloader needs to have SCPLL operating, but we're
|
|
* going to step over to the standby clock and make sure
|
|
* we select the right frequency on SCPLL and then
|
|
* step back to it, to make sure we're sane here.
|
|
*/
|
|
select_clock(acpu_stby->clk_sel, acpu_stby->clk_cfg);
|
|
scpll_power_down();
|
|
scpll_set_freq(speed->sc_l_value);
|
|
select_clock(SRC_SCPLL, 0);
|
|
}
|
|
drv_state.current_speed = speed;
|
|
|
|
for (speed = acpu_freq_tbl; speed->acpu_khz; speed++)
|
|
speed->lpj = cpufreq_scale(loops_per_jiffy,
|
|
init_khz, speed->acpu_khz);
|
|
|
|
loops_per_jiffy = drv_state.current_speed->lpj;
|
|
}
|
|
|
|
unsigned long acpuclk_get_rate(void)
|
|
{
|
|
return drv_state.current_speed->acpu_khz;
|
|
}
|
|
|
|
uint32_t acpuclk_get_switch_time(void)
|
|
{
|
|
return drv_state.acpu_switch_time_us;
|
|
}
|
|
|
|
unsigned long acpuclk_power_collapse(int from_idle)
|
|
{
|
|
int ret = acpuclk_get_rate();
|
|
enum setrate_reason reason = (from_idle) ? SETRATE_PC_IDLE : SETRATE_PC;
|
|
if (ret > drv_state.power_collapse_khz)
|
|
acpuclk_set_rate(drv_state.power_collapse_khz * 1000, reason);
|
|
return ret * 1000;
|
|
}
|
|
|
|
unsigned long acpuclk_get_wfi_rate(void)
|
|
{
|
|
return drv_state.wait_for_irq_khz * 1000;
|
|
}
|
|
|
|
unsigned long acpuclk_wait_for_irq(void)
|
|
{
|
|
int ret = acpuclk_get_rate();
|
|
if (ret > drv_state.wait_for_irq_khz)
|
|
acpuclk_set_rate(drv_state.wait_for_irq_khz * 1000, SETRATE_SWFI);
|
|
return ret * 1000;
|
|
}
|
|
|
|
void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
|
|
{
|
|
spin_lock_init(&acpu_lock);
|
|
mutex_init(&drv_state.lock);
|
|
|
|
drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
|
|
drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
|
|
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
|
|
drv_state.power_collapse_khz = clkdata->power_collapse_khz;
|
|
drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
|
|
|
|
if (clkdata->mpll_khz)
|
|
acpu_mpll->acpu_khz = clkdata->mpll_khz;
|
|
|
|
acpu_freq_tbl_fixup();
|
|
acpuclk_init();
|
|
acpuclk_init_cpufreq_table();
|
|
drv_state.clk_ebi1 = clk_get(NULL,"ebi1_clk");
|
|
#ifndef CONFIG_AXI_SCREEN_POLICY
|
|
clk_set_rate(drv_state.clk_ebi1, drv_state.current_speed->axiclk_khz * 1000);
|
|
#endif
|
|
}
|