376 lines
		
	
	
		
			8.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			376 lines
		
	
	
		
			8.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
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|  * (http://www.opencores.org/projects.cgi/web/i2c/overview).
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|  *
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|  * Peter Korsgaard <jacmet@sunsite.dk>
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|  *
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|  * This file is licensed under the terms of the GNU General Public License
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|  * version 2.  This program is licensed "as is" without any warranty of any
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|  * kind, whether express or implied.
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|  */
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| 
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| #include <linux/kernel.h>
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| #include <linux/module.h>
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| #include <linux/init.h>
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| #include <linux/errno.h>
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| #include <linux/platform_device.h>
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| #include <linux/i2c.h>
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| #include <linux/interrupt.h>
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| #include <linux/wait.h>
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| #include <linux/i2c-ocores.h>
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| #include <asm/io.h>
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| 
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| struct ocores_i2c {
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| 	void __iomem *base;
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| 	int regstep;
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| 	wait_queue_head_t wait;
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| 	struct i2c_adapter adap;
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| 	struct i2c_msg *msg;
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| 	int pos;
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| 	int nmsgs;
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| 	int state; /* see STATE_ */
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| 	int clock_khz;
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| };
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| 
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| /* registers */
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| #define OCI2C_PRELOW		0
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| #define OCI2C_PREHIGH		1
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| #define OCI2C_CONTROL		2
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| #define OCI2C_DATA		3
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| #define OCI2C_CMD		4 /* write only */
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| #define OCI2C_STATUS		4 /* read only, same address as OCI2C_CMD */
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| 
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| #define OCI2C_CTRL_IEN		0x40
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| #define OCI2C_CTRL_EN		0x80
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| 
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| #define OCI2C_CMD_START		0x91
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| #define OCI2C_CMD_STOP		0x41
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| #define OCI2C_CMD_READ		0x21
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| #define OCI2C_CMD_WRITE		0x11
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| #define OCI2C_CMD_READ_ACK	0x21
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| #define OCI2C_CMD_READ_NACK	0x29
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| #define OCI2C_CMD_IACK		0x01
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| 
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| #define OCI2C_STAT_IF		0x01
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| #define OCI2C_STAT_TIP		0x02
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| #define OCI2C_STAT_ARBLOST	0x20
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| #define OCI2C_STAT_BUSY		0x40
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| #define OCI2C_STAT_NACK		0x80
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| 
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| #define STATE_DONE		0
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| #define STATE_START		1
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| #define STATE_WRITE		2
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| #define STATE_READ		3
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| #define STATE_ERROR		4
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| 
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| static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
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| {
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| 	iowrite8(value, i2c->base + reg * i2c->regstep);
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| }
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| 
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| static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
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| {
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| 	return ioread8(i2c->base + reg * i2c->regstep);
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| }
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| 
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| static void ocores_process(struct ocores_i2c *i2c)
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| {
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| 	struct i2c_msg *msg = i2c->msg;
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| 	u8 stat = oc_getreg(i2c, OCI2C_STATUS);
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| 
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| 	if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
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| 		/* stop has been sent */
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| 		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
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| 		wake_up(&i2c->wait);
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| 		return;
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| 	}
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| 
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| 	/* error? */
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| 	if (stat & OCI2C_STAT_ARBLOST) {
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| 		i2c->state = STATE_ERROR;
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| 		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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| 		return;
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| 	}
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| 
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| 	if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
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| 		i2c->state =
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| 			(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
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| 
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| 		if (stat & OCI2C_STAT_NACK) {
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| 			i2c->state = STATE_ERROR;
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| 			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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| 			return;
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| 		}
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| 	} else
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| 		msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
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| 
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| 	/* end of msg? */
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| 	if (i2c->pos == msg->len) {
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| 		i2c->nmsgs--;
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| 		i2c->msg++;
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| 		i2c->pos = 0;
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| 		msg = i2c->msg;
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| 
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| 		if (i2c->nmsgs) {	/* end? */
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| 			/* send start? */
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| 			if (!(msg->flags & I2C_M_NOSTART)) {
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| 				u8 addr = (msg->addr << 1);
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| 
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| 				if (msg->flags & I2C_M_RD)
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| 					addr |= 1;
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| 
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| 				i2c->state = STATE_START;
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| 
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| 				oc_setreg(i2c, OCI2C_DATA, addr);
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| 				oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
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| 				return;
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| 			} else
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| 				i2c->state = (msg->flags & I2C_M_RD)
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| 					? STATE_READ : STATE_WRITE;
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| 		} else {
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| 			i2c->state = STATE_DONE;
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| 			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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| 			return;
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| 		}
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| 	}
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| 
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| 	if (i2c->state == STATE_READ) {
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| 		oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
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| 			  OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
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| 	} else {
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| 		oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
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| 		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
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| 	}
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| }
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| 
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| static irqreturn_t ocores_isr(int irq, void *dev_id)
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| {
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| 	struct ocores_i2c *i2c = dev_id;
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| 
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| 	ocores_process(i2c);
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| 
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| 	return IRQ_HANDLED;
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| }
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| 
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| static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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| {
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| 	struct ocores_i2c *i2c = i2c_get_adapdata(adap);
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| 
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| 	i2c->msg = msgs;
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| 	i2c->pos = 0;
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| 	i2c->nmsgs = num;
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| 	i2c->state = STATE_START;
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| 
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| 	oc_setreg(i2c, OCI2C_DATA,
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| 			(i2c->msg->addr << 1) |
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| 			((i2c->msg->flags & I2C_M_RD) ? 1:0));
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| 
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| 	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
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| 
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| 	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
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| 			       (i2c->state == STATE_DONE), HZ))
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| 		return (i2c->state == STATE_DONE) ? num : -EIO;
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| 	else
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| 		return -ETIMEDOUT;
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| }
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| 
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| static void ocores_init(struct ocores_i2c *i2c)
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| {
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| 	int prescale;
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| 	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
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| 
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| 	/* make sure the device is disabled */
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| 	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
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| 
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| 	prescale = (i2c->clock_khz / (5*100)) - 1;
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| 	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
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| 	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
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| 
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| 	/* Init the device */
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| 	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
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| 	oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
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| }
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| 
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| 
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| static u32 ocores_func(struct i2c_adapter *adap)
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| {
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| 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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| }
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| 
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| static const struct i2c_algorithm ocores_algorithm = {
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| 	.master_xfer	= ocores_xfer,
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| 	.functionality	= ocores_func,
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| };
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| 
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| static struct i2c_adapter ocores_adapter = {
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| 	.owner		= THIS_MODULE,
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| 	.name		= "i2c-ocores",
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| 	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,
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| 	.algo		= &ocores_algorithm,
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| };
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| 
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| 
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| static int __devinit ocores_i2c_probe(struct platform_device *pdev)
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| {
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| 	struct ocores_i2c *i2c;
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| 	struct ocores_i2c_platform_data *pdata;
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| 	struct resource *res, *res2;
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| 	int ret;
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| 	int i;
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| 
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| 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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| 	if (!res)
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| 		return -ENODEV;
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| 
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| 	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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| 	if (!res2)
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| 		return -ENODEV;
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| 
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| 	pdata = (struct ocores_i2c_platform_data*) pdev->dev.platform_data;
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| 	if (!pdata)
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| 		return -ENODEV;
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| 
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| 	i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
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| 	if (!i2c)
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| 		return -ENOMEM;
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| 
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| 	if (!request_mem_region(res->start, resource_size(res),
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| 				pdev->name)) {
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| 		dev_err(&pdev->dev, "Memory region busy\n");
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| 		ret = -EBUSY;
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| 		goto request_mem_failed;
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| 	}
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| 
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| 	i2c->base = ioremap(res->start, resource_size(res));
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| 	if (!i2c->base) {
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| 		dev_err(&pdev->dev, "Unable to map registers\n");
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| 		ret = -EIO;
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| 		goto map_failed;
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| 	}
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| 
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| 	i2c->regstep = pdata->regstep;
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| 	i2c->clock_khz = pdata->clock_khz;
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| 	ocores_init(i2c);
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| 
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| 	init_waitqueue_head(&i2c->wait);
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| 	ret = request_irq(res2->start, ocores_isr, 0, pdev->name, i2c);
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| 	if (ret) {
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| 		dev_err(&pdev->dev, "Cannot claim IRQ\n");
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| 		goto request_irq_failed;
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| 	}
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| 
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| 	/* hook up driver to tree */
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| 	platform_set_drvdata(pdev, i2c);
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| 	i2c->adap = ocores_adapter;
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| 	i2c_set_adapdata(&i2c->adap, i2c);
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| 	i2c->adap.dev.parent = &pdev->dev;
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| 
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| 	/* add i2c adapter to i2c tree */
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| 	ret = i2c_add_adapter(&i2c->adap);
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| 	if (ret) {
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| 		dev_err(&pdev->dev, "Failed to add adapter\n");
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| 		goto add_adapter_failed;
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| 	}
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| 
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| 	/* add in known devices to the bus */
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| 	for (i = 0; i < pdata->num_devices; i++)
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| 		i2c_new_device(&i2c->adap, pdata->devices + i);
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| 
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| 	return 0;
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| 
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| add_adapter_failed:
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| 	free_irq(res2->start, i2c);
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| request_irq_failed:
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| 	iounmap(i2c->base);
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| map_failed:
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| 	release_mem_region(res->start, resource_size(res));
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| request_mem_failed:
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| 	kfree(i2c);
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| 
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| 	return ret;
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| }
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| 
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| static int __devexit ocores_i2c_remove(struct platform_device* pdev)
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| {
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| 	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
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| 	struct resource *res;
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| 
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| 	/* disable i2c logic */
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| 	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
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| 		  & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
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| 
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| 	/* remove adapter & data */
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| 	i2c_del_adapter(&i2c->adap);
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| 	platform_set_drvdata(pdev, NULL);
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| 
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| 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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| 	if (res)
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| 		free_irq(res->start, i2c);
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| 
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| 	iounmap(i2c->base);
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| 
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| 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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| 	if (res)
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| 		release_mem_region(res->start, resource_size(res));
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| 
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| 	kfree(i2c);
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| 
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| 	return 0;
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| }
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| 
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| #ifdef CONFIG_PM
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| static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state)
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| {
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| 	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
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| 	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
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| 
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| 	/* make sure the device is disabled */
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| 	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
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| 
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| 	return 0;
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| }
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| 
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| static int ocores_i2c_resume(struct platform_device *pdev)
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| {
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| 	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
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| 
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| 	ocores_init(i2c);
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| 
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| 	return 0;
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| }
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| #else
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| #define ocores_i2c_suspend	NULL
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| #define ocores_i2c_resume	NULL
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| #endif
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| 
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| /* work with hotplug and coldplug */
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| MODULE_ALIAS("platform:ocores-i2c");
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| 
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| static struct platform_driver ocores_i2c_driver = {
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| 	.probe   = ocores_i2c_probe,
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| 	.remove  = __devexit_p(ocores_i2c_remove),
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| 	.suspend = ocores_i2c_suspend,
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| 	.resume  = ocores_i2c_resume,
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| 	.driver  = {
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| 		.owner = THIS_MODULE,
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| 		.name = "ocores-i2c",
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| 	},
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| };
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| 
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| static int __init ocores_i2c_init(void)
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| {
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| 	return platform_driver_register(&ocores_i2c_driver);
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| }
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| 
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| static void __exit ocores_i2c_exit(void)
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| {
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| 	platform_driver_unregister(&ocores_i2c_driver);
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| }
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| 
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| module_init(ocores_i2c_init);
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| module_exit(ocores_i2c_exit);
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| 
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| MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
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| MODULE_DESCRIPTION("OpenCores I2C bus driver");
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| MODULE_LICENSE("GPL");
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