412 lines
12 KiB
C
412 lines
12 KiB
C
#ifndef _TPI_H_
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#define _TPI_H_
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#define TPI_PIX_CLK_LSB (0x00)
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#define TPI_PIX_CLK_MSB (0x01)
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#define TPI_VERT_FREQ_LSB (0x02)
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#define TPI_VERT_FREQ_MSB (0x03)
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#define TPI_TOTAL_PIX_LSB (0x04)
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#define TPI_TOTAL_PIX_MSB (0x05)
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#define TPI_TOTAL_LINES_LSB (0x06)
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#define TPI_TOTAL_LINES_MSB (0x07)
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// Pixel Repetition Data
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//======================
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#define TPI_PIX_REPETITION (0x08)
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// TPI AVI Input and Output Format Data
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//=====================================
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/// AVI Input Format Data ================================================= ///
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#define TPI_INPUT_FORMAT_REG (0x09)
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//Finish this...
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#define INPUT_COLOR_SPACE_MASK (BIT_1 | BIT_0)
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#define INPUT_COLOR_SPACE_RGB (0x00)
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#define INPUT_COLOR_SPACE_YCBCR444 (0x01)
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#define INPUT_COLOR_SPACE_YCBCR422 (0x02)
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#define INPUT_COLOR_SPACE_BLACK_MODE (0x03)
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/// AVI Output Format Data ================================================ ///
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#define TPI_OUTPUT_FORMAT_REG (0x0A)
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#define TPI_YC_Input_Mode (0x0B)
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// TPI AVI InfoFrame Data
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//=======================
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#define TPI_AVI_BYTE_0 (0x0C)
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#define TPI_AVI_BYTE_1 (0x0D)
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#define TPI_AVI_BYTE_2 (0x0E)
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#define TPI_AVI_BYTE_3 (0x0F)
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#define TPI_AVI_BYTE_4 (0x10)
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#define TPI_AVI_BYTE_5 (0x11)
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#define TPI_AUDIO_BYTE_0 (0xBF)
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#define TPI_INFO_FRM_DBYTE5 0xC8
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#define TPI_INFO_FRM_DBYTE6 0xC9
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#define TPI_END_TOP_BAR_LSB (0x12)
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#define TPI_END_TOP_BAR_MSB (0x13)
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#define TPI_START_BTM_BAR_LSB (0x14)
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#define TPI_START_BTM_BAR_MSB (0x15)
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#define TPI_END_LEFT_BAR_LSB (0x16)
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#define TPI_END_LEFT_BAR_MSB (0x17)
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#define TPI_END_RIGHT_BAR_LSB (0x18)
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#define TPI_END_RIGHT_BAR_MSB (0x19)
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// Colorimetry
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//============
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#define SET_EX_COLORIMETRY 0x0C // Set TPI_AVI_BYTE_2 to extended colorimetry and use
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//TPI_AVI_BYTE_3
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// ===================================================== //
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#define TPI_SYSTEM_CONTROL_DATA_REG (0x1A)
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#define LINK_INTEGRITY_MODE_MASK (BIT_6)
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#define LINK_INTEGRITY_STATIC (0x00)
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#define LINK_INTEGRITY_DYNAMIC (0x40)
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#define TMDS_OUTPUT_CONTROL_MASK (BIT_4)
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#define TMDS_OUTPUT_CONTROL_ACTIVE (0x00)
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#define TMDS_OUTPUT_CONTROL_POWER_DOWN (0x10)
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#define AV_MUTE_MASK (BIT_3)
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#define AV_MUTE_NORMAL (0x00)
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#define AV_MUTE_MUTED (0x08)
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#define DDC_BUS_REQUEST_MASK (BIT_2)
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#define DDC_BUS_REQUEST_NOT_USING (0x00)
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#define DDC_BUS_REQUEST_REQUESTED (0x04)
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#define DDC_BUS_GRANT_MASK (BIT_1)
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#define DDC_BUS_GRANT_NOT_AVAILABLE (0x00)
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#define DDC_BUS_GRANT_GRANTED (0x02)
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#define OUTPUT_MODE_MASK (BIT_0)
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#define OUTPUT_MODE_DVI (0x00)
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#define OUTPUT_MODE_HDMI (0x01)
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// TPI Identification Registers
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//=============================
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#define TPI_DEVICE_ID (0x1B)
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#define TPI_DEVICE_REV_ID (0x1C)
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#define TPI_RESERVED2 (0x1D)
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// ===================================================== //
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#define TPI_DEVICE_POWER_STATE_CTRL_REG (0x1E)
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#define CTRL_PIN_CONTROL_MASK (BIT_4)
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#define CTRL_PIN_TRISTATE (0x00)
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#define CTRL_PIN_DRIVEN_TX_BRIDGE (0x10)
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#define TX_POWER_STATE_MASK (BIT_1 | BIT_0)
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#define TX_POWER_STATE_D0 (0x00)
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#define TX_POWER_STATE_D1 (0x01)
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#define TX_POWER_STATE_D2 (0x02)
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#define TX_POWER_STATE_D3 (0x03)
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// Configuration of I2S Interface
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//===============================
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#define TPI_I2S_EN (0x1F)
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#define TPI_I2S_IN_CFG (0x20)
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// Available only when TPI 0x26[7:6]=10 to select I2S input
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//=========================================================
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#define TPI_I2S_CHST_0 (0x21)
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#define TPI_I2S_CHST_1 (0x22)
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#define TPI_I2S_CHST_2 (0x23)
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#define TPI_I2S_CHST_3 (0x24)
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#define TPI_I2S_CHST_4 (0x25)
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// Available only when 0x26[7:6]=01
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//=================================
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#define TPI_SPDIF_HEADER (0x24)
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#define TPI_AUDIO_HANDLING (0x25)
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// Audio Configuration Regiaters
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//==============================
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#define TPI_AUDIO_INTERFACE_REG (0x26)
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// Finish this...
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#define AUDIO_MUTE_MASK (BIT_4)
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#define AUDIO_MUTE_NORMAL (0x00)
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#define AUDIO_MUTE_MUTED (0x10)
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#define TPI_AUDIO_SAMPLE_CTRL (0x27)
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#define TPI_SPEAKER_CFG (0xC7)
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#define TPI_CHANNEL_COUNT (0xC4)
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/// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ///
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/*\
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| | HDCP Implementation
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| | HDCP link security logic is implemented in certain transmitters; unique
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| | keys are embedded in each chip as part of the solution. The security
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| | scheme is fully automatic and handled completely by the hardware.
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\*/
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/// HDCP Query Data Register ============================================== ///
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#define TPI_HDCP_QUERY_DATA_REG (0x29)
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#define EXTENDED_LINK_PROTECTION_MASK (BIT_7)
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#define EXTENDED_LINK_PROTECTION_NONE (0x00)
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#define EXTENDED_LINK_PROTECTION_SECURE (0x80)
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#define LOCAL_LINK_PROTECTION_MASK (BIT_6)
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#define LOCAL_LINK_PROTECTION_NONE (0x00)
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#define LOCAL_LINK_PROTECTION_SECURE (0x40)
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#define LINK_STATUS_MASK (BIT_5 | BIT_4)
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#define LINK_STATUS_NORMAL (0x00)
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#define LINK_STATUS_LINK_LOST (0x10)
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#define LINK_STATUS_RENEGOTIATION_REQ (0x20)
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#define LINK_STATUS_LINK_SUSPENDED (0x30)
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#define HDCP_REPEATER_MASK (BIT_3)
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#define HDCP_REPEATER_NO (0x00)
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#define HDCP_REPEATER_YES (0x08)
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#define CONNECTOR_TYPE_MASK (BIT_2 | BIT_0)
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#define CONNECTOR_TYPE_DVI (0x00)
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#define CONNECTOR_TYPE_RSVD (0x01)
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#define CONNECTOR_TYPE_HDMI (0x04)
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#define CONNECTOR_TYPE_FUTURE (0x05)
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#define PROTECTION_TYPE_MASK (BIT_1)
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#define PROTECTION_TYPE_NONE (0x00)
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#define PROTECTION_TYPE_HDCP (0x02)
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/// HDCP Control Data Register ============================================ ///
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#define TPI_HDCP_CONTROL_DATA_REG (0x2A)
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#define PROTECTION_LEVEL_MASK (BIT_0)
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#define PROTECTION_LEVEL_MIN (0x00)
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#define PROTECTION_LEVEL_MAX (0x01)
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/// HDCP BKSV Registers =================================================== ///
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#define TPI_BKSV_1_REG (0x2B)
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#define TPI_BKSV_2_REG (0x2C)
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#define TPI_BKSV_3_REG (0x2D)
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#define TPI_BKSV_4_REG (0x2E)
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#define TPI_BKSV_5_REG (0x2F)
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/// HDCP Revision Data Register =========================================== ///
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#define TPI_HDCP_REVISION_DATA_REG (0x30)
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#define HDCP_MAJOR_REVISION_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4)
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#define HDCP_MAJOR_REVISION_VALUE (0x10)
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#define HDCP_MINOR_REVISION_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
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#define HDCP_MINOR_REVISION_VALUE (0x02)
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/// HDCP KSV and V' Value Data Register =================================== ///
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#define TPI_V_PRIME_SELECTOR_REG (0x31)
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/// V' Value Readback Registers =========================================== ///
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#define TPI_V_PRIME_7_0_REG (0x32)
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#define TPI_V_PRIME_15_9_REG (0x33)
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#define TPI_V_PRIME_23_16_REG (0x34)
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#define TPI_V_PRIME_31_24_REG (0x35)
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/// HDCP AKSV Registers =================================================== ///
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#define TPI_AKSV_1_REG (0x36)
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#define TPI_AKSV_2_REG (0x37)
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#define TPI_AKSV_3_REG (0x38)
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#define TPI_AKSV_4_REG (0x39)
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#define TPI_AKSV_5_REG (0x3A)
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/*\
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| | Interrupt Service
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| | TPI can be configured to generate an interrupt to the host to notify it of
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| | various events. The host can either poll for activity or use an interrupt
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| | handler routine. TPI generates on a single interrupt (INT) to the host.
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\*/
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/// Interrupt Enable Register ============================================= ///
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#define TPI_INTERRUPT_ENABLE_REG (0x3C)
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#define HDCP_AUTH_STATUS_CHANGE_EN_MASK (BIT_7)
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#define HDCP_AUTH_STATUS_CHANGE_DISABLE (0x00)
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#define HDCP_AUTH_STATUS_CHANGE_ENABLE (0x80)
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#define HDCP_VPRIME_VALUE_READY_EN_MASK (BIT_6)
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#define HDCP_VPRIME_VALUE_READY_DISABLE (0x00)
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#define HDCP_VPRIME_VALUE_READY_ENABLE (0x40)
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#define HDCP_SECURITY_CHANGE_EN_MASK (BIT_5)
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#define HDCP_SECURITY_CHANGE_DISABLE (0x00)
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#define HDCP_SECURITY_CHANGE_ENABLE (0x20)
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#define AUDIO_ERROR_EVENT_EN_MASK (BIT_4)
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#define AUDIO_ERROR_EVENT_DISABLE (0x00)
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#define AUDIO_ERROR_EVENT_ENABLE (0x10)
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#define CPI_EVENT_NO_RX_SENSE_MASK (BIT_3)
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#define CPI_EVENT_NO_RX_SENSE_DISABLE (0x00)
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#define CPI_EVENT_NO_RX_SENSE_ENABLE (0x08)
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#define RECEIVER_SENSE_EVENT_EN_MASK (BIT_1)
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#define RECEIVER_SENSE_EVENT_DISABLE (0x00)
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#define RECEIVER_SENSE_EVENT_ENABLE (0x02)
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#define HOT_PLUG_EVENT_EN_MASK (BIT_0)
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#define HOT_PLUG_EVENT_DISABLE (0x00)
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#define HOT_PLUG_EVENT_ENABLE (0x01)
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/// Interrupt Status Register ============================================= ///
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#define TPI_INTERRUPT_STATUS_REG (0x3D)
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#define HDCP_AUTH_STATUS_CHANGE_EVENT_MASK (BIT_7)
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#define HDCP_AUTH_STATUS_CHANGE_EVENT_NO (0x00)
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#define HDCP_AUTH_STATUS_CHANGE_EVENT_YES (0x80)
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#define HDCP_VPRIME_VALUE_READY_EVENT_MASK (BIT_6)
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#define HDCP_VPRIME_VALUE_READY_EVENT_NO (0x00)
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#define HDCP_VPRIME_VALUE_READY_EVENT_YES (0x40)
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#define HDCP_SECURITY_CHANGE_EVENT_MASK (BIT_5)
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#define HDCP_SECURITY_CHANGE_EVENT_NO (0x00)
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#define HDCP_SECURITY_CHANGE_EVENT_YES (0x20)
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#define AUDIO_ERROR_EVENT_MASK (BIT_4)
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#define AUDIO_ERROR_EVENT_NO (0x00)
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#define AUDIO_ERROR_EVENT_YES (0x10)
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#define CPI_EVENT_MASK (BIT_3)
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#define CPI_EVENT_NO (0x00)
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#define CPI_EVENT_YES (0x08)
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#define RX_SENSE_MASK (BIT_3) // This bit is dual purpose depending on the value of 0x3C[3]
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#define RX_SENSE_NOT_ATTACHED (0x00)
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#define RX_SENSE_ATTACHED (0x08)
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#define HOT_PLUG_PIN_STATE_MASK (BIT_2)
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#define HOT_PLUG_PIN_STATE_LOW (0x00)
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#define HOT_PLUG_PIN_STATE_HIGH (0x04)
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#define RECEIVER_SENSE_EVENT_MASK (BIT_1)
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#define RECEIVER_SENSE_EVENT_NO (0x00)
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#define RECEIVER_SENSE_EVENT_YES (0x02)
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#define HOT_PLUG_EVENT_MASK (BIT_0)
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#define HOT_PLUG_EVENT_NO (0x00)
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#define HOT_PLUG_EVENT_YES (0x01)
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/// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ///
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// Sync Register Configuration and Sync Monitoring Registers
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//==========================================================
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#define TPI_SYNC_GEN_CTRL (0x60)
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#define TPI_SYNC_POLAR_DETECT (0x61)
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// Explicit Sync DE Generator Registers (TPI 0x60[7]=0)
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//=====================================================
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#define TPI_DE_DLY (0x62)
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#define TPI_DE_CTRL (0x63)
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#define TPI_DE_TOP (0x64)
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#define TPI_RESERVED4 (0x65)
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#define TPI_DE_CNT_7_0 (0x66)
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#define TPI_DE_CNT_11_8 (0x67)
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#define TPI_DE_LIN_7_0 (0x68)
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#define TPI_DE_LIN_10_8 (0x69)
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#define TPI_DE_H_RES_7_0 (0x6A)
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#define TPI_DE_H_RES_10_8 (0x6B)
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#define TPI_DE_V_RES_7_0 (0x6C)
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#define TPI_DE_V_RES_10_8 (0x6D)
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// Embedded Sync Register Set (TPI 0x60[7]=1)
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//===========================================
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#define TPI_HBIT_TO_HSYNC_7_0 (0x62)
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#define TPI_HBIT_TO_HSYNC_9_8 (0x63)
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#define TPI_FIELD_2_OFFSET_7_0 (0x64)
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#define TPI_FIELD_2_OFFSET_11_8 (0x65)
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#define TPI_HWIDTH_7_0 (0x66)
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#define TPI_HWIDTH_8_9 (0x67)
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#define TPI_VBIT_TO_VSYNC (0x68)
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#define TPI_VWIDTH (0x69)
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// TPI Enable Register
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//====================
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#define TPI_ENABLE (0xC7)
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// Misc InfoFrames
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//================
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#define MISC_INFO_FRAMES_CTRL (0xBF)
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#define MISC_INFO_FRAMES_TYPE (0xC0)
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#define MISC_INFO_FRAMES_VER (0xC1)
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#define MISC_INFO_FRAMES_LEN (0xC2)
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#define MISC_INFO_FRAMES_CHKSUM (0xC3)
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// Backdoor Register Offsets
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//==========================
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#define INTERNAL_PAGE_0 0x00
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#define INTERNAL_PAGE_1 0x01
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#define DEVICE_ID_LOW_BYTE 0x02
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#define DEVICE_ID_HI_BYTE 0x03
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#define AUDIO_INPUT_LENGTH 0x24
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#define SW_RESET 0x05
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#define POWER_DOWN 0x6F
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// Backdoor constants
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//===================
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#define DIV_BY_2 0x00
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#define MULT_BY_1 0x01
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#define MULT_BY_2 0x02
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#define MULT_BY_4 0x03
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#define INTERNAL_PAGE_1 0x01
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#define INTERNAL_PAGE_2 0x02
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#define TMDS_CONT_REG 0x82
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#endif
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