542 lines
14 KiB
C
542 lines
14 KiB
C
/*
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* This file is part of wl1271
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/gpio.h>
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#include "wl1271_acx.h"
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#include "wl1271_reg.h"
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#include "wl1271_boot.h"
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#include "wl1271_spi.h"
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#include "wl1271_event.h"
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static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
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[PART_DOWN] = {
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.mem = {
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.start = 0x00000000,
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.size = 0x000177c0
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},
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.reg = {
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.start = REGISTERS_BASE,
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.size = 0x00008800
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},
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},
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[PART_WORK] = {
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.mem = {
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.start = 0x00040000,
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.size = 0x00014fc0
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},
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.reg = {
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.start = REGISTERS_BASE,
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.size = 0x0000b000
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},
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},
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[PART_DRPW] = {
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.mem = {
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.start = 0x00040000,
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.size = 0x00014fc0
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},
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.reg = {
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.start = DRPW_BASE,
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.size = 0x00006000
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}
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}
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};
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static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
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{
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u32 cpu_ctrl;
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/* 10.5.0 run the firmware (I) */
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cpu_ctrl = wl1271_reg_read32(wl, ACX_REG_ECPU_CONTROL);
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/* 10.5.1 run the firmware (II) */
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cpu_ctrl |= flag;
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wl1271_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
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}
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static void wl1271_boot_fw_version(struct wl1271 *wl)
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{
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struct wl1271_static_data static_data;
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wl1271_spi_mem_read(wl, wl->cmd_box_addr,
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&static_data, sizeof(static_data));
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strncpy(wl->chip.fw_ver, static_data.fw_version,
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sizeof(wl->chip.fw_ver));
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/* make sure the string is NULL-terminated */
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wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
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}
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static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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size_t fw_data_len, u32 dest)
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{
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int addr, chunk_num, partition_limit;
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u8 *p;
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/* whal_FwCtrl_LoadFwImageSm() */
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wl1271_debug(DEBUG_BOOT, "starting firmware upload");
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wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
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fw_data_len, CHUNK_SIZE);
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if ((fw_data_len % 4) != 0) {
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wl1271_error("firmware length not multiple of four");
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return -EIO;
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}
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wl1271_set_partition(wl, dest,
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part_table[PART_DOWN].mem.size,
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part_table[PART_DOWN].reg.start,
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part_table[PART_DOWN].reg.size);
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/* 10.1 set partition limit and chunk num */
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chunk_num = 0;
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partition_limit = part_table[PART_DOWN].mem.size;
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while (chunk_num < fw_data_len / CHUNK_SIZE) {
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/* 10.2 update partition, if needed */
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addr = dest + (chunk_num + 2) * CHUNK_SIZE;
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if (addr > partition_limit) {
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addr = dest + chunk_num * CHUNK_SIZE;
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partition_limit = chunk_num * CHUNK_SIZE +
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part_table[PART_DOWN].mem.size;
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/* FIXME: Over 80 chars! */
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wl1271_set_partition(wl,
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addr,
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part_table[PART_DOWN].mem.size,
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part_table[PART_DOWN].reg.start,
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part_table[PART_DOWN].reg.size);
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}
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/* 10.3 upload the chunk */
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addr = dest + chunk_num * CHUNK_SIZE;
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p = buf + chunk_num * CHUNK_SIZE;
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wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
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p, addr);
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wl1271_spi_mem_write(wl, addr, p, CHUNK_SIZE);
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chunk_num++;
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}
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/* 10.4 upload the last chunk */
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addr = dest + chunk_num * CHUNK_SIZE;
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p = buf + chunk_num * CHUNK_SIZE;
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wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
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fw_data_len % CHUNK_SIZE, p, addr);
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wl1271_spi_mem_write(wl, addr, p, fw_data_len % CHUNK_SIZE);
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return 0;
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}
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static int wl1271_boot_upload_firmware(struct wl1271 *wl)
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{
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u32 chunks, addr, len;
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u8 *fw;
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fw = wl->fw;
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chunks = be32_to_cpup((u32 *) fw);
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fw += sizeof(u32);
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wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
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while (chunks--) {
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addr = be32_to_cpup((u32 *) fw);
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fw += sizeof(u32);
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len = be32_to_cpup((u32 *) fw);
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fw += sizeof(u32);
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if (len > 300000) {
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wl1271_info("firmware chunk too long: %u", len);
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return -EINVAL;
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}
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wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
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chunks, addr, len);
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wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
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fw += len;
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}
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return 0;
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}
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static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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{
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size_t nvs_len, burst_len;
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int i;
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u32 dest_addr, val;
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u8 *nvs_ptr, *nvs, *nvs_aligned;
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nvs = wl->nvs;
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if (nvs == NULL)
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return -ENODEV;
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nvs_ptr = nvs;
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nvs_len = wl->nvs_len;
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/* Update the device MAC address into the nvs */
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nvs[11] = wl->mac_addr[0];
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nvs[10] = wl->mac_addr[1];
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nvs[6] = wl->mac_addr[2];
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nvs[5] = wl->mac_addr[3];
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nvs[4] = wl->mac_addr[4];
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nvs[3] = wl->mac_addr[5];
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/*
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* Layout before the actual NVS tables:
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* 1 byte : burst length.
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* 2 bytes: destination address.
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* n bytes: data to burst copy.
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*
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* This is ended by a 0 length, then the NVS tables.
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*/
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/* FIXME: Do we need to check here whether the LSB is 1? */
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while (nvs_ptr[0]) {
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burst_len = nvs_ptr[0];
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dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
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/* FIXME: Due to our new wl1271_translate_reg_addr function,
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we need to add the REGISTER_BASE to the destination */
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dest_addr += REGISTERS_BASE;
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/* We move our pointer to the data */
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nvs_ptr += 3;
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for (i = 0; i < burst_len; i++) {
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val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
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| (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
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wl1271_debug(DEBUG_BOOT,
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"nvs burst write 0x%x: 0x%x",
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dest_addr, val);
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wl1271_reg_write32(wl, dest_addr, val);
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nvs_ptr += 4;
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dest_addr += 4;
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}
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}
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/*
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* We've reached the first zero length, the first NVS table
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* is 7 bytes further.
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*/
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nvs_ptr += 7;
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nvs_len -= nvs_ptr - nvs;
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nvs_len = ALIGN(nvs_len, 4);
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/* FIXME: The driver sets the partition here, but this is not needed,
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since it sets to the same one as currently in use */
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/* Now we must set the partition correctly */
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wl1271_set_partition(wl,
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part_table[PART_WORK].mem.start,
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part_table[PART_WORK].mem.size,
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part_table[PART_WORK].reg.start,
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part_table[PART_WORK].reg.size);
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/* Copy the NVS tables to a new block to ensure alignment */
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nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
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/* And finally we upload the NVS tables */
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/* FIXME: In wl1271, we upload everything at once.
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No endianness handling needed here?! The ref driver doesn't do
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anything about it at this point */
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wl1271_spi_mem_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len);
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kfree(nvs_aligned);
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return 0;
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}
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static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
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{
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enable_irq(wl->irq);
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wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
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WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
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wl1271_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
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}
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static int wl1271_boot_soft_reset(struct wl1271 *wl)
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{
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unsigned long timeout;
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u32 boot_data;
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/* perform soft reset */
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wl1271_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
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/* SOFT_RESET is self clearing */
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timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
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while (1) {
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boot_data = wl1271_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
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wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
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if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
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break;
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if (time_after(jiffies, timeout)) {
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/* 1.2 check pWhalBus->uSelfClearTime if the
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* timeout was reached */
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wl1271_error("soft reset timeout");
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return -1;
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}
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udelay(SOFT_RESET_STALL_TIME);
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}
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/* disable Rx/Tx */
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wl1271_reg_write32(wl, ENABLE, 0x0);
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/* disable auto calibration on start*/
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wl1271_reg_write32(wl, SPARE_A2, 0xffff);
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return 0;
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}
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static int wl1271_boot_run_firmware(struct wl1271 *wl)
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{
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int loop, ret;
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u32 chip_id, interrupt;
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wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
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chip_id = wl1271_reg_read32(wl, CHIP_ID_B);
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wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
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if (chip_id != wl->chip.id) {
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wl1271_error("chip id doesn't match after firmware boot");
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return -EIO;
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}
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/* wait for init to complete */
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loop = 0;
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while (loop++ < INIT_LOOP) {
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udelay(INIT_LOOP_DELAY);
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interrupt = wl1271_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
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if (interrupt == 0xffffffff) {
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wl1271_error("error reading hardware complete "
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"init indication");
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return -EIO;
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}
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/* check that ACX_INTR_INIT_COMPLETE is enabled */
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else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
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wl1271_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
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WL1271_ACX_INTR_INIT_COMPLETE);
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break;
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}
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}
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if (loop >= INIT_LOOP) {
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wl1271_error("timeout waiting for the hardware to "
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"complete initialization");
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return -EIO;
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}
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/* get hardware config command mail box */
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wl->cmd_box_addr = wl1271_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
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/* get hardware config event mail box */
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wl->event_box_addr = wl1271_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
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/* set the working partition to its "running" mode offset */
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wl1271_set_partition(wl,
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part_table[PART_WORK].mem.start,
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part_table[PART_WORK].mem.size,
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part_table[PART_WORK].reg.start,
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part_table[PART_WORK].reg.size);
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wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
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wl->cmd_box_addr, wl->event_box_addr);
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wl1271_boot_fw_version(wl);
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/*
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* in case of full asynchronous mode the firmware event must be
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* ready to receive event from the command mailbox
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*/
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/* enable gpio interrupts */
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wl1271_boot_enable_interrupts(wl);
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/* unmask all mbox events */
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wl->event_mask = 0xffffffff;
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ret = wl1271_event_unmask(wl);
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if (ret < 0) {
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wl1271_error("EVENT mask setting failed");
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return ret;
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}
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wl1271_event_mbox_config(wl);
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/* firmware startup completed */
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return 0;
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}
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static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
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{
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u32 polarity, status, i;
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wl1271_reg_write32(wl, OCP_POR_CTR, OCP_REG_POLARITY);
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wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_READ);
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/* Wait until the command is complete (ie. bit 18 is set) */
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for (i = 0; i < OCP_CMD_LOOP; i++) {
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polarity = wl1271_reg_read32(wl, OCP_DATA_READ);
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if (polarity & OCP_READY_MASK)
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break;
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}
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if (i == OCP_CMD_LOOP) {
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wl1271_error("OCP command timeout!");
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return -EIO;
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}
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status = polarity & OCP_STATUS_MASK;
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if (status != OCP_STATUS_OK) {
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wl1271_error("OCP command failed (%d)", status);
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return -EIO;
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}
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/* We use HIGH polarity, so unset the LOW bit */
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polarity &= ~POLARITY_LOW;
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wl1271_reg_write32(wl, OCP_POR_CTR, OCP_REG_POLARITY);
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wl1271_reg_write32(wl, OCP_DATA_WRITE, polarity);
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wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_WRITE);
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return 0;
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}
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int wl1271_boot(struct wl1271 *wl)
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{
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int ret = 0;
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u32 tmp, clk, pause;
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if (REF_CLOCK == 0 || REF_CLOCK == 2)
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/* ref clk: 19.2/38.4 */
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clk = 0x3;
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else if (REF_CLOCK == 1 || REF_CLOCK == 3)
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/* ref clk: 26/52 */
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clk = 0x5;
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wl1271_reg_write32(wl, PLL_PARAMETERS, clk);
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pause = wl1271_reg_read32(wl, PLL_PARAMETERS);
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wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
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pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
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* WU_COUNTER_PAUSE_VAL instead of
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* 0x3ff (magic number ). How does
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* this work?! */
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pause |= WU_COUNTER_PAUSE_VAL;
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wl1271_reg_write32(wl, WU_COUNTER_PAUSE, pause);
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/* Continue the ELP wake up sequence */
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wl1271_reg_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
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udelay(500);
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wl1271_set_partition(wl,
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part_table[PART_DRPW].mem.start,
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part_table[PART_DRPW].mem.size,
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part_table[PART_DRPW].reg.start,
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part_table[PART_DRPW].reg.size);
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/* Read-modify-write DRPW_SCRATCH_START register (see next state)
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to be used by DRPw FW. The RTRIM value will be added by the FW
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before taking DRPw out of reset */
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wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
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clk = wl1271_reg_read32(wl, DRPW_SCRATCH_START);
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wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
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/* 2 */
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clk |= (REF_CLOCK << 1) << 4;
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wl1271_reg_write32(wl, DRPW_SCRATCH_START, clk);
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wl1271_set_partition(wl,
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part_table[PART_WORK].mem.start,
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part_table[PART_WORK].mem.size,
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part_table[PART_WORK].reg.start,
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part_table[PART_WORK].reg.size);
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/* Disable interrupts */
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wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
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ret = wl1271_boot_soft_reset(wl);
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if (ret < 0)
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goto out;
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/* 2. start processing NVS file */
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ret = wl1271_boot_upload_nvs(wl);
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if (ret < 0)
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goto out;
|
|
|
|
/* write firmware's last address (ie. it's length) to
|
|
* ACX_EEPROMLESS_IND_REG */
|
|
wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
|
|
|
|
wl1271_reg_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
|
|
|
|
tmp = wl1271_reg_read32(wl, CHIP_ID_B);
|
|
|
|
wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
|
|
|
|
/* 6. read the EEPROM parameters */
|
|
tmp = wl1271_reg_read32(wl, SCR_PAD2);
|
|
|
|
ret = wl1271_boot_write_irq_polarity(wl);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
/* FIXME: Need to check whether this is really what we want */
|
|
wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
|
|
WL1271_ACX_ALL_EVENTS_VECTOR);
|
|
|
|
/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
|
|
* to upload_fw) */
|
|
|
|
ret = wl1271_boot_upload_firmware(wl);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
/* 10.5 start firmware */
|
|
ret = wl1271_boot_run_firmware(wl);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
/* set the wl1271 default filters */
|
|
wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
|
|
wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
|
|
|
|
wl1271_event_mbox_config(wl);
|
|
|
|
out:
|
|
return ret;
|
|
}
|