518 lines
14 KiB
C
518 lines
14 KiB
C
/*******************************************************************************
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This is the driver for the MAC 10/100 on-chip Ethernet controller
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currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
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DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
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this code.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/netdevice.h>
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#include <linux/crc32.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include "common.h"
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#include "mac100.h"
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#undef MAC100_DEBUG
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/*#define MAC100_DEBUG*/
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#ifdef MAC100_DEBUG
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#define DBG(fmt, args...) printk(fmt, ## args)
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#else
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#define DBG(fmt, args...) do { } while (0)
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#endif
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static void mac100_core_init(unsigned long ioaddr)
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{
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u32 value = readl(ioaddr + MAC_CONTROL);
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writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
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#ifdef STMMAC_VLAN_TAG_USED
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writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
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#endif
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return;
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}
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static void mac100_dump_mac_regs(unsigned long ioaddr)
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{
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pr_info("\t----------------------------------------------\n"
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"\t MAC100 CSR (base addr = 0x%8x)\n"
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"\t----------------------------------------------\n",
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(unsigned int)ioaddr);
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pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
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readl(ioaddr + MAC_CONTROL));
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pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
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readl(ioaddr + MAC_ADDR_HIGH));
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pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
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readl(ioaddr + MAC_ADDR_LOW));
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pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
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MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
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pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
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MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
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pr_info("\tflow control (offset 0x%x): 0x%08x\n",
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MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
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pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
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readl(ioaddr + MAC_VLAN1));
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pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
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readl(ioaddr + MAC_VLAN2));
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pr_info("\n\tMAC management counter registers\n");
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pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
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MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
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pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
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MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
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pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
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MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
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pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
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MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
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pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
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MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
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return;
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}
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static int mac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
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u32 dma_rx)
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{
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u32 value = readl(ioaddr + DMA_BUS_MODE);
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/* DMA SW reset */
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value |= DMA_BUS_MODE_SFT_RESET;
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writel(value, ioaddr + DMA_BUS_MODE);
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do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
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/* Enable Application Access by writing to DMA CSR0 */
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writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),
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ioaddr + DMA_BUS_MODE);
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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/* The base address of the RX/TX descriptor lists must be written into
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* DMA CSR3 and CSR4, respectively. */
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writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
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writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
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return 0;
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}
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/* Store and Forward capability is not used at all..
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* The transmit threshold can be programmed by
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* setting the TTC bits in the DMA control register.*/
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static void mac100_dma_operation_mode(unsigned long ioaddr, int txmode,
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int rxmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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if (txmode <= 32)
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csr6 |= DMA_CONTROL_TTC_32;
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else if (txmode <= 64)
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csr6 |= DMA_CONTROL_TTC_64;
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else
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csr6 |= DMA_CONTROL_TTC_128;
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writel(csr6, ioaddr + DMA_CONTROL);
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return;
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}
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static void mac100_dump_dma_regs(unsigned long ioaddr)
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{
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int i;
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DBG(KERN_DEBUG "MAC100 DMA CSR \n");
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for (i = 0; i < 9; i++)
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pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
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(DMA_BUS_MODE + i * 4),
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readl(ioaddr + DMA_BUS_MODE + i * 4));
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DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n",
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DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
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DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",
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DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
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return;
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}
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/* DMA controller has two counters to track the number of
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the receive missed frames. */
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static void mac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
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unsigned long ioaddr)
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{
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struct net_device_stats *stats = (struct net_device_stats *)data;
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u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
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if (unlikely(csr8)) {
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if (csr8 & DMA_MISSED_FRAME_OVE) {
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stats->rx_over_errors += 0x800;
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x->rx_overflow_cntr += 0x800;
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} else {
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unsigned int ove_cntr;
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ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
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stats->rx_over_errors += ove_cntr;
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x->rx_overflow_cntr += ove_cntr;
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}
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if (csr8 & DMA_MISSED_FRAME_OVE_M) {
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stats->rx_missed_errors += 0xffff;
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x->rx_missed_cntr += 0xffff;
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} else {
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unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
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stats->rx_missed_errors += miss_f;
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x->rx_missed_cntr += miss_f;
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}
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}
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return;
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}
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static int mac100_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, unsigned long ioaddr)
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{
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int ret = 0;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.tx.error_summary)) {
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if (unlikely(p->des01.tx.underflow_error)) {
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x->tx_underflow++;
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stats->tx_fifo_errors++;
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}
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if (unlikely(p->des01.tx.no_carrier)) {
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x->tx_carrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(p->des01.tx.loss_carrier)) {
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x->tx_losscarrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely((p->des01.tx.excessive_deferral) ||
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(p->des01.tx.excessive_collisions) ||
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(p->des01.tx.late_collision)))
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stats->collisions += p->des01.tx.collision_count;
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ret = -1;
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}
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if (unlikely(p->des01.tx.heartbeat_fail)) {
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x->tx_heartbeat++;
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stats->tx_heartbeat_errors++;
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ret = -1;
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}
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if (unlikely(p->des01.tx.deferred))
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x->tx_deferred++;
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return ret;
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}
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static int mac100_get_tx_len(struct dma_desc *p)
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{
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return p->des01.tx.buffer1_size;
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}
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/* This function verifies if each incoming frame has some errors
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* and, if required, updates the multicast statistics.
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* In case of success, it returns csum_none becasue the device
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* is not able to compute the csum in HW. */
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static int mac100_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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int ret = csum_none;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.rx.last_descriptor == 0)) {
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pr_warning("mac100 Error: Oversized Ethernet "
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"frame spanned multiple buffers\n");
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stats->rx_length_errors++;
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return discard_frame;
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}
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if (unlikely(p->des01.rx.error_summary)) {
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if (unlikely(p->des01.rx.descriptor_error))
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x->rx_desc++;
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if (unlikely(p->des01.rx.partial_frame_error))
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x->rx_partial++;
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if (unlikely(p->des01.rx.run_frame))
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x->rx_runt++;
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if (unlikely(p->des01.rx.frame_too_long))
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x->rx_toolong++;
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if (unlikely(p->des01.rx.collision)) {
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x->rx_collision++;
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stats->collisions++;
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}
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if (unlikely(p->des01.rx.crc_error)) {
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x->rx_crc++;
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stats->rx_crc_errors++;
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}
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ret = discard_frame;
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}
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if (unlikely(p->des01.rx.dribbling))
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ret = discard_frame;
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if (unlikely(p->des01.rx.length_error)) {
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x->rx_lenght++;
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ret = discard_frame;
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}
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if (unlikely(p->des01.rx.mii_error)) {
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x->rx_mii++;
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ret = discard_frame;
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}
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if (p->des01.rx.multicast_frame) {
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x->rx_multicast++;
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stats->multicast++;
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}
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return ret;
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}
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static void mac100_irq_status(unsigned long ioaddr)
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{
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return;
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}
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static void mac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
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}
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static void mac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
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}
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static void mac100_set_filter(struct net_device *dev)
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{
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unsigned long ioaddr = dev->base_addr;
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u32 value = readl(ioaddr + MAC_CONTROL);
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if (dev->flags & IFF_PROMISC) {
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value |= MAC_CONTROL_PR;
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
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MAC_CONTROL_HP);
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} else if ((dev->mc_count > HASH_TABLE_SIZE)
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|| (dev->flags & IFF_ALLMULTI)) {
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value |= MAC_CONTROL_PM;
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value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
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writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
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writel(0xffffffff, ioaddr + MAC_HASH_LOW);
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} else if (dev->mc_count == 0) { /* no multicast */
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
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MAC_CONTROL_HO | MAC_CONTROL_HP);
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} else {
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int i;
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u32 mc_filter[2];
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struct dev_mc_list *mclist;
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/* Perfect filter mode for physical address and Hash
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filter for multicast */
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value |= MAC_CONTROL_HP;
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF
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| MAC_CONTROL_HO);
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memset(mc_filter, 0, sizeof(mc_filter));
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for (i = 0, mclist = dev->mc_list;
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mclist && i < dev->mc_count; i++, mclist = mclist->next) {
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/* The upper 6 bits of the calculated CRC are used to
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* index the contens of the hash table */
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int bit_nr =
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ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
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/* The most significant bit determines the register to
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* use (H/L) while the other 5 bits determine the bit
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* within the register. */
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mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
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}
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writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
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writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
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}
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writel(value, ioaddr + MAC_CONTROL);
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DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
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"HI 0x%08x, LO 0x%08x\n",
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__func__, readl(ioaddr + MAC_CONTROL),
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readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
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return;
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}
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static void mac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
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unsigned int fc, unsigned int pause_time)
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{
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unsigned int flow = MAC_FLOW_CTRL_ENABLE;
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if (duplex)
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flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
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writel(flow, ioaddr + MAC_FLOW_CTRL);
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return;
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}
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/* No PMT module supported in our SoC for the Ethernet Controller. */
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static void mac100_pmt(unsigned long ioaddr, unsigned long mode)
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{
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return;
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}
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static void mac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
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int disable_rx_ic)
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{
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int i;
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for (i = 0; i < ring_size; i++) {
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p->des01.rx.own = 1;
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p->des01.rx.buffer1_size = BUF_SIZE_2KiB - 1;
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if (i == ring_size - 1)
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p->des01.rx.end_ring = 1;
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if (disable_rx_ic)
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p->des01.rx.disable_ic = 1;
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p++;
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}
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return;
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}
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static void mac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
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{
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int i;
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for (i = 0; i < ring_size; i++) {
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p->des01.tx.own = 0;
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if (i == ring_size - 1)
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p->des01.tx.end_ring = 1;
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p++;
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}
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return;
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}
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static int mac100_get_tx_owner(struct dma_desc *p)
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{
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return p->des01.tx.own;
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}
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static int mac100_get_rx_owner(struct dma_desc *p)
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{
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return p->des01.rx.own;
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}
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static void mac100_set_tx_owner(struct dma_desc *p)
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{
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p->des01.tx.own = 1;
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}
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static void mac100_set_rx_owner(struct dma_desc *p)
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{
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p->des01.rx.own = 1;
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}
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static int mac100_get_tx_ls(struct dma_desc *p)
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{
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return p->des01.tx.last_segment;
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}
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static void mac100_release_tx_desc(struct dma_desc *p)
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{
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int ter = p->des01.tx.end_ring;
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/* clean field used within the xmit */
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p->des01.tx.first_segment = 0;
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p->des01.tx.last_segment = 0;
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p->des01.tx.buffer1_size = 0;
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/* clean status reported */
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p->des01.tx.error_summary = 0;
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p->des01.tx.underflow_error = 0;
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p->des01.tx.no_carrier = 0;
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p->des01.tx.loss_carrier = 0;
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p->des01.tx.excessive_deferral = 0;
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p->des01.tx.excessive_collisions = 0;
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p->des01.tx.late_collision = 0;
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p->des01.tx.heartbeat_fail = 0;
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p->des01.tx.deferred = 0;
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/* set termination field */
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p->des01.tx.end_ring = ter;
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return;
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}
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static void mac100_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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int csum_flag)
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{
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p->des01.tx.first_segment = is_fs;
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p->des01.tx.buffer1_size = len;
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}
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static void mac100_clear_tx_ic(struct dma_desc *p)
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{
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p->des01.tx.interrupt = 0;
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}
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static void mac100_close_tx_desc(struct dma_desc *p)
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{
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p->des01.tx.last_segment = 1;
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p->des01.tx.interrupt = 1;
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}
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static int mac100_get_rx_frame_len(struct dma_desc *p)
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{
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return p->des01.rx.frame_length;
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}
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struct stmmac_ops mac100_driver = {
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.core_init = mac100_core_init,
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.dump_mac_regs = mac100_dump_mac_regs,
|
|
.dma_init = mac100_dma_init,
|
|
.dump_dma_regs = mac100_dump_dma_regs,
|
|
.dma_mode = mac100_dma_operation_mode,
|
|
.dma_diagnostic_fr = mac100_dma_diagnostic_fr,
|
|
.tx_status = mac100_get_tx_frame_status,
|
|
.rx_status = mac100_get_rx_frame_status,
|
|
.get_tx_len = mac100_get_tx_len,
|
|
.set_filter = mac100_set_filter,
|
|
.flow_ctrl = mac100_flow_ctrl,
|
|
.pmt = mac100_pmt,
|
|
.init_rx_desc = mac100_init_rx_desc,
|
|
.init_tx_desc = mac100_init_tx_desc,
|
|
.get_tx_owner = mac100_get_tx_owner,
|
|
.get_rx_owner = mac100_get_rx_owner,
|
|
.release_tx_desc = mac100_release_tx_desc,
|
|
.prepare_tx_desc = mac100_prepare_tx_desc,
|
|
.clear_tx_ic = mac100_clear_tx_ic,
|
|
.close_tx_desc = mac100_close_tx_desc,
|
|
.get_tx_ls = mac100_get_tx_ls,
|
|
.set_tx_owner = mac100_set_tx_owner,
|
|
.set_rx_owner = mac100_set_rx_owner,
|
|
.get_rx_frame_len = mac100_get_rx_frame_len,
|
|
.host_irq_status = mac100_irq_status,
|
|
.set_umac_addr = mac100_set_umac_addr,
|
|
.get_umac_addr = mac100_get_umac_addr,
|
|
};
|
|
|
|
struct mac_device_info *mac100_setup(unsigned long ioaddr)
|
|
{
|
|
struct mac_device_info *mac;
|
|
|
|
mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
|
|
|
|
pr_info("\tMAC 10/100\n");
|
|
|
|
mac->ops = &mac100_driver;
|
|
mac->hw.pmt = PMT_NOT_SUPPORTED;
|
|
mac->hw.link.port = MAC_CONTROL_PS;
|
|
mac->hw.link.duplex = MAC_CONTROL_F;
|
|
mac->hw.link.speed = 0;
|
|
mac->hw.mii.addr = MAC_MII_ADDR;
|
|
mac->hw.mii.data = MAC_MII_DATA;
|
|
|
|
return mac;
|
|
}
|