819 lines
22 KiB
C
819 lines
22 KiB
C
#ifdef CONFIG_MSM_KGSL
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/* Copyright (c) 2002,2007-2011, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, and the entire permission notice in its entirety,
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* including the disclaimer of warranties.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* ALTERNATIVELY, this product may be distributed under the terms of
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* the GNU General Public License, version 2, in which case the provisions
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* of the GPL version 2 are required INSTEAD OF the BSD license.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ALL OF
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* WHICH ARE HEREBY DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF NOT ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#ifndef _MSM_KGSL_H
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#define _MSM_KGSL_H
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#define KGSL_VERSION_MAJOR 3
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#define KGSL_VERSION_MINOR 7
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/*context flags */
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#define KGSL_CONTEXT_SAVE_GMEM 1
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#define KGSL_CONTEXT_NO_GMEM_ALLOC 2
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#define KGSL_CONTEXT_SUBMIT_IB_LIST 4
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#define KGSL_CONTEXT_CTX_SWITCH 8
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/* Memory allocayion flags */
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#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000
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/* generic flag values */
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#define KGSL_FLAGS_NORMALMODE 0x00000000
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#define KGSL_FLAGS_SAFEMODE 0x00000001
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#define KGSL_FLAGS_INITIALIZED0 0x00000002
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#define KGSL_FLAGS_INITIALIZED 0x00000004
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#define KGSL_FLAGS_STARTED 0x00000008
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#define KGSL_FLAGS_ACTIVE 0x00000010
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#define KGSL_FLAGS_RESERVED0 0x00000020
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#define KGSL_FLAGS_RESERVED1 0x00000040
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#define KGSL_FLAGS_RESERVED2 0x00000080
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#define KGSL_FLAGS_SOFT_RESET 0x00000100
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#define KGSL_MAX_PWRLEVELS 5
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/* device id */
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enum kgsl_deviceid {
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KGSL_DEVICE_3D0 = 0x00000000,
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KGSL_DEVICE_2D0 = 0x00000001,
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KGSL_DEVICE_2D1 = 0x00000002,
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KGSL_DEVICE_MAX = 0x00000003
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};
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enum kgsl_user_mem_type {
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KGSL_USER_MEM_TYPE_PMEM = 0x00000000,
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KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001,
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KGSL_USER_MEM_TYPE_ADDR = 0x00000002
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};
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struct kgsl_devinfo {
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unsigned int device_id;
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/* chip revision id
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* coreid:8 majorrev:8 minorrev:8 patch:8
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*/
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unsigned int chip_id;
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unsigned int mmu_enabled;
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unsigned int gmem_gpubaseaddr;
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/*
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* This field contains the adreno revision
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* number 200, 205, 220, etc...
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*/
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unsigned int gpu_id;
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unsigned int gmem_sizebytes;
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};
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/* this structure defines the region of memory that can be mmap()ed from this
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driver. The timestamp fields are volatile because they are written by the
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GPU
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*/
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struct kgsl_devmemstore {
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volatile unsigned int soptimestamp;
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unsigned int sbz;
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volatile unsigned int eoptimestamp;
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unsigned int sbz2;
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volatile unsigned int ts_cmp_enable;
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unsigned int sbz3;
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volatile unsigned int ref_wait_ts;
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unsigned int sbz4;
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unsigned int current_context;
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unsigned int sbz5;
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};
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#define KGSL_DEVICE_MEMSTORE_OFFSET(field) \
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offsetof(struct kgsl_devmemstore, field)
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/* timestamp id*/
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enum kgsl_timestamp_type {
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KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */
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KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/
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KGSL_TIMESTAMP_MAX = 0x00000002,
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};
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/* property types - used with kgsl_device_getproperty */
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enum kgsl_property_type {
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KGSL_PROP_DEVICE_INFO = 0x00000001,
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KGSL_PROP_DEVICE_SHADOW = 0x00000002,
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KGSL_PROP_DEVICE_POWER = 0x00000003,
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KGSL_PROP_SHMEM = 0x00000004,
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KGSL_PROP_SHMEM_APERTURES = 0x00000005,
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KGSL_PROP_MMU_ENABLE = 0x00000006,
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KGSL_PROP_INTERRUPT_WAITS = 0x00000007,
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KGSL_PROP_VERSION = 0x00000008,
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};
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struct kgsl_shadowprop {
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unsigned int gpuaddr;
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unsigned int size;
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unsigned int flags; /* contains KGSL_FLAGS_ values */
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};
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struct kgsl_pwrlevel {
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unsigned int gpu_freq;
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unsigned int bus_freq;
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};
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struct kgsl_version {
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unsigned int drv_major;
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unsigned int drv_minor;
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unsigned int dev_major;
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unsigned int dev_minor;
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};
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#ifdef __KERNEL__
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#define KGSL_3D0_REG_MEMORY "kgsl_3d0_reg_memory"
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#define KGSL_3D0_IRQ "kgsl_3d0_irq"
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#define KGSL_2D0_REG_MEMORY "kgsl_2d0_reg_memory"
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#define KGSL_2D0_IRQ "kgsl_2d0_irq"
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#define KGSL_2D1_REG_MEMORY "kgsl_2d1_reg_memory"
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#define KGSL_2D1_IRQ "kgsl_2d1_irq"
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struct kgsl_grp_clk_name {
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const char *clk;
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const char *pclk;
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};
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struct kgsl_device_pwr_data {
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struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS];
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int init_level;
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int num_levels;
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int (*set_grp_async)(void);
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unsigned int idle_timeout;
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unsigned int nap_allowed;
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unsigned int idle_pass;
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};
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struct kgsl_clk_data {
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struct kgsl_grp_clk_name name;
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struct msm_bus_scale_pdata *bus_scale_table;
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};
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struct kgsl_device_platform_data {
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struct kgsl_device_pwr_data pwr_data;
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struct kgsl_clk_data clk;
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/* imem_clk_name is for 3d only, not used in 2d devices */
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struct kgsl_grp_clk_name imem_clk_name;
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};
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#endif
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/* structure holds list of ibs */
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struct kgsl_ibdesc {
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unsigned int gpuaddr;
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void *hostptr;
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unsigned int sizedwords;
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unsigned int ctrl;
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};
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/* ioctls */
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#define KGSL_IOC_TYPE 0x09
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/* get misc info about the GPU
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type should be a value from enum kgsl_property_type
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value points to a structure that varies based on type
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sizebytes is sizeof() that structure
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for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo
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this structure contaings hardware versioning info.
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for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop
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this is used to find mmap() offset and sizes for mapping
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struct kgsl_memstore into userspace.
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*/
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struct kgsl_device_getproperty {
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unsigned int type;
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void *value;
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unsigned int sizebytes;
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};
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#define IOCTL_KGSL_DEVICE_GETPROPERTY \
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_IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty)
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/* read a GPU register.
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offsetwords it the 32 bit word offset from the beginning of the
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GPU register space.
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*/
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struct kgsl_device_regread {
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unsigned int offsetwords;
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unsigned int value; /* output param */
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};
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#define IOCTL_KGSL_DEVICE_REGREAD \
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_IOWR(KGSL_IOC_TYPE, 0x3, struct kgsl_device_regread)
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/* block until the GPU has executed past a given timestamp
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* timeout is in milliseconds.
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*/
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struct kgsl_device_waittimestamp {
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unsigned int timestamp;
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unsigned int timeout;
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};
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#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \
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_IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp)
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/* issue indirect commands to the GPU.
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* drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE
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* ibaddr and sizedwords must specify a subset of a buffer created
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* with IOCTL_KGSL_SHAREDMEM_FROM_PMEM
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* flags may be a mask of KGSL_CONTEXT_ values
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* timestamp is a returned counter value which can be passed to
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* other ioctls to determine when the commands have been executed by
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* the GPU.
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*/
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struct kgsl_ringbuffer_issueibcmds {
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unsigned int drawctxt_id;
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unsigned int ibdesc_addr;
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unsigned int numibs;
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unsigned int timestamp; /*output param */
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unsigned int flags;
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};
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#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \
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_IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds)
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/* read the most recently executed timestamp value
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* type should be a value from enum kgsl_timestamp_type
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*/
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struct kgsl_cmdstream_readtimestamp {
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unsigned int type;
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unsigned int timestamp; /*output param */
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};
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#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD \
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_IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
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#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \
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_IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
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/* free memory when the GPU reaches a given timestamp.
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* gpuaddr specify a memory region created by a
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* IOCTL_KGSL_SHAREDMEM_FROM_PMEM call
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* type should be a value from enum kgsl_timestamp_type
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*/
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struct kgsl_cmdstream_freememontimestamp {
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unsigned int gpuaddr;
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unsigned int type;
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unsigned int timestamp;
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};
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#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \
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_IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
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/* Previous versions of this header had incorrectly defined
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IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead
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of a write only ioctl. To ensure binary compatability, the following
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#define will be used to intercept the incorrect ioctl
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*/
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#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \
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_IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
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/* create a draw context, which is used to preserve GPU state.
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* The flags field may contain a mask KGSL_CONTEXT_* values
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*/
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struct kgsl_drawctxt_create {
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unsigned int flags;
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unsigned int drawctxt_id; /*output param */
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};
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#define IOCTL_KGSL_DRAWCTXT_CREATE \
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_IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create)
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/* destroy a draw context */
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struct kgsl_drawctxt_destroy {
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unsigned int drawctxt_id;
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};
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#define IOCTL_KGSL_DRAWCTXT_DESTROY \
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_IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy)
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/* add a block of pmem, fb, ashmem or user allocated address
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* into the GPU address space */
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struct kgsl_map_user_mem {
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int fd;
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unsigned int gpuaddr; /*output param */
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unsigned int len;
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unsigned int offset;
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unsigned int hostptr; /*input param */
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enum kgsl_user_mem_type memtype;
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unsigned int reserved; /* May be required to add
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params for another mem type */
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};
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#define IOCTL_KGSL_MAP_USER_MEM \
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_IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem)
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/* add a block of pmem or fb into the GPU address space */
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struct kgsl_sharedmem_from_pmem {
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int pmem_fd;
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unsigned int gpuaddr; /*output param */
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unsigned int len;
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unsigned int offset;
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};
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#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \
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_IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem)
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/* remove memory from the GPU's address space */
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struct kgsl_sharedmem_free {
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unsigned int gpuaddr;
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};
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#define IOCTL_KGSL_SHAREDMEM_FREE \
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_IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free)
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struct kgsl_cff_user_event {
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unsigned char cff_opcode;
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unsigned int op1;
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unsigned int op2;
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unsigned int op3;
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unsigned int op4;
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unsigned int op5;
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unsigned int __pad[2];
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};
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#define IOCTL_KGSL_CFF_USER_EVENT \
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_IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event)
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struct kgsl_gmem_desc {
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unsigned int x;
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unsigned int y;
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unsigned int width;
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unsigned int height;
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unsigned int pitch;
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};
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struct kgsl_buffer_desc {
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void *hostptr;
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unsigned int gpuaddr;
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int size;
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unsigned int format;
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unsigned int pitch;
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unsigned int enabled;
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};
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struct kgsl_bind_gmem_shadow {
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unsigned int drawctxt_id;
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struct kgsl_gmem_desc gmem_desc;
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unsigned int shadow_x;
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unsigned int shadow_y;
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struct kgsl_buffer_desc shadow_buffer;
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unsigned int buffer_id;
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};
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#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \
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_IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow)
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/* add a block of memory into the GPU address space */
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struct kgsl_sharedmem_from_vmalloc {
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unsigned int gpuaddr; /*output param */
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unsigned int hostptr;
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unsigned int flags;
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};
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#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \
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_IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc)
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#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \
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_IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free)
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struct kgsl_drawctxt_set_bin_base_offset {
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unsigned int drawctxt_id;
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unsigned int offset;
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};
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#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \
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_IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset)
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enum kgsl_cmdwindow_type {
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KGSL_CMDWINDOW_MIN = 0x00000000,
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KGSL_CMDWINDOW_2D = 0x00000000,
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KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */
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KGSL_CMDWINDOW_MMU = 0x00000002,
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KGSL_CMDWINDOW_ARBITER = 0x000000FF,
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KGSL_CMDWINDOW_MAX = 0x000000FF,
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};
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/* write to the command window */
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struct kgsl_cmdwindow_write {
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enum kgsl_cmdwindow_type target;
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unsigned int addr;
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unsigned int data;
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};
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#define IOCTL_KGSL_CMDWINDOW_WRITE \
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_IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write)
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struct kgsl_gpumem_alloc {
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unsigned long gpuaddr;
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size_t size;
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unsigned int flags;
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};
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#define IOCTL_KGSL_GPUMEM_ALLOC \
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_IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc)
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struct kgsl_cff_syncmem {
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unsigned int gpuaddr;
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unsigned int len;
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unsigned int __pad[2]; /* For future binary compatibility */
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};
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#define IOCTL_KGSL_CFF_SYNCMEM \
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_IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem)
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#ifdef __KERNEL__
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#ifdef CONFIG_MSM_KGSL_DRM
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int kgsl_gem_obj_addr(int drm_fd, int handle, unsigned long *start,
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unsigned long *len);
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#else
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#define kgsl_gem_obj_addr(...) 0
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#endif
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#endif
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#endif /* _MSM_KGSL_H */
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#else
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/*
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* (C) Copyright Advanced Micro Devices, Inc. 2002, 2007
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* Copyright (c) 2008-2009 QUALCOMM USA, INC.
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*
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* All source code in this file is licensed under the following license
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can find it at http://www.fsf.org
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*/
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#ifndef _MSM_KGSL_H
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#define _MSM_KGSL_H
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/*context flags */
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#define KGSL_CONTEXT_SAVE_GMEM 1
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#define KGSL_CONTEXT_NO_GMEM_ALLOC 2
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/* generic flag values */
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#define KGSL_FLAGS_NORMALMODE 0x00000000
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#define KGSL_FLAGS_SAFEMODE 0x00000001
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#define KGSL_FLAGS_INITIALIZED0 0x00000002
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#define KGSL_FLAGS_INITIALIZED 0x00000004
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#define KGSL_FLAGS_STARTED 0x00000008
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|
#define KGSL_FLAGS_ACTIVE 0x00000010
|
|
#define KGSL_FLAGS_RESERVED0 0x00000020
|
|
#define KGSL_FLAGS_RESERVED1 0x00000040
|
|
#define KGSL_FLAGS_RESERVED2 0x00000080
|
|
|
|
/* device id */
|
|
enum kgsl_deviceid {
|
|
KGSL_DEVICE_ANY = 0x00000000,
|
|
KGSL_DEVICE_YAMATO = 0x00000001,
|
|
KGSL_DEVICE_G12 = 0x00000002,
|
|
KGSL_DEVICE_MAX = 0x00000002
|
|
};
|
|
|
|
struct kgsl_devinfo {
|
|
|
|
unsigned int device_id;
|
|
/* chip revision id
|
|
* coreid:8 majorrev:8 minorrev:8 patch:8
|
|
*/
|
|
unsigned int chip_id;
|
|
unsigned int mmu_enabled;
|
|
unsigned int gmem_gpubaseaddr;
|
|
/* if gmem_hostbaseaddr is NULL, we would know its not mapped into
|
|
* mmio space */
|
|
unsigned int gmem_hostbaseaddr;
|
|
unsigned int gmem_sizebytes;
|
|
};
|
|
|
|
/* this structure defines the region of memory that can be mmap()ed from this
|
|
driver. The timestamp fields are volatile because they are written by the
|
|
GPU
|
|
*/
|
|
struct kgsl_devmemstore {
|
|
volatile unsigned int soptimestamp;
|
|
unsigned int sbz;
|
|
volatile unsigned int eoptimestamp;
|
|
unsigned int sbz2;
|
|
volatile unsigned int ts_cmp_enable;
|
|
unsigned int sbz3;
|
|
volatile unsigned int ref_wait_ts;
|
|
unsigned int sbz4;
|
|
};
|
|
|
|
#define KGSL_DEVICE_MEMSTORE_OFFSET(field) \
|
|
offsetof(struct kgsl_devmemstore, field)
|
|
|
|
|
|
/* timestamp id*/
|
|
enum kgsl_timestamp_type {
|
|
KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */
|
|
KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/
|
|
KGSL_TIMESTAMP_MAX = 0x00000002,
|
|
};
|
|
|
|
/* property types - used with kgsl_device_getproperty */
|
|
enum kgsl_property_type {
|
|
KGSL_PROP_DEVICE_INFO = 0x00000001,
|
|
KGSL_PROP_DEVICE_SHADOW = 0x00000002,
|
|
KGSL_PROP_DEVICE_POWER = 0x00000003,
|
|
KGSL_PROP_SHMEM = 0x00000004,
|
|
KGSL_PROP_SHMEM_APERTURES = 0x00000005,
|
|
KGSL_PROP_MMU_ENABLE = 0x00000006,
|
|
KGSL_PROP_INTERRUPT_WAITS = 0x00000007,
|
|
};
|
|
|
|
struct kgsl_shadowprop {
|
|
unsigned int gpuaddr;
|
|
unsigned int size;
|
|
unsigned int flags; /* contains KGSL_FLAGS_ values */
|
|
};
|
|
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
struct kgsl_platform_data {
|
|
unsigned int high_axi_2d;
|
|
unsigned int high_axi_3d;
|
|
unsigned int max_grp2d_freq;
|
|
unsigned int min_grp2d_freq;
|
|
int (*set_grp2d_async)(void);
|
|
unsigned int max_grp3d_freq;
|
|
unsigned int min_grp3d_freq;
|
|
int (*set_grp3d_async)(void);
|
|
};
|
|
#endif
|
|
/* ioctls */
|
|
#define KGSL_IOC_TYPE 0x09
|
|
|
|
/* get misc info about the GPU
|
|
type should be a value from enum kgsl_property_type
|
|
value points to a structure that varies based on type
|
|
sizebytes is sizeof() that structure
|
|
for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo
|
|
this structure contaings hardware versioning info.
|
|
for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop
|
|
this is used to find mmap() offset and sizes for mapping
|
|
struct kgsl_memstore into userspace.
|
|
*/
|
|
struct kgsl_device_getproperty {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int type;
|
|
void *value;
|
|
unsigned int sizebytes;
|
|
};
|
|
|
|
#define IOCTL_KGSL_DEVICE_GETPROPERTY \
|
|
_IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty)
|
|
|
|
|
|
/* read a GPU register.
|
|
offsetwords it the 32 bit word offset from the beginning of the
|
|
GPU register space.
|
|
*/
|
|
struct kgsl_device_regread {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int offsetwords;
|
|
unsigned int value; /* output param */
|
|
};
|
|
|
|
#define IOCTL_KGSL_DEVICE_REGREAD \
|
|
_IOWR(KGSL_IOC_TYPE, 0x3, struct kgsl_device_regread)
|
|
|
|
|
|
/* block until the GPU has executed past a given timestamp
|
|
* timeout is in milliseconds.
|
|
*/
|
|
struct kgsl_device_waittimestamp {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int timestamp;
|
|
unsigned int timeout;
|
|
};
|
|
|
|
#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \
|
|
_IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp)
|
|
|
|
|
|
/* issue indirect commands to the GPU.
|
|
* drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE
|
|
* ibaddr and sizedwords must specify a subset of a buffer created
|
|
* with IOCTL_KGSL_SHAREDMEM_FROM_PMEM
|
|
* flags may be a mask of KGSL_CONTEXT_ values
|
|
* timestamp is a returned counter value which can be passed to
|
|
* other ioctls to determine when the commands have been executed by
|
|
* the GPU.
|
|
*/
|
|
struct kgsl_ringbuffer_issueibcmds {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int drawctxt_id;
|
|
unsigned int ibaddr;
|
|
unsigned int sizedwords;
|
|
unsigned int timestamp; /*output param */
|
|
unsigned int flags;
|
|
};
|
|
|
|
#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \
|
|
_IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds)
|
|
|
|
/* read the most recently executed timestamp value
|
|
* type should be a value from enum kgsl_timestamp_type
|
|
*/
|
|
struct kgsl_cmdstream_readtimestamp {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int type;
|
|
unsigned int timestamp; /*output param */
|
|
};
|
|
|
|
#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \
|
|
_IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
|
|
|
|
/* free memory when the GPU reaches a given timestamp.
|
|
* gpuaddr specify a memory region created by a
|
|
* IOCTL_KGSL_SHAREDMEM_FROM_PMEM call
|
|
* type should be a value from enum kgsl_timestamp_type
|
|
*/
|
|
struct kgsl_cmdstream_freememontimestamp {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int gpuaddr;
|
|
unsigned int type;
|
|
unsigned int timestamp;
|
|
};
|
|
|
|
#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \
|
|
_IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
|
|
|
|
/* create a draw context, which is used to preserve GPU state.
|
|
* The flags field may contain a mask KGSL_CONTEXT_* values
|
|
*/
|
|
struct kgsl_drawctxt_create {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int flags;
|
|
unsigned int drawctxt_id; /*output param */
|
|
};
|
|
|
|
#define IOCTL_KGSL_DRAWCTXT_CREATE \
|
|
_IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create)
|
|
|
|
/* destroy a draw context */
|
|
struct kgsl_drawctxt_destroy {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int drawctxt_id;
|
|
};
|
|
|
|
#define IOCTL_KGSL_DRAWCTXT_DESTROY \
|
|
_IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy)
|
|
|
|
/* add a block of pmem or fb into the GPU address space */
|
|
struct kgsl_sharedmem_from_pmem {
|
|
int pmem_fd;
|
|
unsigned int gpuaddr; /*output param */
|
|
unsigned int len;
|
|
unsigned int offset;
|
|
};
|
|
|
|
#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \
|
|
_IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem)
|
|
|
|
/* remove memory from the GPU's address space */
|
|
struct kgsl_sharedmem_free {
|
|
unsigned int gpuaddr;
|
|
};
|
|
|
|
#define IOCTL_KGSL_SHAREDMEM_FREE \
|
|
_IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free)
|
|
|
|
struct kgsl_gmem_desc {
|
|
unsigned int x;
|
|
unsigned int y;
|
|
unsigned int width;
|
|
unsigned int height;
|
|
unsigned int pitch;
|
|
};
|
|
|
|
struct kgsl_buffer_desc {
|
|
void *hostptr;
|
|
unsigned int gpuaddr;
|
|
int size;
|
|
unsigned int format;
|
|
unsigned int pitch;
|
|
unsigned int enabled;
|
|
};
|
|
|
|
struct kgsl_bind_gmem_shadow {
|
|
unsigned int drawctxt_id;
|
|
struct kgsl_gmem_desc gmem_desc;
|
|
unsigned int shadow_x;
|
|
unsigned int shadow_y;
|
|
struct kgsl_buffer_desc shadow_buffer;
|
|
unsigned int buffer_id;
|
|
};
|
|
|
|
#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \
|
|
_IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow)
|
|
|
|
/* add a block of memory into the GPU address space */
|
|
struct kgsl_sharedmem_from_vmalloc {
|
|
unsigned int gpuaddr; /*output param */
|
|
unsigned int hostptr;
|
|
/* If set from user space then will attempt to
|
|
* allocate even if low watermark is crossed */
|
|
int force_no_low_watermark;
|
|
};
|
|
|
|
#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \
|
|
_IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc)
|
|
|
|
#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \
|
|
_IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free)
|
|
|
|
struct kgsl_drawctxt_set_bin_base_offset {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
unsigned int drawctxt_id;
|
|
unsigned int offset;
|
|
};
|
|
|
|
#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \
|
|
_IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset)
|
|
|
|
enum kgsl_cmdwindow_type {
|
|
KGSL_CMDWINDOW_MIN = 0x00000000,
|
|
KGSL_CMDWINDOW_2D = 0x00000000,
|
|
KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */
|
|
KGSL_CMDWINDOW_MMU = 0x00000002,
|
|
KGSL_CMDWINDOW_ARBITER = 0x000000FF,
|
|
KGSL_CMDWINDOW_MAX = 0x000000FF,
|
|
};
|
|
|
|
/* write to the command window */
|
|
struct kgsl_cmdwindow_write {
|
|
#ifdef CONFIG_ARCH_MSM7X30
|
|
unsigned int device_id;
|
|
#endif
|
|
enum kgsl_cmdwindow_type target;
|
|
unsigned int addr;
|
|
unsigned int data;
|
|
};
|
|
|
|
#define IOCTL_KGSL_CMDWINDOW_WRITE \
|
|
_IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write)
|
|
|
|
#endif /* _MSM_KGSL_H */
|
|
#endif
|