519 lines
14 KiB
C
519 lines
14 KiB
C
/*
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* linux/arch/m32r/platforms/m32700ut/setup.c
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*
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* Setup routines for Renesas M32700UT Board
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*
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* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Takeo Takahashi
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of this
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* archive for more details.
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <asm/system.h>
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#include <asm/m32r.h>
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#include <asm/io.h>
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/*
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* M32700 Interrupt Control Unit (Level 1)
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*/
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#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
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icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
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static void disable_m32700ut_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
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outl(data, port);
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}
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static void enable_m32700ut_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
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outl(data, port);
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}
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static void mask_and_ack_m32700ut(unsigned int irq)
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{
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disable_m32700ut_irq(irq);
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}
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static void end_m32700ut_irq(unsigned int irq)
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{
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enable_m32700ut_irq(irq);
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}
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static unsigned int startup_m32700ut_irq(unsigned int irq)
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{
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enable_m32700ut_irq(irq);
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return (0);
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}
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static void shutdown_m32700ut_irq(unsigned int irq)
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{
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unsigned long port;
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port = irq2port(irq);
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outl(M32R_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip m32700ut_irq_type =
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{
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.typename = "M32700UT-IRQ",
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.startup = startup_m32700ut_irq,
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.shutdown = shutdown_m32700ut_irq,
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.enable = enable_m32700ut_irq,
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.disable = disable_m32700ut_irq,
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.ack = mask_and_ack_m32700ut,
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.end = end_m32700ut_irq
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};
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/*
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* Interrupt Control Unit of PLD on M32700UT (Level 2)
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*/
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#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
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#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
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(((x) - 1) * sizeof(unsigned short)))
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typedef struct {
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unsigned short icucr; /* ICU Control Register */
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} pld_icu_data_t;
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static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
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static void disable_m32700ut_pld_irq(unsigned int irq)
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{
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unsigned long port, data;
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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// disable_m32700ut_irq(M32R_IRQ_INT1);
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port = pldirq2port(pldirq);
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data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
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outw(data, port);
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}
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static void enable_m32700ut_pld_irq(unsigned int irq)
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{
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unsigned long port, data;
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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// enable_m32700ut_irq(M32R_IRQ_INT1);
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port = pldirq2port(pldirq);
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data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
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outw(data, port);
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}
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static void mask_and_ack_m32700ut_pld(unsigned int irq)
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{
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disable_m32700ut_pld_irq(irq);
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// mask_and_ack_m32700ut(M32R_IRQ_INT1);
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}
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static void end_m32700ut_pld_irq(unsigned int irq)
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{
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enable_m32700ut_pld_irq(irq);
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end_m32700ut_irq(M32R_IRQ_INT1);
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}
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static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
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{
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enable_m32700ut_pld_irq(irq);
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return (0);
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}
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static void shutdown_m32700ut_pld_irq(unsigned int irq)
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{
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unsigned long port;
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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// shutdown_m32700ut_irq(M32R_IRQ_INT1);
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port = pldirq2port(pldirq);
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outw(PLD_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip m32700ut_pld_irq_type =
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{
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.typename = "M32700UT-PLD-IRQ",
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.startup = startup_m32700ut_pld_irq,
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.shutdown = shutdown_m32700ut_pld_irq,
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.enable = enable_m32700ut_pld_irq,
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.disable = disable_m32700ut_pld_irq,
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.ack = mask_and_ack_m32700ut_pld,
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.end = end_m32700ut_pld_irq
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};
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/*
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* Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
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*/
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#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
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#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
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(((x) - 1) * sizeof(unsigned short)))
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static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
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static void disable_m32700ut_lanpld_irq(unsigned int irq)
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{
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unsigned long port, data;
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unsigned int pldirq;
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pldirq = irq2lanpldirq(irq);
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port = lanpldirq2port(pldirq);
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data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
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outw(data, port);
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}
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static void enable_m32700ut_lanpld_irq(unsigned int irq)
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{
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unsigned long port, data;
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unsigned int pldirq;
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pldirq = irq2lanpldirq(irq);
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port = lanpldirq2port(pldirq);
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data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
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outw(data, port);
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}
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static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
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{
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disable_m32700ut_lanpld_irq(irq);
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}
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static void end_m32700ut_lanpld_irq(unsigned int irq)
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{
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enable_m32700ut_lanpld_irq(irq);
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end_m32700ut_irq(M32R_IRQ_INT0);
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}
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static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
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{
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enable_m32700ut_lanpld_irq(irq);
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return (0);
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}
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static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
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{
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unsigned long port;
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unsigned int pldirq;
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pldirq = irq2lanpldirq(irq);
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port = lanpldirq2port(pldirq);
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outw(PLD_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip m32700ut_lanpld_irq_type =
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{
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.typename = "M32700UT-PLD-LAN-IRQ",
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.startup = startup_m32700ut_lanpld_irq,
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.shutdown = shutdown_m32700ut_lanpld_irq,
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.enable = enable_m32700ut_lanpld_irq,
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.disable = disable_m32700ut_lanpld_irq,
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.ack = mask_and_ack_m32700ut_lanpld,
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.end = end_m32700ut_lanpld_irq
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};
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/*
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* Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
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*/
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#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
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#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
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(((x) - 1) * sizeof(unsigned short)))
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static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
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static void disable_m32700ut_lcdpld_irq(unsigned int irq)
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{
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unsigned long port, data;
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unsigned int pldirq;
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pldirq = irq2lcdpldirq(irq);
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port = lcdpldirq2port(pldirq);
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data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
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outw(data, port);
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}
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static void enable_m32700ut_lcdpld_irq(unsigned int irq)
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{
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unsigned long port, data;
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unsigned int pldirq;
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pldirq = irq2lcdpldirq(irq);
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port = lcdpldirq2port(pldirq);
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data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
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outw(data, port);
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}
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static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
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{
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disable_m32700ut_lcdpld_irq(irq);
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}
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static void end_m32700ut_lcdpld_irq(unsigned int irq)
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{
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enable_m32700ut_lcdpld_irq(irq);
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end_m32700ut_irq(M32R_IRQ_INT2);
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}
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static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
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{
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enable_m32700ut_lcdpld_irq(irq);
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return (0);
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}
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static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
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{
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unsigned long port;
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unsigned int pldirq;
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pldirq = irq2lcdpldirq(irq);
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port = lcdpldirq2port(pldirq);
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outw(PLD_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip m32700ut_lcdpld_irq_type =
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{
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.typename = "M32700UT-PLD-LCD-IRQ",
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.startup = startup_m32700ut_lcdpld_irq,
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.shutdown = shutdown_m32700ut_lcdpld_irq,
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.enable = enable_m32700ut_lcdpld_irq,
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.disable = disable_m32700ut_lcdpld_irq,
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.ack = mask_and_ack_m32700ut_lcdpld,
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.end = end_m32700ut_lcdpld_irq
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};
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void __init init_IRQ(void)
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{
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#if defined(CONFIG_SMC91X)
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/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
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irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
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irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;
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irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
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irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
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lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
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disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
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#endif /* CONFIG_SMC91X */
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/* MFT2 : system timer */
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irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;
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irq_desc[M32R_IRQ_MFT2].action = 0;
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irq_desc[M32R_IRQ_MFT2].depth = 1;
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icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
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disable_m32700ut_irq(M32R_IRQ_MFT2);
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/* SIO0 : receive */
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irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;
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irq_desc[M32R_IRQ_SIO0_R].action = 0;
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irq_desc[M32R_IRQ_SIO0_R].depth = 1;
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icu_data[M32R_IRQ_SIO0_R].icucr = 0;
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disable_m32700ut_irq(M32R_IRQ_SIO0_R);
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/* SIO0 : send */
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irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;
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irq_desc[M32R_IRQ_SIO0_S].action = 0;
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irq_desc[M32R_IRQ_SIO0_S].depth = 1;
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icu_data[M32R_IRQ_SIO0_S].icucr = 0;
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disable_m32700ut_irq(M32R_IRQ_SIO0_S);
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/* SIO1 : receive */
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irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;
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irq_desc[M32R_IRQ_SIO1_R].action = 0;
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irq_desc[M32R_IRQ_SIO1_R].depth = 1;
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icu_data[M32R_IRQ_SIO1_R].icucr = 0;
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disable_m32700ut_irq(M32R_IRQ_SIO1_R);
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/* SIO1 : send */
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irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;
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irq_desc[M32R_IRQ_SIO1_S].action = 0;
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irq_desc[M32R_IRQ_SIO1_S].depth = 1;
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icu_data[M32R_IRQ_SIO1_S].icucr = 0;
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disable_m32700ut_irq(M32R_IRQ_SIO1_S);
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/* DMA1 : */
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irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;
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irq_desc[M32R_IRQ_DMA1].action = 0;
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irq_desc[M32R_IRQ_DMA1].depth = 1;
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icu_data[M32R_IRQ_DMA1].icucr = 0;
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disable_m32700ut_irq(M32R_IRQ_DMA1);
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#ifdef CONFIG_SERIAL_M32R_PLDSIO
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/* INT#1: SIO0 Receive on PLD */
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irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
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irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
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disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
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/* INT#1: SIO0 Send on PLD */
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irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_SIO0_SND].action = 0;
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irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
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disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
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#endif /* CONFIG_SERIAL_M32R_PLDSIO */
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/* INT#1: CFC IREQ on PLD */
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irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_CFIREQ].action = 0;
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irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
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disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
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/* INT#1: CFC Insert on PLD */
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irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
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irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
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disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
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/* INT#1: CFC Eject on PLD */
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irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
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irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
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disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
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/*
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* INT0# is used for LAN, DIO
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* We enable it here.
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*/
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icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
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enable_m32700ut_irq(M32R_IRQ_INT0);
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/*
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* INT1# is used for UART, MMC, CF Controller in FPGA.
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* We enable it here.
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*/
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icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
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enable_m32700ut_irq(M32R_IRQ_INT1);
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#if defined(CONFIG_USB)
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outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
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|
|
irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
|
|
irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;
|
|
irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
|
|
irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
|
|
lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
|
|
disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
|
|
#endif
|
|
/*
|
|
* INT2# is used for BAT, USB, AUDIO
|
|
* We enable it here.
|
|
*/
|
|
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
|
|
enable_m32700ut_irq(M32R_IRQ_INT2);
|
|
|
|
#if defined(CONFIG_VIDEO_M32R_AR)
|
|
/*
|
|
* INT3# is used for AR
|
|
*/
|
|
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
|
|
irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;
|
|
irq_desc[M32R_IRQ_INT3].action = 0;
|
|
irq_desc[M32R_IRQ_INT3].depth = 1;
|
|
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
|
disable_m32700ut_irq(M32R_IRQ_INT3);
|
|
#endif /* CONFIG_VIDEO_M32R_AR */
|
|
}
|
|
|
|
#if defined(CONFIG_SMC91X)
|
|
|
|
#define LAN_IOSTART 0x300
|
|
#define LAN_IOEND 0x320
|
|
static struct resource smc91x_resources[] = {
|
|
[0] = {
|
|
.start = (LAN_IOSTART),
|
|
.end = (LAN_IOEND),
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = M32700UT_LAN_IRQ_LAN,
|
|
.end = M32700UT_LAN_IRQ_LAN,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
};
|
|
|
|
static struct platform_device smc91x_device = {
|
|
.name = "smc91x",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(smc91x_resources),
|
|
.resource = smc91x_resources,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_FB_S1D13XXX)
|
|
|
|
#include <video/s1d13xxxfb.h>
|
|
#include <asm/s1d13806.h>
|
|
|
|
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
|
|
.initregs = s1d13xxxfb_initregs,
|
|
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
|
|
.platform_init_video = NULL,
|
|
#ifdef CONFIG_PM
|
|
.platform_suspend_video = NULL,
|
|
.platform_resume_video = NULL,
|
|
#endif
|
|
};
|
|
|
|
static struct resource s1d13xxxfb_resources[] = {
|
|
[0] = {
|
|
.start = 0x10600000UL,
|
|
.end = 0x1073FFFFUL,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = 0x10400000UL,
|
|
.end = 0x104001FFUL,
|
|
.flags = IORESOURCE_MEM,
|
|
}
|
|
};
|
|
|
|
static struct platform_device s1d13xxxfb_device = {
|
|
.name = S1D_DEVICENAME,
|
|
.id = 0,
|
|
.dev = {
|
|
.platform_data = &s1d13xxxfb_data,
|
|
},
|
|
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
|
|
.resource = s1d13xxxfb_resources,
|
|
};
|
|
#endif
|
|
|
|
static int __init platform_init(void)
|
|
{
|
|
#if defined(CONFIG_SMC91X)
|
|
platform_device_register(&smc91x_device);
|
|
#endif
|
|
#if defined(CONFIG_FB_S1D13XXX)
|
|
platform_device_register(&s1d13xxxfb_device);
|
|
#endif
|
|
return 0;
|
|
}
|
|
arch_initcall(platform_init);
|