255 lines
6.4 KiB
C
255 lines
6.4 KiB
C
/* linux/arch/arm/mach-msm/irq.c
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*
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* Copyright (c) 2009 QUALCOMM Incorporated.
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* Copyright (C) 2009 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <mach/fiq.h>
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#include <mach/msm_iomap.h>
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#include "sirc.h"
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#define SIRC_MASK 0x007FFFFF
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#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00)
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#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04)
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#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08)
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#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C)
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#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10)
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#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14)
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#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18)
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#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C)
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#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20)
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#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24)
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#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28)
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#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C)
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struct sirc_regs_t {
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void *int_enable;
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void *int_enable_clear;
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void *int_enable_set;
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void *int_type;
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void *int_polarity;
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void *int_clear;
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};
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struct sirc_cascade_regs {
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void *int_status;
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unsigned int cascade_irq;
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unsigned int cascade_fiq;
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};
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static void sirc_irq_mask(unsigned int irq);
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static void sirc_irq_unmask(unsigned int irq);
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static void sirc_irq_ack(unsigned int irq);
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static int sirc_irq_set_wake(unsigned int irq, unsigned int on);
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static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type);
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static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc);
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static unsigned int int_enable;
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static unsigned int wake_enable;
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static struct sirc_regs_t sirc_regs = {
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.int_enable = SPSS_SIRC_INT_ENABLE,
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.int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
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.int_enable_set = SPSS_SIRC_INT_ENABLE_SET,
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.int_type = SPSS_SIRC_INT_TYPE,
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.int_polarity = SPSS_SIRC_INT_POLARITY,
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.int_clear = SPSS_SIRC_INT_CLEAR,
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};
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static struct sirc_cascade_regs sirc_reg_table[] = {
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{
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.int_status = SPSS_SIRC_IRQ_STATUS,
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.cascade_irq = INT_SIRC_0,
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.cascade_fiq = INT_SIRC_1,
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}
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};
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static unsigned int save_type;
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static unsigned int save_polarity;
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/* Mask off the given interrupt. Keep the int_enable mask in sync with
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the enable reg, so it can be restored after power collapse. */
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static void sirc_irq_mask(unsigned int irq)
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{
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unsigned int mask;
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_enable_clear);
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int_enable &= ~mask;
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return;
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}
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/* Unmask the given interrupt. Keep the int_enable mask in sync with
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the enable reg, so it can be restored after power collapse. */
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static void sirc_irq_unmask(unsigned int irq)
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{
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unsigned int mask;
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_enable_set);
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int_enable |= mask;
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return;
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}
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static void sirc_irq_ack(unsigned int irq)
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{
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unsigned int mask;
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_clear);
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return;
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}
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static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
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{
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unsigned int mask;
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/* Used to set the interrupt enable mask during power collapse. */
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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if (on)
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wake_enable |= mask;
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else
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wake_enable &= ~mask;
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return 0;
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}
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static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned int mask;
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unsigned int val;
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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val = readl(sirc_regs.int_polarity);
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if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
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val |= mask;
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else
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val &= ~mask;
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writel(val, sirc_regs.int_polarity);
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val = readl(sirc_regs.int_type);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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val |= mask;
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irq_desc[irq].handle_irq = handle_edge_irq;
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} else {
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val &= ~mask;
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irq_desc[irq].handle_irq = handle_level_irq;
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}
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writel(val, sirc_regs.int_type);
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return 0;
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}
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#if defined(CONFIG_MSM_FIQ_SUPPORT)
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void sirc_fiq_select(int irq, bool enable)
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{
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uint32_t mask = 1 << (irq - FIRST_SIRC_IRQ);
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uint32_t val;
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unsigned long flags;
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local_irq_save(flags);
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val = readl(SPSS_SIRC_INT_SELECT);
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if (enable)
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val |= mask;
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else
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val &= ~mask;
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writel(val, SPSS_SIRC_INT_SELECT);
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local_irq_restore(flags);
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}
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#endif
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/* Finds the pending interrupt on the passed cascade irq and redrives it */
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static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int reg = 0;
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unsigned int sirq;
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unsigned int status;
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while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
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(sirc_reg_table[reg].cascade_irq != irq))
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reg++;
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status = readl(sirc_reg_table[reg].int_status);
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status &= SIRC_MASK;
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if (status == 0)
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return;
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for (sirq = 0;
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(sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
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sirq++)
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;
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generic_handle_irq(sirq+FIRST_SIRC_IRQ);
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desc->chip->ack(irq);
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}
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void msm_sirc_enter_sleep(void)
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{
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save_type = readl(sirc_regs.int_type);
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save_polarity = readl(sirc_regs.int_polarity);
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writel(wake_enable, sirc_regs.int_enable);
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return;
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}
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void msm_sirc_exit_sleep(void)
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{
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writel(save_type, sirc_regs.int_type);
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writel(save_polarity, sirc_regs.int_polarity);
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writel(int_enable, sirc_regs.int_enable);
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return;
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}
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static struct irq_chip sirc_irq_chip = {
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.name = "sirc",
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.ack = sirc_irq_ack,
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.mask = sirc_irq_mask,
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.unmask = sirc_irq_unmask,
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.set_wake = sirc_irq_set_wake,
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.set_type = sirc_irq_set_type,
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};
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void __init msm_init_sirc(void)
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{
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int i;
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int_enable = 0;
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wake_enable = 0;
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for (i = FIRST_SIRC_IRQ; i < FIRST_SIRC_IRQ + NR_SIRC_IRQS; i++) {
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set_irq_chip(i, &sirc_irq_chip);
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set_irq_handler(i, handle_edge_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
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set_irq_chained_handler(sirc_reg_table[i].cascade_irq,
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sirc_irq_handler);
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set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
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#if defined(CONFIG_MSM_FIQ_SUPPORT)
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msm_fiq_select(sirc_reg_table[i].cascade_fiq);
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msm_fiq_enable(sirc_reg_table[i].cascade_fiq);
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#endif
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}
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return;
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}
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