131 lines
3.0 KiB
C
131 lines
3.0 KiB
C
/*
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* arch/sh/kernel/cpu/sh4/clock-sh7757.c
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*
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* SH7757 support for the clock framework
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
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16, 1, 1, 32, 1, 1, 1, 1 };
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static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
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16, 1, 1, 32, 1, 1, 1, 1 };
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static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
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16, 1, 1, 32, 1, 1, 1, 1 };
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static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
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16, 1, 1, 32, 1, 1, 1, 1 };
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static void master_clk_init(struct clk *clk)
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{
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clk->rate = CONFIG_SH_PCLK_FREQ * 16;
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}
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static struct clk_ops sh7757_master_clk_ops = {
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.init = master_clk_init,
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};
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static void module_clk_recalc(struct clk *clk)
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{
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int idx = ctrl_inl(FRQCR) & 0x0000000f;
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clk->rate = clk->parent->rate / p1fc_divisors[idx];
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}
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static struct clk_ops sh7757_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static void bus_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f;
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clk->rate = clk->parent->rate / bfc_divisors[idx];
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}
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static struct clk_ops sh7757_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static void cpu_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f;
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clk->rate = clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops sh7757_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7757_clk_ops[] = {
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&sh7757_master_clk_ops,
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&sh7757_module_clk_ops,
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&sh7757_bus_clk_ops,
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&sh7757_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7757_clk_ops))
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*ops = sh7757_clk_ops[idx];
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}
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static void shyway_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f;
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clk->rate = clk->parent->rate / sfc_divisors[idx];
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}
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static struct clk_ops sh7757_shyway_clk_ops = {
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.recalc = shyway_clk_recalc,
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};
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static struct clk sh7757_shyway_clk = {
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.name = "shyway_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh7757_shyway_clk_ops,
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};
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/*
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* Additional sh7757-specific on-chip clocks that aren't already part of the
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* clock framework
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*/
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static struct clk *sh7757_onchip_clocks[] = {
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&sh7757_shyway_clk,
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};
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static int __init sh7757_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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int i;
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for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
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struct clk *clkp = sh7757_onchip_clocks[i];
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clkp->parent = clk;
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clk_register(clkp);
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clk_enable(clkp);
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}
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/*
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* Now that we have the rest of the clocks registered, we need to
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* force the parent clock to propagate so that these clocks will
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* automatically figure out their rate. We cheat by handing the
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* parent clock its current rate and forcing child propagation.
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*/
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clk_set_rate(clk, clk_get_rate(clk));
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clk_put(clk);
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return 0;
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}
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arch_initcall(sh7757_clk_init);
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