1059 lines
26 KiB
C
1059 lines
26 KiB
C
/*
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* PCI Express PCI Hot Plug Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/signal.h>
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#include <linux/jiffies.h>
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#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include "../pci.h"
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#include "pciehp.h"
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static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
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static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
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{
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struct pci_dev *dev = ctrl->pcie->port;
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return pci_read_config_word(dev, ctrl->cap_base + reg, value);
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}
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static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
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{
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struct pci_dev *dev = ctrl->pcie->port;
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return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
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}
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static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
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{
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struct pci_dev *dev = ctrl->pcie->port;
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return pci_write_config_word(dev, ctrl->cap_base + reg, value);
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}
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static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
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{
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struct pci_dev *dev = ctrl->pcie->port;
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return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
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}
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/* Power Control Command */
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#define POWER_ON 0
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#define POWER_OFF PCI_EXP_SLTCTL_PCC
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static irqreturn_t pcie_isr(int irq, void *dev_id);
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static void start_int_poll_timer(struct controller *ctrl, int sec);
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/* This is the interrupt polling timeout function. */
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static void int_poll_timeout(unsigned long data)
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{
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struct controller *ctrl = (struct controller *)data;
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/* Poll for interrupt events. regs == NULL => polling */
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pcie_isr(0, ctrl);
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init_timer(&ctrl->poll_timer);
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if (!pciehp_poll_time)
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pciehp_poll_time = 2; /* default polling interval is 2 sec */
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start_int_poll_timer(ctrl, pciehp_poll_time);
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}
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/* This function starts the interrupt polling timer. */
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static void start_int_poll_timer(struct controller *ctrl, int sec)
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{
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/* Clamp to sane value */
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if ((sec <= 0) || (sec > 60))
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sec = 2;
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ctrl->poll_timer.function = &int_poll_timeout;
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ctrl->poll_timer.data = (unsigned long)ctrl;
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ctrl->poll_timer.expires = jiffies + sec * HZ;
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add_timer(&ctrl->poll_timer);
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}
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static inline int pciehp_request_irq(struct controller *ctrl)
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{
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int retval, irq = ctrl->pcie->irq;
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/* Install interrupt polling timer. Start with 10 sec delay */
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if (pciehp_poll_mode) {
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init_timer(&ctrl->poll_timer);
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start_int_poll_timer(ctrl, 10);
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return 0;
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}
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/* Installs the interrupt handler */
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retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
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if (retval)
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ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
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irq);
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return retval;
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}
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static inline void pciehp_free_irq(struct controller *ctrl)
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{
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if (pciehp_poll_mode)
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del_timer_sync(&ctrl->poll_timer);
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else
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free_irq(ctrl->pcie->irq, ctrl);
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}
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static int pcie_poll_cmd(struct controller *ctrl)
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{
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u16 slot_status;
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int err, timeout = 1000;
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err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
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pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
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return 1;
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}
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while (timeout > 0) {
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msleep(10);
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timeout -= 10;
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err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
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pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
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return 1;
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}
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}
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return 0; /* timeout */
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}
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static void pcie_wait_cmd(struct controller *ctrl, int poll)
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{
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unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
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unsigned long timeout = msecs_to_jiffies(msecs);
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int rc;
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if (poll)
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rc = pcie_poll_cmd(ctrl);
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else
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rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
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if (!rc)
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ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
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}
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/**
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* pcie_write_cmd - Issue controller command
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* @ctrl: controller to which the command is issued
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* @cmd: command value written to slot control register
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* @mask: bitmask of slot control register to be modified
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*/
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static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
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{
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int retval = 0;
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u16 slot_status;
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u16 slot_ctrl;
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mutex_lock(&ctrl->ctrl_lock);
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retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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if (retval) {
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ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
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__func__);
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goto out;
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}
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if (slot_status & PCI_EXP_SLTSTA_CC) {
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if (!ctrl->no_cmd_complete) {
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/*
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* After 1 sec and CMD_COMPLETED still not set, just
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* proceed forward to issue the next command according
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* to spec. Just print out the error message.
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*/
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ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
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} else if (!NO_CMD_CMPL(ctrl)) {
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/*
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* This controller semms to notify of command completed
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* event even though it supports none of power
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* controller, attention led, power led and EMI.
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*/
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ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
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"wait for command completed event.\n");
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ctrl->no_cmd_complete = 0;
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} else {
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ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
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"the controller is broken.\n");
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}
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}
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retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
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if (retval) {
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ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
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goto out;
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}
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slot_ctrl &= ~mask;
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slot_ctrl |= (cmd & mask);
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ctrl->cmd_busy = 1;
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smp_mb();
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retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
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if (retval)
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ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
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/*
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* Wait for command completion.
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*/
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if (!retval && !ctrl->no_cmd_complete) {
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int poll = 0;
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/*
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* if hotplug interrupt is not enabled or command
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* completed interrupt is not enabled, we need to poll
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* command completed event.
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*/
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if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
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!(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
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poll = 1;
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pcie_wait_cmd(ctrl, poll);
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}
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out:
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mutex_unlock(&ctrl->ctrl_lock);
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return retval;
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}
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static inline int check_link_active(struct controller *ctrl)
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{
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u16 link_status;
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if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
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return 0;
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return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
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}
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static void pcie_wait_link_active(struct controller *ctrl)
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{
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int timeout = 1000;
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if (check_link_active(ctrl))
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return;
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while (timeout > 0) {
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msleep(10);
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timeout -= 10;
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if (check_link_active(ctrl))
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return;
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}
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ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
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}
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int pciehp_check_link_status(struct controller *ctrl)
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{
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u16 lnk_status;
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int retval = 0;
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/*
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* Data Link Layer Link Active Reporting must be capable for
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* hot-plug capable downstream port. But old controller might
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* not implement it. In this case, we wait for 1000 ms.
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*/
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if (ctrl->link_active_reporting){
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/* Wait for Data Link Layer Link Active bit to be set */
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pcie_wait_link_active(ctrl);
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/*
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* We must wait for 100 ms after the Data Link Layer
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* Link Active bit reads 1b before initiating a
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* configuration access to the hot added device.
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*/
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msleep(100);
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} else
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msleep(1000);
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retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
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if (retval) {
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ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
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return retval;
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}
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ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
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if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
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!(lnk_status & PCI_EXP_LNKSTA_NLW)) {
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ctrl_err(ctrl, "Link Training Error occurs \n");
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retval = -1;
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return retval;
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}
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return retval;
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}
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int pciehp_get_attention_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_ctrl;
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u8 atten_led_state;
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int retval = 0;
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retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
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if (retval) {
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ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
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return retval;
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}
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
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atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
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switch (atten_led_state) {
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case 0:
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*status = 0xFF; /* Reserved */
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break;
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case 1:
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*status = 1; /* On */
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break;
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case 2:
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*status = 2; /* Blink */
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break;
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case 3:
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*status = 0; /* Off */
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break;
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default:
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*status = 0xFF;
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break;
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}
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return 0;
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}
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int pciehp_get_power_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_ctrl;
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u8 pwr_state;
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int retval = 0;
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retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
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if (retval) {
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ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
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return retval;
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}
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
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pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
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switch (pwr_state) {
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case 0:
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*status = 1;
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break;
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case 1:
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*status = 0;
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break;
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default:
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*status = 0xFF;
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break;
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}
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return retval;
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}
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int pciehp_get_latch_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_status;
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int retval;
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retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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if (retval) {
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ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
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__func__);
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return retval;
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}
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*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
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return 0;
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}
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int pciehp_get_adapter_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_status;
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int retval;
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retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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if (retval) {
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ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
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__func__);
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return retval;
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}
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*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
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return 0;
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}
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int pciehp_query_power_fault(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_status;
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int retval;
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retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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if (retval) {
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ctrl_err(ctrl, "Cannot check for power fault\n");
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return retval;
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}
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return !!(slot_status & PCI_EXP_SLTSTA_PFD);
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}
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int pciehp_set_attention_status(struct slot *slot, u8 value)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_cmd;
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u16 cmd_mask;
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int rc;
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cmd_mask = PCI_EXP_SLTCTL_AIC;
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switch (value) {
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case 0 : /* turn off */
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slot_cmd = 0x00C0;
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break;
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case 1: /* turn on */
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slot_cmd = 0x0040;
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break;
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case 2: /* turn blink */
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slot_cmd = 0x0080;
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break;
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default:
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return -1;
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}
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rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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return rc;
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}
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void pciehp_green_led_on(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_cmd;
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u16 cmd_mask;
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slot_cmd = 0x0100;
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cmd_mask = PCI_EXP_SLTCTL_PIC;
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pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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}
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void pciehp_green_led_off(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_cmd;
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u16 cmd_mask;
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slot_cmd = 0x0300;
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cmd_mask = PCI_EXP_SLTCTL_PIC;
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pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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}
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void pciehp_green_led_blink(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_cmd;
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u16 cmd_mask;
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slot_cmd = 0x0200;
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cmd_mask = PCI_EXP_SLTCTL_PIC;
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pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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}
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int pciehp_power_on_slot(struct slot * slot)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_cmd;
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u16 cmd_mask;
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u16 slot_status;
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int retval = 0;
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/* Clear sticky power-fault bit from previous power failures */
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retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
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if (retval) {
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ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
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__func__);
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return retval;
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}
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slot_status &= PCI_EXP_SLTSTA_PFD;
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if (slot_status) {
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retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
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if (retval) {
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ctrl_err(ctrl,
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"%s: Cannot write to SLOTSTATUS register\n",
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__func__);
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return retval;
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}
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}
|
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|
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slot_cmd = POWER_ON;
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cmd_mask = PCI_EXP_SLTCTL_PCC;
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if (!pciehp_poll_mode) {
|
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/* Enable power fault detection turned off at power off time */
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slot_cmd |= PCI_EXP_SLTCTL_PFDE;
|
|
cmd_mask |= PCI_EXP_SLTCTL_PFDE;
|
|
}
|
|
|
|
retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
|
|
if (retval) {
|
|
ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
|
|
return retval;
|
|
}
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
|
|
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
|
|
|
|
ctrl->power_fault_detected = 0;
|
|
return retval;
|
|
}
|
|
|
|
static inline int pcie_mask_bad_dllp(struct controller *ctrl)
|
|
{
|
|
struct pci_dev *dev = ctrl->pcie->port;
|
|
int pos;
|
|
u32 reg;
|
|
|
|
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
|
|
if (!pos)
|
|
return 0;
|
|
pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
|
|
if (reg & PCI_ERR_COR_BAD_DLLP)
|
|
return 0;
|
|
reg |= PCI_ERR_COR_BAD_DLLP;
|
|
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
|
|
return 1;
|
|
}
|
|
|
|
static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
|
|
{
|
|
struct pci_dev *dev = ctrl->pcie->port;
|
|
u32 reg;
|
|
int pos;
|
|
|
|
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
|
|
if (!pos)
|
|
return;
|
|
pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
|
|
if (!(reg & PCI_ERR_COR_BAD_DLLP))
|
|
return;
|
|
reg &= ~PCI_ERR_COR_BAD_DLLP;
|
|
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
|
|
}
|
|
|
|
int pciehp_power_off_slot(struct slot * slot)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
u16 slot_cmd;
|
|
u16 cmd_mask;
|
|
int retval = 0;
|
|
int changed;
|
|
|
|
/*
|
|
* Set Bad DLLP Mask bit in Correctable Error Mask
|
|
* Register. This is the workaround against Bad DLLP error
|
|
* that sometimes happens during turning power off the slot
|
|
* which conforms to PCI Express 1.0a spec.
|
|
*/
|
|
changed = pcie_mask_bad_dllp(ctrl);
|
|
|
|
slot_cmd = POWER_OFF;
|
|
cmd_mask = PCI_EXP_SLTCTL_PCC;
|
|
if (!pciehp_poll_mode) {
|
|
/* Disable power fault detection */
|
|
slot_cmd &= ~PCI_EXP_SLTCTL_PFDE;
|
|
cmd_mask |= PCI_EXP_SLTCTL_PFDE;
|
|
}
|
|
|
|
retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
|
|
if (retval) {
|
|
ctrl_err(ctrl, "Write command failed!\n");
|
|
retval = -1;
|
|
goto out;
|
|
}
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
|
|
__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
|
|
out:
|
|
if (changed)
|
|
pcie_unmask_bad_dllp(ctrl);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static irqreturn_t pcie_isr(int irq, void *dev_id)
|
|
{
|
|
struct controller *ctrl = (struct controller *)dev_id;
|
|
struct slot *slot = ctrl->slot;
|
|
u16 detected, intr_loc;
|
|
|
|
/*
|
|
* In order to guarantee that all interrupt events are
|
|
* serviced, we need to re-inspect Slot Status register after
|
|
* clearing what is presumed to be the last pending interrupt.
|
|
*/
|
|
intr_loc = 0;
|
|
do {
|
|
if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
|
|
ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
|
|
__func__);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
|
|
PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
|
|
PCI_EXP_SLTSTA_CC);
|
|
detected &= ~intr_loc;
|
|
intr_loc |= detected;
|
|
if (!intr_loc)
|
|
return IRQ_NONE;
|
|
if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
|
|
ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
|
|
__func__);
|
|
return IRQ_NONE;
|
|
}
|
|
} while (detected);
|
|
|
|
ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
|
|
|
|
/* Check Command Complete Interrupt Pending */
|
|
if (intr_loc & PCI_EXP_SLTSTA_CC) {
|
|
ctrl->cmd_busy = 0;
|
|
smp_mb();
|
|
wake_up(&ctrl->queue);
|
|
}
|
|
|
|
if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
|
|
return IRQ_HANDLED;
|
|
|
|
/* Check MRL Sensor Changed */
|
|
if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
|
|
pciehp_handle_switch_change(slot);
|
|
|
|
/* Check Attention Button Pressed */
|
|
if (intr_loc & PCI_EXP_SLTSTA_ABP)
|
|
pciehp_handle_attention_button(slot);
|
|
|
|
/* Check Presence Detect Changed */
|
|
if (intr_loc & PCI_EXP_SLTSTA_PDC)
|
|
pciehp_handle_presence_change(slot);
|
|
|
|
/* Check Power Fault Detected */
|
|
if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
|
|
ctrl->power_fault_detected = 1;
|
|
pciehp_handle_power_fault(slot);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *value)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
enum pcie_link_speed lnk_speed;
|
|
u32 lnk_cap;
|
|
int retval = 0;
|
|
|
|
retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
|
|
if (retval) {
|
|
ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
|
|
return retval;
|
|
}
|
|
|
|
switch (lnk_cap & 0x000F) {
|
|
case 1:
|
|
lnk_speed = PCIE_2_5GB;
|
|
break;
|
|
case 2:
|
|
lnk_speed = PCIE_5_0GB;
|
|
break;
|
|
default:
|
|
lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
|
|
break;
|
|
}
|
|
|
|
*value = lnk_speed;
|
|
ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
|
|
|
|
return retval;
|
|
}
|
|
|
|
int pciehp_get_max_lnk_width(struct slot *slot,
|
|
enum pcie_link_width *value)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
enum pcie_link_width lnk_wdth;
|
|
u32 lnk_cap;
|
|
int retval = 0;
|
|
|
|
retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
|
|
if (retval) {
|
|
ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
|
|
return retval;
|
|
}
|
|
|
|
switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
|
|
case 0:
|
|
lnk_wdth = PCIE_LNK_WIDTH_RESRV;
|
|
break;
|
|
case 1:
|
|
lnk_wdth = PCIE_LNK_X1;
|
|
break;
|
|
case 2:
|
|
lnk_wdth = PCIE_LNK_X2;
|
|
break;
|
|
case 4:
|
|
lnk_wdth = PCIE_LNK_X4;
|
|
break;
|
|
case 8:
|
|
lnk_wdth = PCIE_LNK_X8;
|
|
break;
|
|
case 12:
|
|
lnk_wdth = PCIE_LNK_X12;
|
|
break;
|
|
case 16:
|
|
lnk_wdth = PCIE_LNK_X16;
|
|
break;
|
|
case 32:
|
|
lnk_wdth = PCIE_LNK_X32;
|
|
break;
|
|
default:
|
|
lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
|
|
break;
|
|
}
|
|
|
|
*value = lnk_wdth;
|
|
ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
|
|
|
|
return retval;
|
|
}
|
|
|
|
int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *value)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
|
|
int retval = 0;
|
|
u16 lnk_status;
|
|
|
|
retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
|
|
if (retval) {
|
|
ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
|
|
__func__);
|
|
return retval;
|
|
}
|
|
|
|
switch (lnk_status & PCI_EXP_LNKSTA_CLS) {
|
|
case 1:
|
|
lnk_speed = PCIE_2_5GB;
|
|
break;
|
|
case 2:
|
|
lnk_speed = PCIE_5_0GB;
|
|
break;
|
|
default:
|
|
lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
|
|
break;
|
|
}
|
|
|
|
*value = lnk_speed;
|
|
ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
|
|
|
|
return retval;
|
|
}
|
|
|
|
int pciehp_get_cur_lnk_width(struct slot *slot,
|
|
enum pcie_link_width *value)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
|
|
int retval = 0;
|
|
u16 lnk_status;
|
|
|
|
retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
|
|
if (retval) {
|
|
ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
|
|
__func__);
|
|
return retval;
|
|
}
|
|
|
|
switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
|
|
case 0:
|
|
lnk_wdth = PCIE_LNK_WIDTH_RESRV;
|
|
break;
|
|
case 1:
|
|
lnk_wdth = PCIE_LNK_X1;
|
|
break;
|
|
case 2:
|
|
lnk_wdth = PCIE_LNK_X2;
|
|
break;
|
|
case 4:
|
|
lnk_wdth = PCIE_LNK_X4;
|
|
break;
|
|
case 8:
|
|
lnk_wdth = PCIE_LNK_X8;
|
|
break;
|
|
case 12:
|
|
lnk_wdth = PCIE_LNK_X12;
|
|
break;
|
|
case 16:
|
|
lnk_wdth = PCIE_LNK_X16;
|
|
break;
|
|
case 32:
|
|
lnk_wdth = PCIE_LNK_X32;
|
|
break;
|
|
default:
|
|
lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
|
|
break;
|
|
}
|
|
|
|
*value = lnk_wdth;
|
|
ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
|
|
|
|
return retval;
|
|
}
|
|
|
|
int pcie_enable_notification(struct controller *ctrl)
|
|
{
|
|
u16 cmd, mask;
|
|
|
|
cmd = PCI_EXP_SLTCTL_PDCE;
|
|
if (ATTN_BUTTN(ctrl))
|
|
cmd |= PCI_EXP_SLTCTL_ABPE;
|
|
if (POWER_CTRL(ctrl))
|
|
cmd |= PCI_EXP_SLTCTL_PFDE;
|
|
if (MRL_SENS(ctrl))
|
|
cmd |= PCI_EXP_SLTCTL_MRLSCE;
|
|
if (!pciehp_poll_mode)
|
|
cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
|
|
|
|
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
|
|
PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
|
|
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
|
|
|
|
if (pcie_write_cmd(ctrl, cmd, mask)) {
|
|
ctrl_err(ctrl, "Cannot enable software notification\n");
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void pcie_disable_notification(struct controller *ctrl)
|
|
{
|
|
u16 mask;
|
|
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
|
|
PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
|
|
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
|
|
if (pcie_write_cmd(ctrl, 0, mask))
|
|
ctrl_warn(ctrl, "Cannot disable software notification\n");
|
|
}
|
|
|
|
int pcie_init_notification(struct controller *ctrl)
|
|
{
|
|
if (pciehp_request_irq(ctrl))
|
|
return -1;
|
|
if (pcie_enable_notification(ctrl)) {
|
|
pciehp_free_irq(ctrl);
|
|
return -1;
|
|
}
|
|
ctrl->notification_enabled = 1;
|
|
return 0;
|
|
}
|
|
|
|
static void pcie_shutdown_notification(struct controller *ctrl)
|
|
{
|
|
if (ctrl->notification_enabled) {
|
|
pcie_disable_notification(ctrl);
|
|
pciehp_free_irq(ctrl);
|
|
ctrl->notification_enabled = 0;
|
|
}
|
|
}
|
|
|
|
static int pcie_init_slot(struct controller *ctrl)
|
|
{
|
|
struct slot *slot;
|
|
|
|
slot = kzalloc(sizeof(*slot), GFP_KERNEL);
|
|
if (!slot)
|
|
return -ENOMEM;
|
|
|
|
slot->ctrl = ctrl;
|
|
mutex_init(&slot->lock);
|
|
INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
|
|
ctrl->slot = slot;
|
|
return 0;
|
|
}
|
|
|
|
static void pcie_cleanup_slot(struct controller *ctrl)
|
|
{
|
|
struct slot *slot = ctrl->slot;
|
|
cancel_delayed_work(&slot->work);
|
|
flush_scheduled_work();
|
|
flush_workqueue(pciehp_wq);
|
|
kfree(slot);
|
|
}
|
|
|
|
static inline void dbg_ctrl(struct controller *ctrl)
|
|
{
|
|
int i;
|
|
u16 reg16;
|
|
struct pci_dev *pdev = ctrl->pcie->port;
|
|
|
|
if (!pciehp_debug)
|
|
return;
|
|
|
|
ctrl_info(ctrl, "Hotplug Controller:\n");
|
|
ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
|
|
pci_name(pdev), pdev->irq);
|
|
ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
|
|
ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
|
|
ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
|
|
pdev->subsystem_device);
|
|
ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
|
|
pdev->subsystem_vendor);
|
|
ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
|
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
|
if (!pci_resource_len(pdev, i))
|
|
continue;
|
|
ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n",
|
|
i, (unsigned long long)pci_resource_len(pdev, i),
|
|
(unsigned long long)pci_resource_start(pdev, i));
|
|
}
|
|
ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
|
|
ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
|
|
ctrl_info(ctrl, " Attention Button : %3s\n",
|
|
ATTN_BUTTN(ctrl) ? "yes" : "no");
|
|
ctrl_info(ctrl, " Power Controller : %3s\n",
|
|
POWER_CTRL(ctrl) ? "yes" : "no");
|
|
ctrl_info(ctrl, " MRL Sensor : %3s\n",
|
|
MRL_SENS(ctrl) ? "yes" : "no");
|
|
ctrl_info(ctrl, " Attention Indicator : %3s\n",
|
|
ATTN_LED(ctrl) ? "yes" : "no");
|
|
ctrl_info(ctrl, " Power Indicator : %3s\n",
|
|
PWR_LED(ctrl) ? "yes" : "no");
|
|
ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
|
|
HP_SUPR_RM(ctrl) ? "yes" : "no");
|
|
ctrl_info(ctrl, " EMI Present : %3s\n",
|
|
EMI(ctrl) ? "yes" : "no");
|
|
ctrl_info(ctrl, " Command Completed : %3s\n",
|
|
NO_CMD_CMPL(ctrl) ? "no" : "yes");
|
|
pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
|
|
ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
|
|
pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
|
|
ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
|
|
}
|
|
|
|
struct controller *pcie_init(struct pcie_device *dev)
|
|
{
|
|
struct controller *ctrl;
|
|
u32 slot_cap, link_cap;
|
|
struct pci_dev *pdev = dev->port;
|
|
|
|
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
|
|
if (!ctrl) {
|
|
dev_err(&dev->device, "%s: Out of memory\n", __func__);
|
|
goto abort;
|
|
}
|
|
ctrl->pcie = dev;
|
|
ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
|
|
if (!ctrl->cap_base) {
|
|
ctrl_err(ctrl, "Cannot find PCI Express capability\n");
|
|
goto abort_ctrl;
|
|
}
|
|
if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
|
|
ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
|
|
goto abort_ctrl;
|
|
}
|
|
|
|
ctrl->slot_cap = slot_cap;
|
|
mutex_init(&ctrl->ctrl_lock);
|
|
init_waitqueue_head(&ctrl->queue);
|
|
dbg_ctrl(ctrl);
|
|
/*
|
|
* Controller doesn't notify of command completion if the "No
|
|
* Command Completed Support" bit is set in Slot Capability
|
|
* register or the controller supports none of power
|
|
* controller, attention led, power led and EMI.
|
|
*/
|
|
if (NO_CMD_CMPL(ctrl) ||
|
|
!(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
|
|
ctrl->no_cmd_complete = 1;
|
|
|
|
/* Check if Data Link Layer Link Active Reporting is implemented */
|
|
if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
|
|
ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
|
|
goto abort_ctrl;
|
|
}
|
|
if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
|
|
ctrl_dbg(ctrl, "Link Active Reporting supported\n");
|
|
ctrl->link_active_reporting = 1;
|
|
}
|
|
|
|
/* Clear all remaining event bits in Slot Status register */
|
|
if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
|
|
goto abort_ctrl;
|
|
|
|
/* Disable sotfware notification */
|
|
pcie_disable_notification(ctrl);
|
|
|
|
/*
|
|
* If this is the first controller to be initialized,
|
|
* initialize the pciehp work queue
|
|
*/
|
|
if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
|
|
pciehp_wq = create_singlethread_workqueue("pciehpd");
|
|
if (!pciehp_wq)
|
|
goto abort_ctrl;
|
|
}
|
|
|
|
ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
|
|
pdev->vendor, pdev->device, pdev->subsystem_vendor,
|
|
pdev->subsystem_device);
|
|
|
|
if (pcie_init_slot(ctrl))
|
|
goto abort_ctrl;
|
|
|
|
return ctrl;
|
|
|
|
abort_ctrl:
|
|
kfree(ctrl);
|
|
abort:
|
|
return NULL;
|
|
}
|
|
|
|
void pciehp_release_ctrl(struct controller *ctrl)
|
|
{
|
|
pcie_shutdown_notification(ctrl);
|
|
pcie_cleanup_slot(ctrl);
|
|
/*
|
|
* If this is the last controller to be released, destroy the
|
|
* pciehp work queue
|
|
*/
|
|
if (atomic_dec_and_test(&pciehp_num_controllers))
|
|
destroy_workqueue(pciehp_wq);
|
|
kfree(ctrl);
|
|
}
|