131 lines
3.5 KiB
ArmAsm
131 lines
3.5 KiB
ArmAsm
/*
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* Assembly Language Functions for MIPS MT SMTC support
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*/
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/*
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* This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. */
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#include <asm/regdef.h>
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#include <asm/asmmacro.h>
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#include <asm/stackframe.h>
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#include <asm/irqflags.h>
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/*
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* "Software Interrupt" linkage.
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*
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* This is invoked when an "Interrupt" is sent from one TC to another,
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* where the TC to be interrupted is halted, has it's Restart address
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* and Status values saved by the "remote control" thread, then modified
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* to cause execution to begin here, in kenel mode. This code then
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* disguises the TC state as that of an exception and transfers
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* control to the general exception or vectored interrupt handler.
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*/
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.set noreorder
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/*
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The __smtc_ipi_vector would use k0 and k1 as temporaries and
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1) Set EXL (this is per-VPE, so this can't be done by proxy!)
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2) Restore the K/CU and IXMT bits to the pre "exception" state
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(EXL means no interrupts and access to the kernel map).
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3) Set EPC to be the saved value of TCRestart.
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4) Jump to the exception handler entry point passed by the sender.
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CAN WE PROVE THAT WE WON'T DO THIS IF INTS DISABLED??
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*/
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/*
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* Reviled and slandered vision: Set EXL and restore K/CU/IXMT
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* state of pre-halt thread, then save everything and call
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* thought some function pointer to imaginary_exception, which
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* will parse a register value or memory message queue to
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* deliver things like interprocessor interrupts. On return
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* from that function, jump to the global ret_from_irq code
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* to invoke the scheduler and return as appropriate.
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*/
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#define PT_PADSLOT4 (PT_R0-8)
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#define PT_PADSLOT5 (PT_R0-4)
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.text
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.align 5
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FEXPORT(__smtc_ipi_vector)
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.set noat
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/* Disable thread scheduling to make Status update atomic */
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DMT 27 # dmt k1
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_ehb
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/* Set EXL */
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mfc0 k0,CP0_STATUS
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ori k0,k0,ST0_EXL
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mtc0 k0,CP0_STATUS
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_ehb
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/* Thread scheduling now inhibited by EXL. Restore TE state. */
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andi k1,k1,VPECONTROL_TE
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beqz k1,1f
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emt
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1:
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/*
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* The IPI sender has put some information on the anticipated
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* kernel stack frame. If we were in user mode, this will be
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* built above the saved kernel SP. If we were already in the
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* kernel, it will be built above the current CPU SP.
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*
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* Were we in kernel mode, as indicated by CU0?
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*/
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sll k1,k0,3
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.set noreorder
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bltz k1,2f
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move k1,sp
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.set reorder
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/*
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* If previously in user mode, set CU0 and use kernel stack.
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*/
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li k1,ST0_CU0
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or k1,k1,k0
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mtc0 k1,CP0_STATUS
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_ehb
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get_saved_sp
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/* Interrupting TC will have pre-set values in slots in the new frame */
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2: subu k1,k1,PT_SIZE
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/* Load TCStatus Value */
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lw k0,PT_TCSTATUS(k1)
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/* Write it to TCStatus to restore CU/KSU/IXMT state */
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mtc0 k0,$2,1
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_ehb
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lw k0,PT_EPC(k1)
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mtc0 k0,CP0_EPC
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/* Save all will redundantly recompute the SP, but use it for now */
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SAVE_ALL
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CLI
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TRACE_IRQS_OFF
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/* Function to be invoked passed stack pad slot 5 */
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lw t0,PT_PADSLOT5(sp)
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/* Argument from sender passed in stack pad slot 4 */
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lw a0,PT_PADSLOT4(sp)
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LONG_L s0, TI_REGS($28)
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LONG_S sp, TI_REGS($28)
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PTR_LA ra, ret_from_irq
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jr t0
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/*
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* Called from idle loop to provoke processing of queued IPIs
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* First IPI message in queue passed as argument.
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*/
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LEAF(self_ipi)
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/* Before anything else, block interrupts */
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mfc0 t0,CP0_TCSTATUS
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ori t1,t0,TCSTATUS_IXMT
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mtc0 t1,CP0_TCSTATUS
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_ehb
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/* We know we're in kernel mode, so prepare stack frame */
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subu t1,sp,PT_SIZE
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sw ra,PT_EPC(t1)
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sw a0,PT_PADSLOT4(t1)
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la t2,ipi_decode
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sw t2,PT_PADSLOT5(t1)
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/* Save pre-disable value of TCStatus */
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sw t0,PT_TCSTATUS(t1)
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j __smtc_ipi_vector
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nop
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END(self_ipi)
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