339 lines
8.2 KiB
C
339 lines
8.2 KiB
C
/*
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* arch/arm/mach-ixp23xx/ixdp2351.c
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*
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* IXDP2351 board-specific routines
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* Based on 2.4 code Copyright 2004 (c) Intel Corporation
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/bitops.h>
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#include <linux/ioport.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_core.h>
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#include <linux/device.h>
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include <linux/mtd/physmap.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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/*
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* IXDP2351 Interrupt Handling
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*/
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static void ixdp2351_inta_mask(unsigned int irq)
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{
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*IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
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}
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static void ixdp2351_inta_unmask(unsigned int irq)
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{
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*IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
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}
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static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
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{
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u16 ex_interrupt =
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*IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
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int i;
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desc->chip->mask(irq);
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for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
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if (ex_interrupt & (1 << i)) {
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int cpld_irq =
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IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
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generic_handle_irq(cpld_irq);
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}
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}
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desc->chip->unmask(irq);
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}
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static struct irq_chip ixdp2351_inta_chip = {
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.ack = ixdp2351_inta_mask,
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.mask = ixdp2351_inta_mask,
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.unmask = ixdp2351_inta_unmask
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};
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static void ixdp2351_intb_mask(unsigned int irq)
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{
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*IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
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}
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static void ixdp2351_intb_unmask(unsigned int irq)
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{
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*IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
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}
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static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
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{
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u16 ex_interrupt =
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*IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
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int i;
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desc->chip->ack(irq);
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for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
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if (ex_interrupt & (1 << i)) {
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int cpld_irq =
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IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
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generic_handle_irq(cpld_irq);
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}
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}
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desc->chip->unmask(irq);
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}
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static struct irq_chip ixdp2351_intb_chip = {
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.ack = ixdp2351_intb_mask,
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.mask = ixdp2351_intb_mask,
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.unmask = ixdp2351_intb_unmask
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};
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void __init ixdp2351_init_irq(void)
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{
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int irq;
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/* Mask all interrupts from CPLD, disable simulation */
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*IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
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*IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
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*IXDP2351_CPLD_INTA_SIM_REG = 0;
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*IXDP2351_CPLD_INTB_SIM_REG = 0;
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ixp23xx_init_irq();
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for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
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irq <
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IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
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irq++) {
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if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
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set_irq_flags(irq, IRQF_VALID);
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set_irq_handler(irq, handle_level_irq);
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set_irq_chip(irq, &ixdp2351_inta_chip);
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}
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}
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for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
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irq <
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IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
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irq++) {
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if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
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set_irq_flags(irq, IRQF_VALID);
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set_irq_handler(irq, handle_level_irq);
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set_irq_chip(irq, &ixdp2351_intb_chip);
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}
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}
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set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
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set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
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}
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/*
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* IXDP2351 PCI
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*/
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/*
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* This board does not do normal PCI IRQ routing, or any
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* sort of swizzling, so we just need to check where on the
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* bus the device is and figure out what CPLD pin it is
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* being routed to.
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*/
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#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
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static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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u8 bus = dev->bus->number;
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u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
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struct pci_bus *tmp_bus = dev->bus;
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/* Primary bus, no interrupts here */
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if (!bus)
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return -1;
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/* Lookup first leaf in bus tree */
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while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
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tmp_bus = tmp_bus->parent;
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/* Select between known bridges */
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switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
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/* Device is located after first bridge */
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case 0x0008:
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if (tmp_bus == dev->bus) {
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/* Device is located directy after first bridge */
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switch (devpin) {
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/* Onboard 82546 */
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case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
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return IRQ_IXDP2351_INTA_82546;
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case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
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return IRQ_IXDP2351_INTB_82546;
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/* PMC SLOT */
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case DEVPIN(0, 1): /* PMCP INTA# */
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case DEVPIN(2, 4): /* PMCS INTD# */
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return IRQ_IXDP2351_SPCI_PMC_INTA;
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case DEVPIN(0, 2): /* PMCP INTB# */
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case DEVPIN(2, 1): /* PMCS INTA# */
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return IRQ_IXDP2351_SPCI_PMC_INTB;
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case DEVPIN(0, 3): /* PMCP INTC# */
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case DEVPIN(2, 2): /* PMCS INTB# */
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return IRQ_IXDP2351_SPCI_PMC_INTC;
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case DEVPIN(0, 4): /* PMCP INTD# */
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case DEVPIN(2, 3): /* PMCS INTC# */
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return IRQ_IXDP2351_SPCI_PMC_INTD;
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}
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} else {
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/* Device is located indirectly after first bridge */
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/* Not supported now */
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return -1;
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}
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break;
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case 0x0010:
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if (tmp_bus == dev->bus) {
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/* Device is located directy after second bridge */
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/* Secondary bus of second bridge */
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switch (devpin) {
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case DEVPIN(0, 1): /* DB#0 */
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case DEVPIN(0, 2):
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case DEVPIN(0, 3):
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case DEVPIN(0, 4):
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return IRQ_IXDP2351_SPCI_DB_0;
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case DEVPIN(1, 1): /* DB#1 */
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case DEVPIN(1, 2):
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case DEVPIN(1, 3):
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case DEVPIN(1, 4):
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return IRQ_IXDP2351_SPCI_DB_1;
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case DEVPIN(2, 1): /* FIC1 */
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case DEVPIN(2, 2):
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case DEVPIN(2, 3):
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case DEVPIN(2, 4):
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case DEVPIN(3, 1): /* FIC2 */
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case DEVPIN(3, 2):
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case DEVPIN(3, 3):
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case DEVPIN(3, 4):
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return IRQ_IXDP2351_SPCI_FIC;
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}
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} else {
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/* Device is located indirectly after second bridge */
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/* Not supported now */
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return -1;
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}
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break;
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}
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return -1;
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}
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struct hw_pci ixdp2351_pci __initdata = {
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.nr_controllers = 1,
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.preinit = ixp23xx_pci_preinit,
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.setup = ixp23xx_pci_setup,
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.scan = ixp23xx_pci_scan_bus,
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.map_irq = ixdp2351_map_irq,
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};
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int __init ixdp2351_pci_init(void)
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{
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if (machine_is_ixdp2351())
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pci_common_init(&ixdp2351_pci);
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return 0;
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}
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subsys_initcall(ixdp2351_pci_init);
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/*
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* IXDP2351 Static Mapped I/O
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*/
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static struct map_desc ixdp2351_io_desc[] __initdata = {
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{
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.virtual = IXDP2351_NP_VIRT_BASE,
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.pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
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.length = IXDP2351_NP_PHYS_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = IXDP2351_BB_BASE_VIRT,
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.pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
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.length = IXDP2351_BB_SIZE,
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.type = MT_DEVICE
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}
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};
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static void __init ixdp2351_map_io(void)
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{
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ixp23xx_map_io();
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iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
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}
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static struct physmap_flash_data ixdp2351_flash_data = {
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.width = 1,
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};
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static struct resource ixdp2351_flash_resource = {
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.start = 0x90000000,
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.end = 0x93ffffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ixdp2351_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &ixdp2351_flash_data,
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},
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.num_resources = 1,
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.resource = &ixdp2351_flash_resource,
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};
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static void __init ixdp2351_init(void)
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{
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platform_device_register(&ixdp2351_flash);
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/*
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* Mark flash as writeable
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*/
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IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
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IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
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IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
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IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
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ixp23xx_sys_init();
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}
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MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.phys_io = IXP23XX_PERIPHERAL_PHYS,
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.io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
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.map_io = ixdp2351_map_io,
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.init_irq = ixdp2351_init_irq,
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.timer = &ixp23xx_timer,
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.boot_params = 0x00000100,
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.init_machine = ixdp2351_init,
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MACHINE_END
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