220 lines
6.0 KiB
C
220 lines
6.0 KiB
C
/*
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* linux/arch/arm/mach-at91/at91rm9200_time.c
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*
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* Copyright (C) 2003 SAN People
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* Copyright (C) 2003 ATMEL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clockchips.h>
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#include <asm/mach/time.h>
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#include <mach/at91_st.h>
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static unsigned long last_crtr;
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static u32 irqmask;
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static struct clock_event_device clkevt;
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/*
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* The ST_CRTR is updated asynchronously to the master clock ... but
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* the updates as seen by the CPU don't seem to be strictly monotonic.
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* Waiting until we read the same value twice avoids glitching.
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*/
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static inline unsigned long read_CRTR(void)
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{
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unsigned long x1, x2;
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x1 = at91_sys_read(AT91_ST_CRTR);
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do {
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x2 = at91_sys_read(AT91_ST_CRTR);
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if (x1 == x2)
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break;
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x1 = x2;
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} while (1);
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return x1;
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}
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
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{
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u32 sr = at91_sys_read(AT91_ST_SR) & irqmask;
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/* simulate "oneshot" timer with alarm */
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if (sr & AT91_ST_ALMS) {
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clkevt.event_handler(&clkevt);
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return IRQ_HANDLED;
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}
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/* periodic mode should handle delayed ticks */
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if (sr & AT91_ST_PITS) {
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u32 crtr = read_CRTR();
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while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) {
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last_crtr += LATCH;
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clkevt.event_handler(&clkevt);
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}
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return IRQ_HANDLED;
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}
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/* this irq is shared ... */
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return IRQ_NONE;
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}
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static struct irqaction at91rm9200_timer_irq = {
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.name = "at91_tick",
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.flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = at91rm9200_timer_interrupt
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};
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static cycle_t read_clk32k(struct clocksource *cs)
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{
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return read_CRTR();
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}
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static struct clocksource clk32k = {
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.name = "32k_counter",
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.rating = 150,
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.read = read_clk32k,
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.mask = CLOCKSOURCE_MASK(20),
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.shift = 10,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void
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clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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/* Disable and flush pending timer interrupts */
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at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
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(void) at91_sys_read(AT91_ST_SR);
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last_crtr = read_CRTR();
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* PIT for periodic irqs; fixed rate of 1/HZ */
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irqmask = AT91_ST_PITS;
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at91_sys_write(AT91_ST_PIMR, LATCH);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* ALM for oneshot irqs, set by next_event()
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* before 32 seconds have passed
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*/
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irqmask = AT91_ST_ALMS;
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at91_sys_write(AT91_ST_RTAR, last_crtr);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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irqmask = 0;
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break;
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}
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at91_sys_write(AT91_ST_IER, irqmask);
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}
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static int
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clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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unsigned long flags;
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u32 alm;
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int status = 0;
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BUG_ON(delta < 2);
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/* Use "raw" primitives so we behave correctly on RT kernels. */
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raw_local_irq_save(flags);
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/*
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* According to Thomas Gleixner irqs are already disabled here. Simply
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* removing raw_local_irq_save above (and the matching
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* raw_local_irq_restore) was not accepted. See
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* http://thread.gmane.org/gmane.linux.ports.arm.kernel/41174
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* So for now (2008-11-20) just warn once if irqs were not disabled ...
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*/
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WARN_ON_ONCE(!raw_irqs_disabled_flags(flags));
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/* The alarm IRQ uses absolute time (now+delta), not the relative
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* time (delta) in our calling convention. Like all clockevents
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* using such "match" hardware, we have a race to defend against.
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*
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* Our defense here is to have set up the clockevent device so the
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* delta is at least two. That way we never end up writing RTAR
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* with the value then held in CRTR ... which would mean the match
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* wouldn't trigger until 32 seconds later, after CRTR wraps.
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*/
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alm = read_CRTR();
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/* Cancel any pending alarm; flush any pending IRQ */
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at91_sys_write(AT91_ST_RTAR, alm);
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(void) at91_sys_read(AT91_ST_SR);
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/* Schedule alarm by writing RTAR. */
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alm += delta;
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at91_sys_write(AT91_ST_RTAR, alm);
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raw_local_irq_restore(flags);
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return status;
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}
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static struct clock_event_device clkevt = {
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.name = "at91_tick",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 150,
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.set_next_event = clkevt32k_next_event,
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.set_mode = clkevt32k_mode,
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};
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/*
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* ST (system timer) module supports both clockevents and clocksource.
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*/
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void __init at91rm9200_timer_init(void)
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{
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/* Disable all timer interrupts, and clear any pending ones */
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at91_sys_write(AT91_ST_IDR,
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AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
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(void) at91_sys_read(AT91_ST_SR);
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/* Make IRQs happen for the system timer */
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setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
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/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
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* directly for the clocksource and all clockevents, after adjusting
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* its prescaler from the 1 Hz default.
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*/
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at91_sys_write(AT91_ST_RTMR, 1);
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/* Setup timer clockevent, with minimum of two ticks (important!!) */
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clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
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clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
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clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
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clkevt.cpumask = cpumask_of(0);
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clockevents_register_device(&clkevt);
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/* register clocksource */
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clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift);
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clocksource_register(&clk32k);
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}
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struct sys_timer at91rm9200_timer = {
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.init = at91rm9200_timer_init,
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};
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