575 lines
14 KiB
Plaintext
575 lines
14 KiB
Plaintext
/*
|
|
* MPC8568E MDS Device Tree Source
|
|
*
|
|
* Copyright 2007, 2008 Freescale Semiconductor Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
model = "MPC8568EMDS";
|
|
compatible = "MPC8568EMDS", "MPC85xxMDS";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
ethernet0 = &enet0;
|
|
ethernet1 = &enet1;
|
|
ethernet2 = &enet2;
|
|
ethernet3 = &enet3;
|
|
serial0 = &serial0;
|
|
serial1 = &serial1;
|
|
pci0 = &pci0;
|
|
pci1 = &pci1;
|
|
rapidio0 = &rio0;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
PowerPC,8568@0 {
|
|
device_type = "cpu";
|
|
reg = <0x0>;
|
|
d-cache-line-size = <32>; // 32 bytes
|
|
i-cache-line-size = <32>; // 32 bytes
|
|
d-cache-size = <0x8000>; // L1, 32K
|
|
i-cache-size = <0x8000>; // L1, 32K
|
|
timebase-frequency = <0>;
|
|
bus-frequency = <0>;
|
|
clock-frequency = <0>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x0 0x10000000>;
|
|
};
|
|
|
|
bcsr@f8000000 {
|
|
compatible = "fsl,mpc8568mds-bcsr";
|
|
reg = <0xf8000000 0x8000>;
|
|
};
|
|
|
|
soc8568@e0000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "simple-bus";
|
|
ranges = <0x0 0xe0000000 0x100000>;
|
|
bus-frequency = <0>;
|
|
|
|
ecm-law@0 {
|
|
compatible = "fsl,ecm-law";
|
|
reg = <0x0 0x1000>;
|
|
fsl,num-laws = <10>;
|
|
};
|
|
|
|
ecm@1000 {
|
|
compatible = "fsl,mpc8568-ecm", "fsl,ecm";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <17 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
memory-controller@2000 {
|
|
compatible = "fsl,8568-memory-controller";
|
|
reg = <0x2000 0x1000>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <18 2>;
|
|
};
|
|
|
|
L2: l2-cache-controller@20000 {
|
|
compatible = "fsl,8568-l2-cache-controller";
|
|
reg = <0x20000 0x1000>;
|
|
cache-line-size = <32>; // 32 bytes
|
|
cache-size = <0x80000>; // L2, 512K
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <16 2>;
|
|
};
|
|
|
|
i2c@3000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
compatible = "fsl-i2c";
|
|
reg = <0x3000 0x100>;
|
|
interrupts = <43 2>;
|
|
interrupt-parent = <&mpic>;
|
|
dfsrr;
|
|
|
|
rtc@68 {
|
|
compatible = "dallas,ds1374";
|
|
reg = <0x68>;
|
|
};
|
|
};
|
|
|
|
i2c@3100 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <1>;
|
|
compatible = "fsl-i2c";
|
|
reg = <0x3100 0x100>;
|
|
interrupts = <43 2>;
|
|
interrupt-parent = <&mpic>;
|
|
dfsrr;
|
|
};
|
|
|
|
dma@21300 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
|
|
reg = <0x21300 0x4>;
|
|
ranges = <0x0 0x21100 0x200>;
|
|
cell-index = <0>;
|
|
dma-channel@0 {
|
|
compatible = "fsl,mpc8568-dma-channel",
|
|
"fsl,eloplus-dma-channel";
|
|
reg = <0x0 0x80>;
|
|
cell-index = <0>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <20 2>;
|
|
};
|
|
dma-channel@80 {
|
|
compatible = "fsl,mpc8568-dma-channel",
|
|
"fsl,eloplus-dma-channel";
|
|
reg = <0x80 0x80>;
|
|
cell-index = <1>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <21 2>;
|
|
};
|
|
dma-channel@100 {
|
|
compatible = "fsl,mpc8568-dma-channel",
|
|
"fsl,eloplus-dma-channel";
|
|
reg = <0x100 0x80>;
|
|
cell-index = <2>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <22 2>;
|
|
};
|
|
dma-channel@180 {
|
|
compatible = "fsl,mpc8568-dma-channel",
|
|
"fsl,eloplus-dma-channel";
|
|
reg = <0x180 0x80>;
|
|
cell-index = <3>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <23 2>;
|
|
};
|
|
};
|
|
|
|
enet0: ethernet@24000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
cell-index = <0>;
|
|
device_type = "network";
|
|
model = "eTSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x24000 0x1000>;
|
|
ranges = <0x0 0x24000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <29 2 30 2 34 2>;
|
|
interrupt-parent = <&mpic>;
|
|
tbi-handle = <&tbi0>;
|
|
phy-handle = <&phy2>;
|
|
|
|
mdio@520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-mdio";
|
|
reg = <0x520 0x20>;
|
|
|
|
phy0: ethernet-phy@7 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <1 1>;
|
|
reg = <0x7>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
phy1: ethernet-phy@1 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <2 1>;
|
|
reg = <0x1>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
phy2: ethernet-phy@2 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <1 1>;
|
|
reg = <0x2>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
phy3: ethernet-phy@3 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <2 1>;
|
|
reg = <0x3>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
tbi0: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
};
|
|
|
|
enet1: ethernet@25000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
cell-index = <1>;
|
|
device_type = "network";
|
|
model = "eTSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x25000 0x1000>;
|
|
ranges = <0x0 0x25000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <35 2 36 2 40 2>;
|
|
interrupt-parent = <&mpic>;
|
|
tbi-handle = <&tbi1>;
|
|
phy-handle = <&phy3>;
|
|
|
|
mdio@520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-tbi";
|
|
reg = <0x520 0x20>;
|
|
|
|
tbi1: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
};
|
|
|
|
serial0: serial@4500 {
|
|
cell-index = <0>;
|
|
device_type = "serial";
|
|
compatible = "ns16550";
|
|
reg = <0x4500 0x100>;
|
|
clock-frequency = <0>;
|
|
interrupts = <42 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
global-utilities@e0000 { //global utilities block
|
|
compatible = "fsl,mpc8548-guts";
|
|
reg = <0xe0000 0x1000>;
|
|
fsl,has-rstcr;
|
|
};
|
|
|
|
serial1: serial@4600 {
|
|
cell-index = <1>;
|
|
device_type = "serial";
|
|
compatible = "ns16550";
|
|
reg = <0x4600 0x100>;
|
|
clock-frequency = <0>;
|
|
interrupts = <42 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
crypto@30000 {
|
|
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
|
reg = <0x30000 0x10000>;
|
|
interrupts = <45 2>;
|
|
interrupt-parent = <&mpic>;
|
|
fsl,num-channels = <4>;
|
|
fsl,channel-fifo-len = <24>;
|
|
fsl,exec-units-mask = <0xfe>;
|
|
fsl,descriptor-types-mask = <0x12b0ebf>;
|
|
};
|
|
|
|
mpic: pic@40000 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x40000 0x40000>;
|
|
compatible = "chrp,open-pic";
|
|
device_type = "open-pic";
|
|
};
|
|
|
|
msi@41600 {
|
|
compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
|
|
reg = <0x41600 0x80>;
|
|
msi-available-ranges = <0 0x100>;
|
|
interrupts = <
|
|
0xe0 0
|
|
0xe1 0
|
|
0xe2 0
|
|
0xe3 0
|
|
0xe4 0
|
|
0xe5 0
|
|
0xe6 0
|
|
0xe7 0>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
par_io@e0100 {
|
|
reg = <0xe0100 0x100>;
|
|
device_type = "par_io";
|
|
num-ports = <7>;
|
|
|
|
pio1: ucc_pin@01 {
|
|
pio-map = <
|
|
/* port pin dir open_drain assignment has_irq */
|
|
0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
|
|
0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
|
|
0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
|
|
0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
|
|
0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
|
|
0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
|
|
0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
|
|
0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
|
|
0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
|
|
0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
|
|
0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
|
|
0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
|
|
0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
|
|
0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
|
|
0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
|
|
0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
|
|
0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
|
|
0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
|
|
0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
|
|
0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
|
|
0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
|
|
0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
|
|
0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
|
|
};
|
|
|
|
pio2: ucc_pin@02 {
|
|
pio-map = <
|
|
/* port pin dir open_drain assignment has_irq */
|
|
0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
|
|
0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
|
|
0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
|
|
0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
|
|
0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
|
|
0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
|
|
0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
|
|
0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
|
|
0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
|
|
0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
|
|
0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
|
|
0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
|
|
0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
|
|
0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
|
|
0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
|
|
0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
|
|
0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
|
|
0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
|
|
0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
|
|
0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
|
|
0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
|
|
0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
|
|
0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
|
|
0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
|
|
0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
|
|
};
|
|
};
|
|
};
|
|
|
|
qe@e0080000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "qe";
|
|
compatible = "fsl,qe";
|
|
ranges = <0x0 0xe0080000 0x40000>;
|
|
reg = <0xe0080000 0x480>;
|
|
brg-frequency = <0>;
|
|
bus-frequency = <396000000>;
|
|
fsl,qe-num-riscs = <2>;
|
|
fsl,qe-num-snums = <28>;
|
|
|
|
muram@10000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
|
ranges = <0x0 0x10000 0x10000>;
|
|
|
|
data-only@0 {
|
|
compatible = "fsl,qe-muram-data",
|
|
"fsl,cpm-muram-data";
|
|
reg = <0x0 0x10000>;
|
|
};
|
|
};
|
|
|
|
spi@4c0 {
|
|
cell-index = <0>;
|
|
compatible = "fsl,spi";
|
|
reg = <0x4c0 0x40>;
|
|
interrupts = <2>;
|
|
interrupt-parent = <&qeic>;
|
|
mode = "cpu";
|
|
};
|
|
|
|
spi@500 {
|
|
cell-index = <1>;
|
|
compatible = "fsl,spi";
|
|
reg = <0x500 0x40>;
|
|
interrupts = <1>;
|
|
interrupt-parent = <&qeic>;
|
|
mode = "cpu";
|
|
};
|
|
|
|
enet2: ucc@2000 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <1>;
|
|
reg = <0x2000 0x200>;
|
|
interrupts = <32>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "none";
|
|
tx-clock-name = "clk16";
|
|
pio-handle = <&pio1>;
|
|
phy-handle = <&phy0>;
|
|
phy-connection-type = "rgmii-id";
|
|
};
|
|
|
|
enet3: ucc@3000 {
|
|
device_type = "network";
|
|
compatible = "ucc_geth";
|
|
cell-index = <2>;
|
|
reg = <0x3000 0x200>;
|
|
interrupts = <33>;
|
|
interrupt-parent = <&qeic>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
rx-clock-name = "none";
|
|
tx-clock-name = "clk16";
|
|
pio-handle = <&pio2>;
|
|
phy-handle = <&phy1>;
|
|
phy-connection-type = "rgmii-id";
|
|
};
|
|
|
|
mdio@2120 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x2120 0x18>;
|
|
compatible = "fsl,ucc-mdio";
|
|
|
|
/* These are the same PHYs as on
|
|
* gianfar's MDIO bus */
|
|
qe_phy0: ethernet-phy@07 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <1 1>;
|
|
reg = <0x7>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
qe_phy1: ethernet-phy@01 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <2 1>;
|
|
reg = <0x1>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
qe_phy2: ethernet-phy@02 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <1 1>;
|
|
reg = <0x2>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
qe_phy3: ethernet-phy@03 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <2 1>;
|
|
reg = <0x3>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
};
|
|
|
|
qeic: interrupt-controller@80 {
|
|
interrupt-controller;
|
|
compatible = "fsl,qe-ic";
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x80 0x80>;
|
|
big-endian;
|
|
interrupts = <46 2 46 2>; //high:30 low:30
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
};
|
|
|
|
pci0: pci@e0008000 {
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x12 AD18 */
|
|
0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
|
|
0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
|
|
0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
|
|
0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
|
|
|
|
/* IDSEL 0x13 AD19 */
|
|
0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
|
|
0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
|
|
0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
|
|
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <24 2>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
|
0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
|
|
clock-frequency = <66666666>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xe0008000 0x1000>;
|
|
compatible = "fsl,mpc8540-pci";
|
|
device_type = "pci";
|
|
};
|
|
|
|
/* PCI Express */
|
|
pci1: pcie@e000a000 {
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
|
|
/* IDSEL 0x0 (PEX) */
|
|
00000 0x0 0x0 0x1 &mpic 0x0 0x1
|
|
00000 0x0 0x0 0x2 &mpic 0x1 0x1
|
|
00000 0x0 0x0 0x3 &mpic 0x2 0x1
|
|
00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
|
|
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <26 2>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
|
0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
|
|
clock-frequency = <33333333>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xe000a000 0x1000>;
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xa0000000
|
|
0x2000000 0x0 0xa0000000
|
|
0x0 0x10000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x800000>;
|
|
};
|
|
};
|
|
|
|
rio0: rapidio@e00c00000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
|
|
reg = <0xe00c0000 0x20000>;
|
|
ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
|
|
interrupts = <48 2 /* error */
|
|
49 2 /* bell_outb */
|
|
50 2 /* bell_inb */
|
|
53 2 /* msg1_tx */
|
|
54 2 /* msg1_rx */
|
|
55 2 /* msg2_tx */
|
|
56 2 /* msg2_rx */>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
};
|