85 lines
1.7 KiB
C
85 lines
1.7 KiB
C
/*
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* Common Blackfin memory map
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __BFIN_MEM_MAP_H__
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#define __BFIN_MEM_MAP_H__
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#include <mach/mem_map.h>
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/* Every Blackfin so far has MMRs like this */
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#ifndef COREMMR_BASE
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# define COREMMR_BASE 0xFFE00000
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#endif
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#ifndef SYSMMR_BASE
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# define SYSMMR_BASE 0xFFC00000
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#endif
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/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
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#ifndef L1_SCRATCH_START
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# define L1_SCRATCH_START 0xFFB00000
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# define L1_SCRATCH_LENGTH 0x1000
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#endif
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/* Most parts lack on-chip L2 SRAM */
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#ifndef L2_START
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# define L2_START 0
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# define L2_LENGTH 0
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#endif
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/* Most parts lack on-chip L1 ROM */
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#ifndef L1_ROM_START
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# define L1_ROM_START 0
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# define L1_ROM_LENGTH 0
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#endif
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/* Allow wonky SMP ports to override this */
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#ifndef GET_PDA_SAFE
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# define GET_PDA_SAFE(preg) \
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preg.l = _cpu_pda; \
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preg.h = _cpu_pda;
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# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
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# ifndef __ASSEMBLY__
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static inline unsigned long get_l1_scratch_start_cpu(int cpu)
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{
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return L1_SCRATCH_START;
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}
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static inline unsigned long get_l1_code_start_cpu(int cpu)
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{
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return L1_CODE_START;
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}
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static inline unsigned long get_l1_data_a_start_cpu(int cpu)
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{
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return L1_DATA_A_START;
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}
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static inline unsigned long get_l1_data_b_start_cpu(int cpu)
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{
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return L1_DATA_B_START;
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}
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static inline unsigned long get_l1_scratch_start(void)
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{
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return get_l1_scratch_start_cpu(0);
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}
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static inline unsigned long get_l1_code_start(void)
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{
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return get_l1_code_start_cpu(0);
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}
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static inline unsigned long get_l1_data_a_start(void)
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{
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return get_l1_data_a_start_cpu(0);
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}
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static inline unsigned long get_l1_data_b_start(void)
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{
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return get_l1_data_b_start_cpu(0);
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}
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# endif /* __ASSEMBLY__ */
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#endif /* !GET_PDA_SAFE */
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#endif
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