204 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			204 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  linux/arch/arm/mach-pxa/irq.c
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|  *
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|  *  Generic PXA IRQ handling
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|  *
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|  *  Author:	Nicolas Pitre
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|  *  Created:	Jun 15, 2001
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|  *  Copyright:	MontaVista Software Inc.
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|  *
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|  *  This program is free software; you can redistribute it and/or modify
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|  *  it under the terms of the GNU General Public License version 2 as
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|  *  published by the Free Software Foundation.
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|  */
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| 
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| #include <linux/init.h>
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| #include <linux/module.h>
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| #include <linux/interrupt.h>
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| #include <linux/sysdev.h>
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| 
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| #include <mach/hardware.h>
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| #include <asm/irq.h>
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| #include <asm/mach/irq.h>
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| #include <mach/gpio.h>
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| #include <mach/regs-intc.h>
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| 
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| #include "generic.h"
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| 
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| #define MAX_INTERNAL_IRQS	128
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| 
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| #define IRQ_BIT(n)	(((n) - PXA_IRQ(0)) & 0x1f)
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| #define _ICMR(n)	(*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
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| #define _ICLR(n)	(*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
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| 
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| /*
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|  * This is for peripheral IRQs internal to the PXA chip.
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|  */
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| 
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| static int pxa_internal_irq_nr;
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| 
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| static void pxa_mask_irq(unsigned int irq)
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| {
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| 	_ICMR(irq) &= ~(1 << IRQ_BIT(irq));
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| }
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| 
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| static void pxa_unmask_irq(unsigned int irq)
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| {
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| 	_ICMR(irq) |= 1 << IRQ_BIT(irq);
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| }
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| 
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| static struct irq_chip pxa_internal_irq_chip = {
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| 	.name		= "SC",
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| 	.ack		= pxa_mask_irq,
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| 	.mask		= pxa_mask_irq,
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| 	.unmask		= pxa_unmask_irq,
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| };
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| 
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| /*
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|  * GPIO IRQs for GPIO 0 and 1
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|  */
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| static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type)
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| {
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| 	int gpio = irq - IRQ_GPIO0;
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| 
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| 	if (__gpio_is_occupied(gpio)) {
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| 		pr_err("%s failed: GPIO is configured\n", __func__);
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| 		return -EINVAL;
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| 	}
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| 
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| 	if (type & IRQ_TYPE_EDGE_RISING)
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| 		GRER0 |= GPIO_bit(gpio);
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| 	else
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| 		GRER0 &= ~GPIO_bit(gpio);
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| 
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| 	if (type & IRQ_TYPE_EDGE_FALLING)
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| 		GFER0 |= GPIO_bit(gpio);
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| 	else
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| 		GFER0 &= ~GPIO_bit(gpio);
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| 
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| 	return 0;
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| }
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| 
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| static void pxa_ack_low_gpio(unsigned int irq)
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| {
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| 	GEDR0 = (1 << (irq - IRQ_GPIO0));
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| }
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| 
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| static void pxa_mask_low_gpio(unsigned int irq)
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| {
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| 	ICMR &= ~(1 << (irq - PXA_IRQ(0)));
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| }
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| 
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| static void pxa_unmask_low_gpio(unsigned int irq)
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| {
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| 	ICMR |= 1 << (irq - PXA_IRQ(0));
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| }
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| 
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| static struct irq_chip pxa_low_gpio_chip = {
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| 	.name		= "GPIO-l",
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| 	.ack		= pxa_ack_low_gpio,
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| 	.mask		= pxa_mask_low_gpio,
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| 	.unmask		= pxa_unmask_low_gpio,
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| 	.set_type	= pxa_set_low_gpio_type,
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| };
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| 
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| static void __init pxa_init_low_gpio_irq(set_wake_t fn)
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| {
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| 	int irq;
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| 
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| 	/* clear edge detection on GPIO 0 and 1 */
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| 	GFER0 &= ~0x3;
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| 	GRER0 &= ~0x3;
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| 	GEDR0 = 0x3;
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| 
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| 	for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
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| 		set_irq_chip(irq, &pxa_low_gpio_chip);
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| 		set_irq_handler(irq, handle_edge_irq);
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| 		set_irq_flags(irq, IRQF_VALID);
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| 	}
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| 
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| 	pxa_low_gpio_chip.set_wake = fn;
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| }
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| 
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| void __init pxa_init_irq(int irq_nr, set_wake_t fn)
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| {
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| 	int irq, i;
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| 
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| 	BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
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| 
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| 	pxa_internal_irq_nr = irq_nr;
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| 
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| 	for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
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| 		_ICMR(irq) = 0;	/* disable all IRQs */
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| 		_ICLR(irq) = 0;	/* all IRQs are IRQ, not FIQ */
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| 	}
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| 
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| 	/* initialize interrupt priority */
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| 	if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
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| 		for (i = 0; i < irq_nr; i++)
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| 			IPR(i) = i | (1 << 31);
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| 	}
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| 
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| 	/* only unmasked interrupts kick us out of idle */
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| 	ICCR = 1;
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| 
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| 	for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
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| 		set_irq_chip(irq, &pxa_internal_irq_chip);
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| 		set_irq_handler(irq, handle_level_irq);
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| 		set_irq_flags(irq, IRQF_VALID);
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| 	}
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| 
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| 	pxa_internal_irq_chip.set_wake = fn;
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| 	pxa_init_low_gpio_irq(fn);
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| }
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| 
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| #ifdef CONFIG_PM
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| static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
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| static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
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| 
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| static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
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| {
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| 	int i, irq = PXA_IRQ(0);
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| 
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| 	for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
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| 		saved_icmr[i] = _ICMR(irq);
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| 		_ICMR(irq) = 0;
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| 	}
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| 	for (i = 0; i < pxa_internal_irq_nr; i++)
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| 		saved_ipr[i] = IPR(i);
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| 
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| 	return 0;
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| }
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| 
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| static int pxa_irq_resume(struct sys_device *dev)
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| {
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| 	int i, irq = PXA_IRQ(0);
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| 
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| 	for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
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| 		_ICMR(irq) = saved_icmr[i];
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| 		_ICLR(irq) = 0;
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| 	}
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| 	for (i = 0; i < pxa_internal_irq_nr; i++)
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| 		IPR(i) = saved_ipr[i];
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| 
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| 	ICCR = 1;
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| 	return 0;
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| }
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| #else
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| #define pxa_irq_suspend		NULL
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| #define pxa_irq_resume		NULL
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| #endif
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| 
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| struct sysdev_class pxa_irq_sysclass = {
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| 	.name		= "irq",
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| 	.suspend	= pxa_irq_suspend,
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| 	.resume		= pxa_irq_resume,
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| };
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| 
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| static int __init pxa_irq_init(void)
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| {
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| 	return sysdev_class_register(&pxa_irq_sysclass);
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| }
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| 
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| core_initcall(pxa_irq_init);
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