359 lines
7.3 KiB
ArmAsm
359 lines
7.3 KiB
ArmAsm
/*
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* This file contains low-level cache management functions
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* used for sleep and CPU speed changes on Apple machines.
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* (In fact the only thing that is Apple-specific is that we assume
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* that we can read from ROM at physical address 0xfff00000.)
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*
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* Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and
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* Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/cputable.h>
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/*
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* Flush and disable all data caches (dL1, L2, L3). This is used
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* when going to sleep, when doing a PMU based cpufreq transition,
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* or when "offlining" a CPU on SMP machines. This code is over
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* paranoid, but I've had enough issues with various CPU revs and
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* bugs that I decided it was worth beeing over cautious
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*/
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_GLOBAL(flush_disable_caches)
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#ifndef CONFIG_6xx
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blr
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#else
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BEGIN_FTR_SECTION
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b flush_disable_745x
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END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
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BEGIN_FTR_SECTION
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b flush_disable_75x
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END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
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b __flush_disable_L1
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/* This is the code for G3 and 74[01]0 */
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flush_disable_75x:
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mflr r10
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/* Turn off EE and DR in MSR */
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mfmsr r11
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rlwinm r0,r11,0,~MSR_EE
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rlwinm r0,r0,0,~MSR_DR
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sync
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mtmsr r0
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isync
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/* Stop DST streams */
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BEGIN_FTR_SECTION
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DSSALL
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sync
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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/* Stop DPM */
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mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
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rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
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sync
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mtspr SPRN_HID0,r4 /* Disable DPM */
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sync
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/* Disp-flush L1. We have a weird problem here that I never
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* totally figured out. On 750FX, using the ROM for the flush
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* results in a non-working flush. We use that workaround for
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* now until I finally understand what's going on. --BenH
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*/
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/* ROM base by default */
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lis r4,0xfff0
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mfpvr r3
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srwi r3,r3,16
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cmplwi cr0,r3,0x7000
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bne+ 1f
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/* RAM base on 750FX */
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li r4,0
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1: li r4,0x4000
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mtctr r4
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1: lwz r0,0(r4)
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addi r4,r4,32
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bdnz 1b
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sync
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isync
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/* Disable / invalidate / enable L1 data */
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mfspr r3,SPRN_HID0
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rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
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mtspr SPRN_HID0,r3
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sync
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isync
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ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
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sync
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isync
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mtspr SPRN_HID0,r3
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xori r3,r3,(HID0_DCI|HID0_ICFI)
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mtspr SPRN_HID0,r3
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sync
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/* Get the current enable bit of the L2CR into r4 */
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mfspr r5,SPRN_L2CR
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/* Set to data-only (pre-745x bit) */
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oris r3,r5,L2CR_L2DO@h
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b 2f
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/* When disabling L2, code must be in L1 */
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.balign 32
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1: mtspr SPRN_L2CR,r3
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3: sync
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isync
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b 1f
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2: b 3f
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3: sync
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isync
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b 1b
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1: /* disp-flush L2. The interesting thing here is that the L2 can be
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* up to 2Mb ... so using the ROM, we'll end up wrapping back to memory
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* but that is probbaly fine. We disp-flush over 4Mb to be safe
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*/
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lis r4,2
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mtctr r4
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lis r4,0xfff0
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1: lwz r0,0(r4)
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addi r4,r4,32
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bdnz 1b
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sync
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isync
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lis r4,2
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mtctr r4
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lis r4,0xfff0
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1: dcbf 0,r4
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addi r4,r4,32
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bdnz 1b
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sync
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isync
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/* now disable L2 */
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rlwinm r5,r5,0,~L2CR_L2E
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b 2f
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/* When disabling L2, code must be in L1 */
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.balign 32
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1: mtspr SPRN_L2CR,r5
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3: sync
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isync
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b 1f
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2: b 3f
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3: sync
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isync
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b 1b
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1: sync
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isync
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/* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
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oris r4,r5,L2CR_L2I@h
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mtspr SPRN_L2CR,r4
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sync
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isync
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/* Wait for the invalidation to complete */
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1: mfspr r3,SPRN_L2CR
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rlwinm. r0,r3,0,31,31
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bne 1b
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/* Clear L2I */
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xoris r4,r4,L2CR_L2I@h
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sync
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mtspr SPRN_L2CR,r4
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sync
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/* now disable the L1 data cache */
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mfspr r0,SPRN_HID0
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rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
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mtspr SPRN_HID0,r0
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sync
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isync
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/* Restore HID0[DPM] to whatever it was before */
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sync
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mfspr r0,SPRN_HID0
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rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
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mtspr SPRN_HID0,r0
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sync
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/* restore DR and EE */
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sync
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mtmsr r11
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isync
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mtlr r10
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blr
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/* This code is for 745x processors */
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flush_disable_745x:
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/* Turn off EE and DR in MSR */
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mfmsr r11
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rlwinm r0,r11,0,~MSR_EE
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rlwinm r0,r0,0,~MSR_DR
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sync
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mtmsr r0
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isync
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/* Stop prefetch streams */
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DSSALL
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sync
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/* Disable L2 prefetching */
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mfspr r0,SPRN_MSSCR0
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rlwinm r0,r0,0,0,29
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mtspr SPRN_MSSCR0,r0
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sync
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isync
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lis r4,0
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dcbf 0,r4
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dcbf 0,r4
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dcbf 0,r4
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dcbf 0,r4
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dcbf 0,r4
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dcbf 0,r4
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dcbf 0,r4
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dcbf 0,r4
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/* Due to a bug with the HW flush on some CPU revs, we occasionally
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* experience data corruption. I'm adding a displacement flush along
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* with a dcbf loop over a few Mb to "help". The problem isn't totally
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* fixed by this in theory, but at least, in practice, I couldn't reproduce
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* it even with a big hammer...
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*/
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lis r4,0x0002
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mtctr r4
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li r4,0
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1:
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lwz r0,0(r4)
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addi r4,r4,32 /* Go to start of next cache line */
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bdnz 1b
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isync
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/* Now, flush the first 4MB of memory */
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lis r4,0x0002
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mtctr r4
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li r4,0
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sync
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1:
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dcbf 0,r4
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addi r4,r4,32 /* Go to start of next cache line */
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bdnz 1b
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/* Flush and disable the L1 data cache */
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mfspr r6,SPRN_LDSTCR
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lis r3,0xfff0 /* read from ROM for displacement flush */
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li r4,0xfe /* start with only way 0 unlocked */
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li r5,128 /* 128 lines in each way */
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1: mtctr r5
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rlwimi r6,r4,0,24,31
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mtspr SPRN_LDSTCR,r6
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sync
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isync
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2: lwz r0,0(r3) /* touch each cache line */
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addi r3,r3,32
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bdnz 2b
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rlwinm r4,r4,1,24,30 /* move on to the next way */
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ori r4,r4,1
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cmpwi r4,0xff /* all done? */
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bne 1b
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/* now unlock the L1 data cache */
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li r4,0
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rlwimi r6,r4,0,24,31
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sync
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mtspr SPRN_LDSTCR,r6
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sync
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isync
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/* Flush the L2 cache using the hardware assist */
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mfspr r3,SPRN_L2CR
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cmpwi r3,0 /* check if it is enabled first */
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bge 4f
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oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h
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b 2f
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/* When disabling/locking L2, code must be in L1 */
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.balign 32
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1: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
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3: sync
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isync
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b 1f
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2: b 3f
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3: sync
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isync
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b 1b
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1: sync
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isync
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ori r0,r3,L2CR_L2HWF_745x
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sync
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mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
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3: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
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andi. r0,r0,L2CR_L2HWF_745x
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bne 3b
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sync
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rlwinm r3,r3,0,~L2CR_L2E
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b 2f
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/* When disabling L2, code must be in L1 */
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.balign 32
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1: mtspr SPRN_L2CR,r3 /* disable the L2 cache */
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3: sync
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isync
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b 1f
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2: b 3f
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3: sync
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isync
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b 1b
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1: sync
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isync
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oris r4,r3,L2CR_L2I@h
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mtspr SPRN_L2CR,r4
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sync
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isync
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1: mfspr r4,SPRN_L2CR
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andis. r0,r4,L2CR_L2I@h
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bne 1b
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sync
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BEGIN_FTR_SECTION
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/* Flush the L3 cache using the hardware assist */
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4: mfspr r3,SPRN_L3CR
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cmpwi r3,0 /* check if it is enabled */
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bge 6f
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oris r0,r3,L3CR_L3IO@h
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ori r0,r0,L3CR_L3DO
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sync
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mtspr SPRN_L3CR,r0 /* lock the L3 cache */
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sync
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isync
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ori r0,r0,L3CR_L3HWF
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sync
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mtspr SPRN_L3CR,r0 /* set the hardware flush bit */
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5: mfspr r0,SPRN_L3CR /* wait for it to go to zero */
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andi. r0,r0,L3CR_L3HWF
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bne 5b
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rlwinm r3,r3,0,~L3CR_L3E
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sync
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mtspr SPRN_L3CR,r3 /* disable the L3 cache */
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sync
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ori r4,r3,L3CR_L3I
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mtspr SPRN_L3CR,r4
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1: mfspr r4,SPRN_L3CR
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andi. r0,r4,L3CR_L3I
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bne 1b
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sync
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END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
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6: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */
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rlwinm r0,r0,0,~HID0_DCE
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mtspr SPRN_HID0,r0
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sync
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isync
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mtmsr r11 /* restore DR and EE */
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isync
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blr
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#endif /* CONFIG_6xx */
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