diff --git a/arch/arm/configs/htcleo_defconfig b/arch/arm/configs/htcleo_defconfig index 5cfd40dd..5f799b34 100644 --- a/arch/arm/configs/htcleo_defconfig +++ b/arch/arm/configs/htcleo_defconfig @@ -1407,8 +1407,6 @@ CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_MSM=y CONFIG_FB_MSM_LCDC=y # CONFIG_FB_MSM_TVOUT is not set -# CONFIG_GPU_MSM_KGSL is not set -# CONFIG_GPU_MSM_KGSL_MMU is not set # CONFIG_MSM_HDMI is not set CONFIG_FB_MSM_LOGO=y # CONFIG_BACKLIGHT_LCD_SUPPORT is not set diff --git a/drivers/video/msm/Kconfig b/drivers/video/msm/Kconfig index 9ce28950..c6610107 100644 --- a/drivers/video/msm/Kconfig +++ b/drivers/video/msm/Kconfig @@ -55,22 +55,6 @@ config MSM_ROTATOR_USE_IMEM block. Or some systems may want the iMem to be dedicated to a different function. -config GPU_MSM_KGSL_MMU - bool "Turn on MMU for graphics driver " - depends on GPU_MSM_KGSL && MMU - default n - help - If enabled, the GPU driver will allocate memory from vmalloc - and enable the use of GPU MMU, instead of using pmem. - -config MSM_KGSL_PER_FD_PAGETABLE - bool "Turn on per-fd pagetable for MMU of graphics driver " - depends on MSM_KGSL_MMU && MMU - default n - help - If enabled, the MMU unit of GPU driver will use seperate - pagetables for each file descriptor - config MSM_HDMI bool "Support for HDMI in QCT platform" depends on MSM_MDP31 diff --git a/drivers/video/msm/Makefile b/drivers/video/msm/Makefile index a013cd57..60380b65 100644 --- a/drivers/video/msm/Makefile +++ b/drivers/video/msm/Makefile @@ -33,5 +33,3 @@ obj-y += mddi_client_novb9f6_5582.o obj-$(CONFIG_FB_MSM_LCDC) += mdp_lcdc.o obj-$(CONFIG_FB_MSM_TVOUT) += tvenc.o tvfb.o -# Yamato GL driver -obj-$(CONFIG_GPU_MSM_KGSL) += gpu/kgsl/ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IAB b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IAB deleted file mode 100755 index e8d88646..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IAB and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IAD b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IAD deleted file mode 100755 index 09e28dae..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IAD and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IMB b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IMB deleted file mode 100755 index ae098b3b..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IMB and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IMD b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IMD deleted file mode 100755 index 89d25dd2..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.IMD and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PFI b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PFI deleted file mode 100755 index 4e77fed0..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PFI and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PO b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PO deleted file mode 100755 index 30a745ff..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PO and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PR b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PR deleted file mode 100755 index 7a4ae3e4..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PR and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PRI b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PRI deleted file mode 100755 index 65dfe059..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PRI and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PS b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PS deleted file mode 100755 index 0d0fa1d5..00000000 Binary files a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.PS and /dev/null differ diff --git a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.SearchResults b/drivers/video/msm/gpu/KGSL_SI/Untitled Project.SearchResults deleted file mode 100755 index 71943fcd..00000000 --- a/drivers/video/msm/gpu/KGSL_SI/Untitled Project.SearchResults +++ /dev/null @@ -1,12 +0,0 @@ ----- CONFIG_MSM_KGSL_MMU Matches (11 in 6 files) ---- -kgsl.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl_device.h (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl_log.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl_log.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl_mmu.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifndef CONFIG_MSM_KGSL_MMU -kgsl_mmu.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl_mmu.h (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl_yamato.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU -kgsl_yamato.c (\\jupiter\xinwang\hd2\kernel\msm8x50\20120427A\dorimanx-Dorimanx-HD2-2.6.32.X-69084da_hwa_mix\drivers\video\msm\gpu\kgsl):#ifdef CONFIG_MSM_KGSL_MMU diff --git a/drivers/video/msm/gpu/kgsl/Makefile b/drivers/video/msm/gpu/kgsl/Makefile deleted file mode 100644 index 0290b50c..00000000 --- a/drivers/video/msm/gpu/kgsl/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -msm_kgsl-objs = \ - kgsl_drawctxt.o \ - kgsl_cmdstream.o \ - kgsl.o \ - kgsl_log.o \ - kgsl_mmu.o \ - kgsl_ringbuffer.o \ - kgsl_sharedmem.o \ - kgsl_yamato.o - -obj-$(CONFIG_GPU_MSM_KGSL) += msm_kgsl.o diff --git a/drivers/video/msm/gpu/kgsl/kgsl.c b/drivers/video/msm/gpu/kgsl/kgsl.c deleted file mode 100644 index 2d296514..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl.c +++ /dev/null @@ -1,1228 +0,0 @@ -/* -* Copyright (c) 2008-2009 QUALCOMM USA, INC. -* -* All source code in this file is licensed under the following license -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* version 2 as published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -* See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, you can find it at http://www.fsf.org -*/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "kgsl.h" -#include "kgsl_drawctxt.h" -#include "kgsl_ringbuffer.h" -#include "kgsl_cmdstream.h" -#include "kgsl_log.h" - -struct kgsl_file_private { - struct list_head list; - struct list_head mem_list; - uint32_t ctxt_id_mask; - struct kgsl_pagetable *pagetable; - unsigned long vmalloc_size; -}; - -static void kgsl_put_phys_file(struct file *file); - -#ifdef CONFIG_GPU_MSM_KGSL_MMU -static long flush_l1_cache_range(unsigned long addr, int size) -{ - struct page *page; - pte_t *pte_ptr; - unsigned long end; - - for (end = addr; end < (addr + size); end += KGSL_PAGESIZE) { - pte_ptr = kgsl_get_pte_from_vaddr(end); - if (!pte_ptr) - return -EINVAL; - - page = pte_page(pte_val(*pte_ptr)); - if (!page) { - KGSL_DRV_ERR("could not find page for pte\n"); - pte_unmap(pte_ptr); - return -EINVAL; - } - - pte_unmap(pte_ptr); - flush_dcache_page(page); - } - - return 0; -} - -static long flush_l1_cache_all(struct kgsl_file_private *private) -{ - int result = 0; - struct kgsl_mem_entry *entry = NULL; - - kgsl_yamato_runpending(&kgsl_driver.yamato_device); - list_for_each_entry(entry, &private->mem_list, list) { - if (KGSL_MEMFLAGS_MEM_REQUIRES_FLUSH & entry->memdesc.priv) { - result = - flush_l1_cache_range((unsigned long)entry-> - memdesc.hostptr, - entry->memdesc.size); - if (result) - goto done; - } - } -done: - return result; -} -#else -static inline long flush_l1_cache_range(unsigned long addr, int size) -{ return 0; } - -static inline long flush_l1_cache_all(struct kgsl_file_private *private) -{ return 0; } -#endif - -/*this is used for logging, so that we can call the dev_printk - functions without export struct kgsl_driver everywhere*/ -struct device *kgsl_driver_getdevnode(void) -{ - BUG_ON(kgsl_driver.pdev == NULL); - return &kgsl_driver.pdev->dev; -} - -/* the hw and clk enable/disable funcs must be either called from softirq or - * with mutex held */ -static void kgsl_clk_enable(void) -{ - clk_set_rate(kgsl_driver.ebi1_clk, 128000000); - clk_enable(kgsl_driver.imem_clk); - if (kgsl_driver.grp_pclk) - clk_enable(kgsl_driver.grp_pclk); - clk_enable(kgsl_driver.grp_clk); -} - -static void kgsl_clk_disable(void) -{ - clk_disable(kgsl_driver.grp_clk); - if (kgsl_driver.grp_pclk) - clk_disable(kgsl_driver.grp_pclk); - clk_disable(kgsl_driver.imem_clk); - clk_set_rate(kgsl_driver.ebi1_clk, 0); -} - -static void kgsl_hw_disable(void) -{ - kgsl_driver.active = false; - disable_irq(kgsl_driver.interrupt_num); - kgsl_clk_disable(); - pr_debug("kgsl: hw disabled\n"); - wake_unlock(&kgsl_driver.wake_lock); -} - -static void kgsl_hw_enable(void) -{ - wake_lock(&kgsl_driver.wake_lock); - kgsl_clk_enable(); - enable_irq(kgsl_driver.interrupt_num); - kgsl_driver.active = true; - pr_debug("kgsl: hw enabled\n"); -} - -static void kgsl_hw_get_locked(void) -{ - /* active_cnt is protected by driver mutex */ - if (kgsl_driver.active_cnt++ == 0) { - if (kgsl_driver.active) { - del_timer_sync(&kgsl_driver.standby_timer); - barrier(); - } - if (!kgsl_driver.active) - kgsl_hw_enable(); - } -} - -static void kgsl_hw_put_locked(bool start_timer) -{ - if ((--kgsl_driver.active_cnt == 0) && start_timer) { - mod_timer(&kgsl_driver.standby_timer, - jiffies + msecs_to_jiffies(20)); - } -} - -static void kgsl_do_standby_timer(unsigned long data) -{ - if (kgsl_yamato_is_idle(&kgsl_driver.yamato_device)) - kgsl_hw_disable(); - else - mod_timer(&kgsl_driver.standby_timer, - jiffies + msecs_to_jiffies(10)); -} - -/* file operations */ -static int kgsl_first_open_locked(void) -{ - int result = 0; - - BUG_ON(kgsl_driver.active); - BUG_ON(kgsl_driver.active_cnt); - - kgsl_clk_enable(); - - /* init devices */ - result = kgsl_yamato_init(&kgsl_driver.yamato_device, - &kgsl_driver.yamato_config); - if (result != 0) - goto done; - - result = kgsl_yamato_start(&kgsl_driver.yamato_device, 0); - if (result != 0) - goto done; - -done: - kgsl_clk_disable(); - return result; -} - -static int kgsl_last_release_locked(void) -{ - BUG_ON(kgsl_driver.active_cnt); - - disable_irq(kgsl_driver.interrupt_num); - - kgsl_yamato_stop(&kgsl_driver.yamato_device); - - /* close devices */ - kgsl_yamato_close(&kgsl_driver.yamato_device); - - kgsl_clk_disable(); - kgsl_driver.active = false; - wake_unlock(&kgsl_driver.wake_lock); - - return 0; -} - -static int kgsl_release(struct inode *inodep, struct file *filep) -{ - int result = 0; - unsigned int i; - struct kgsl_mem_entry *entry, *entry_tmp; - struct kgsl_file_private *private = NULL; - - mutex_lock(&kgsl_driver.mutex); - - private = filep->private_data; - BUG_ON(private == NULL); - filep->private_data = NULL; - list_del(&private->list); - - kgsl_hw_get_locked(); - - for (i = 0; i < KGSL_CONTEXT_MAX; i++) - if (private->ctxt_id_mask & (1 << i)) - kgsl_drawctxt_destroy(&kgsl_driver.yamato_device, i); - - list_for_each_entry_safe(entry, entry_tmp, &private->mem_list, list) - kgsl_remove_mem_entry(entry); - - if (private->pagetable != NULL) { - kgsl_yamato_cleanup_pt(&kgsl_driver.yamato_device, - private->pagetable); - kgsl_mmu_destroypagetableobject(private->pagetable); - private->pagetable = NULL; - } - - kfree(private); - - if (atomic_dec_return(&kgsl_driver.open_count) == 0) { - KGSL_DRV_VDBG("last_release\n"); - kgsl_hw_put_locked(false); - result = kgsl_last_release_locked(); - } else - kgsl_hw_put_locked(true); - - mutex_unlock(&kgsl_driver.mutex); - - return result; -} - -static int kgsl_open(struct inode *inodep, struct file *filep) -{ - int result = 0; - struct kgsl_file_private *private = NULL; - - KGSL_DRV_DBG("file %p pid %d\n", filep, task_pid_nr(current)); - - - if (filep->f_flags & O_EXCL) { - KGSL_DRV_ERR("O_EXCL not allowed\n"); - return -EBUSY; - } - - private = kzalloc(sizeof(*private), GFP_KERNEL); - if (private == NULL) { - KGSL_DRV_ERR("cannot allocate file private data\n"); - return -ENOMEM; - } - - mutex_lock(&kgsl_driver.mutex); - - private->ctxt_id_mask = 0; - INIT_LIST_HEAD(&private->mem_list); - - filep->private_data = private; - - list_add(&private->list, &kgsl_driver.client_list); - - if (atomic_inc_return(&kgsl_driver.open_count) == 1) { - result = kgsl_first_open_locked(); - if (result != 0) - goto done; - } - - kgsl_hw_get_locked(); - - /*NOTE: this must happen after first_open */ - private->pagetable = - kgsl_mmu_createpagetableobject(&kgsl_driver.yamato_device.mmu); - if (private->pagetable == NULL) { - result = -ENOMEM; - goto done; - } - result = kgsl_yamato_setup_pt(&kgsl_driver.yamato_device, - private->pagetable); - if (result) { - kgsl_mmu_destroypagetableobject(private->pagetable); - private->pagetable = NULL; - goto done; - } - private->vmalloc_size = 0; -done: - kgsl_hw_put_locked(true); - mutex_unlock(&kgsl_driver.mutex); - if (result != 0) - kgsl_release(inodep, filep); - return result; -} - - -/*call with driver locked */ -static struct kgsl_mem_entry * -kgsl_sharedmem_find(struct kgsl_file_private *private, unsigned int gpuaddr) -{ - struct kgsl_mem_entry *entry = NULL, *result = NULL; - - BUG_ON(private == NULL); - - list_for_each_entry(entry, &private->mem_list, list) { - if (entry->memdesc.gpuaddr == gpuaddr) { - result = entry; - break; - } - } - return result; -} - -/*call with driver locked */ -struct kgsl_mem_entry * -kgsl_sharedmem_find_region(struct kgsl_file_private *private, - unsigned int gpuaddr, - size_t size) -{ - struct kgsl_mem_entry *entry = NULL, *result = NULL; - - BUG_ON(private == NULL); - - list_for_each_entry(entry, &private->mem_list, list) { - if (gpuaddr >= entry->memdesc.gpuaddr && - ((gpuaddr + size) <= - (entry->memdesc.gpuaddr + entry->memdesc.size))) { - result = entry; - break; - } - } - - return result; -} - -/*call all ioctl sub functions with driver locked*/ - -static long kgsl_ioctl_device_getproperty(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_device_getproperty param; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - result = kgsl_yamato_getproperty(&kgsl_driver.yamato_device, - param.type, - param.value, param.sizebytes); -done: - return result; -} - -static long kgsl_ioctl_device_regread(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_device_regread param; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - result = kgsl_yamato_regread(&kgsl_driver.yamato_device, - param.offsetwords, ¶m.value); - if (result != 0) - goto done; - - if (copy_to_user(arg, ¶m, sizeof(param))) { - result = -EFAULT; - goto done; - } -done: - return result; -} - - -static long kgsl_ioctl_device_waittimestamp(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_device_waittimestamp param; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - - /* Don't wait forever, set a max value for now */ - if (param.timeout == -1) - param.timeout = 10 * MSEC_PER_SEC; - result = kgsl_yamato_waittimestamp(&kgsl_driver.yamato_device, - param.timestamp, - param.timeout); - - kgsl_yamato_runpending(&kgsl_driver.yamato_device); -done: - return result; -} - -static long kgsl_ioctl_rb_issueibcmds(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_ringbuffer_issueibcmds param; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - - if (param.drawctxt_id >= KGSL_CONTEXT_MAX - || (private->ctxt_id_mask & 1 << param.drawctxt_id) == 0) { - result = -EINVAL; - KGSL_DRV_ERR("invalid drawctxt drawctxt_id %d\n", - param.drawctxt_id); - result = -EINVAL; - goto done; - } - - if (kgsl_sharedmem_find_region(private, param.ibaddr, - param.sizedwords*sizeof(uint32_t)) == NULL) { - KGSL_DRV_ERR("invalid cmd buffer ibaddr %08x sizedwords %d\n", - param.ibaddr, param.sizedwords); - result = -EINVAL; - goto done; - - } - - result = kgsl_ringbuffer_issueibcmds(&kgsl_driver.yamato_device, - param.drawctxt_id, - param.ibaddr, - param.sizedwords, - ¶m.timestamp, - param.flags); - if (result != 0) - goto done; - - if (copy_to_user(arg, ¶m, sizeof(param))) { - result = -EFAULT; - goto done; - } -done: - return result; -} - -static long kgsl_ioctl_cmdstream_readtimestamp(struct kgsl_file_private - *private, void __user *arg) -{ - int result = 0; - struct kgsl_cmdstream_readtimestamp param; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - - param.timestamp = - kgsl_cmdstream_readtimestamp(&kgsl_driver.yamato_device, - param.type); - if (result != 0) - goto done; - - if (copy_to_user(arg, ¶m, sizeof(param))) { - result = -EFAULT; - goto done; - } -done: - return result; -} - -static long kgsl_ioctl_cmdstream_freememontimestamp(struct kgsl_file_private - *private, void __user *arg) -{ - int result = 0; - struct kgsl_cmdstream_freememontimestamp param; - struct kgsl_mem_entry *entry = NULL; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - - entry = kgsl_sharedmem_find(private, param.gpuaddr); - if (entry == NULL) { - KGSL_DRV_ERR("invalid gpuaddr %08x\n", param.gpuaddr); - result = -EINVAL; - goto done; - } - - if (entry->memdesc.priv & KGSL_MEMFLAGS_VMALLOC_MEM) - entry->memdesc.priv &= ~KGSL_MEMFLAGS_MEM_REQUIRES_FLUSH; - - result = kgsl_cmdstream_freememontimestamp(&kgsl_driver.yamato_device, - entry, - param.timestamp, - param.type); - - kgsl_yamato_runpending(&kgsl_driver.yamato_device); - -done: - return result; -} - -static long kgsl_ioctl_drawctxt_create(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_drawctxt_create param; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - - result = kgsl_drawctxt_create(&kgsl_driver.yamato_device, - private->pagetable, - param.flags, - ¶m.drawctxt_id); - if (result != 0) - goto done; - - if (copy_to_user(arg, ¶m, sizeof(param))) { - result = -EFAULT; - goto done; - } - - private->ctxt_id_mask |= 1 << param.drawctxt_id; - -done: - return result; -} - -static long kgsl_ioctl_drawctxt_destroy(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_drawctxt_destroy param; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - - if (param.drawctxt_id >= KGSL_CONTEXT_MAX - || (private->ctxt_id_mask & 1 << param.drawctxt_id) == 0) { - result = -EINVAL; - goto done; - } - - result = kgsl_drawctxt_destroy(&kgsl_driver.yamato_device, - param.drawctxt_id); - if (result == 0) - private->ctxt_id_mask &= ~(1 << param.drawctxt_id); - -done: - return result; -} - -void kgsl_remove_mem_entry(struct kgsl_mem_entry *entry) -{ - kgsl_mmu_unmap(entry->memdesc.pagetable, - entry->memdesc.gpuaddr & KGSL_PAGEMASK, - entry->memdesc.size); - if (KGSL_MEMFLAGS_VMALLOC_MEM & entry->memdesc.priv) { - vfree((void *)entry->memdesc.physaddr); - entry->priv->vmalloc_size -= entry->memdesc.size; - } else - kgsl_put_phys_file(entry->pmem_file); - list_del(&entry->list); - - if (entry->free_list.prev) - list_del(&entry->free_list); - - kfree(entry); - -} - -static long kgsl_ioctl_sharedmem_free(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_sharedmem_free param; - struct kgsl_mem_entry *entry = NULL; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - - entry = kgsl_sharedmem_find(private, param.gpuaddr); - if (entry == NULL) { - KGSL_DRV_ERR("invalid gpuaddr %08x\n", param.gpuaddr); - result = -EINVAL; - goto done; - } - - kgsl_remove_mem_entry(entry); -done: - return result; -} - -#ifdef CONFIG_GPU_MSM_KGSL_MMU -static int kgsl_ioctl_sharedmem_from_vmalloc(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0, len; - struct kgsl_sharedmem_from_vmalloc param; - struct kgsl_mem_entry *entry = NULL; - void *vmalloc_area; - struct vm_area_struct *vma; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto error; - } - - if (!param.hostptr) { - KGSL_DRV_ERR - ("Invalid host pointer of malloc passed: param.hostptr " - "%08x\n", param.hostptr); - result = -EINVAL; - goto error; - } - - vma = find_vma(current->mm, param.hostptr); - if (!vma) { - KGSL_MEM_ERR("Could not find vma for address %x\n", - param.hostptr); - result = -EINVAL; - goto error; - } - len = vma->vm_end - vma->vm_start; - if (vma->vm_pgoff || !IS_ALIGNED(len, PAGE_SIZE) - || !IS_ALIGNED(vma->vm_start, PAGE_SIZE)) { - KGSL_MEM_ERR - ("kgsl vmalloc mapping must be at offset 0 and page aligned\n"); - result = -EINVAL; - goto error; - } - if (vma->vm_start != param.hostptr) { - KGSL_MEM_ERR - ("vma start address is not equal to mmap address\n"); - result = -EINVAL; - goto error; - } - - if ((private->vmalloc_size + len) > KGSL_GRAPHICS_MEMORY_LOW_WATERMARK - && !param.force_no_low_watermark) { - result = -ENOMEM; - goto error; - } - - entry = kzalloc(sizeof(struct kgsl_mem_entry), GFP_KERNEL); - if (entry == NULL) { - result = -ENOMEM; - goto error; - } - - /* allocate memory and map it to user space */ - vmalloc_area = vmalloc_user(len); - if (!vmalloc_area) { - KGSL_MEM_ERR("vmalloc failed\n"); - result = -ENOMEM; - goto error_free_entry; - } - if (!kgsl_cache_enable) { - /* If we are going to map non-cached, make sure to flush the - * cache to ensure that previously cached data does not - * overwrite this memory */ - dmac_flush_range(vmalloc_area, vmalloc_area + len); - KGSL_MEM_INFO("Caching for memory allocation turned off\n"); - vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); - } else { - KGSL_MEM_INFO("Caching for memory allocation turned on\n"); - } - - result = remap_vmalloc_range(vma, vmalloc_area, 0); - if (result) { - KGSL_MEM_ERR("remap_vmalloc_range returned %d\n", result); - goto error_free_vmalloc; - } - - result = - kgsl_mmu_map(private->pagetable, (unsigned long)vmalloc_area, len, - GSL_PT_PAGE_RV | GSL_PT_PAGE_WV, - &entry->memdesc.gpuaddr, KGSL_MEMFLAGS_ALIGN4K); - - if (result != 0) - goto error_free_vmalloc; - - entry->memdesc.pagetable = private->pagetable; - entry->memdesc.size = len; - entry->memdesc.hostptr = (void *)param.hostptr; - entry->memdesc.priv = KGSL_MEMFLAGS_VMALLOC_MEM | - KGSL_MEMFLAGS_MEM_REQUIRES_FLUSH; - entry->memdesc.physaddr = (unsigned long)vmalloc_area; - entry->priv = private; - - param.gpuaddr = entry->memdesc.gpuaddr; - - if (copy_to_user(arg, ¶m, sizeof(param))) { - result = -EFAULT; - goto error_unmap_entry; - } - private->vmalloc_size += len; - list_add(&entry->list, &private->mem_list); - - return 0; - -error_unmap_entry: - kgsl_mmu_unmap(private->pagetable, entry->memdesc.gpuaddr, - entry->memdesc.size); - -error_free_vmalloc: - vfree(vmalloc_area); - -error_free_entry: - kfree(entry); - -error: - return result; -} -#else -static inline int kgsl_ioctl_sharedmem_from_vmalloc( - struct kgsl_file_private *private, void __user *arg) -{ - return -ENOSYS; -} -#endif - -static int kgsl_get_phys_file(int fd, unsigned long *start, unsigned long *len, - struct file **filep) -{ - struct file *fbfile; - int put_needed; - unsigned long vstart = 0; - int ret = 0; - dev_t rdev; - struct fb_info *info; - - *filep = NULL; - if (!get_pmem_file(fd, start, &vstart, len, filep)) - return 0; - - fbfile = fget_light(fd, &put_needed); - if (fbfile == NULL) - return -1; - - rdev = fbfile->f_dentry->d_inode->i_rdev; - info = MAJOR(rdev) == FB_MAJOR ? registered_fb[MINOR(rdev)] : NULL; - if (info) { - *start = info->fix.smem_start; - *len = info->fix.smem_len; - ret = 0; - } else - ret = -1; - fput_light(fbfile, put_needed); - - return ret; -} - -static void kgsl_put_phys_file(struct file *file) -{ - KGSL_DRV_DBG("put phys file %p\n", file); - if (file) - put_pmem_file(file); -} - -static int kgsl_ioctl_sharedmem_from_pmem(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_sharedmem_from_pmem param; - struct kgsl_mem_entry *entry = NULL; - unsigned long start = 0, len = 0; - struct file *pmem_file = NULL; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto error; - } - - if (kgsl_get_phys_file(param.pmem_fd, &start, &len, &pmem_file)) { - result = -EINVAL; - goto error; - } else if (param.offset + param.len > len) { - KGSL_DRV_ERR("%s: region too large 0x%x + 0x%x >= 0x%lx\n", - __func__, param.offset, param.len, len); - result = -EINVAL; - goto error_put_pmem; - } - - KGSL_MEM_INFO("get phys file %p start 0x%lx len 0x%lx\n", - pmem_file, start, len); - KGSL_DRV_DBG("locked phys file %p\n", pmem_file); - - entry = kzalloc(sizeof(*entry), GFP_KERNEL); - if (entry == NULL) { - result = -ENOMEM; - goto error_put_pmem; - } - - entry->pmem_file = pmem_file; - - entry->memdesc.pagetable = private->pagetable; - - /* Any MMU mapped memory must have a length in multiple of PAGESIZE */ - entry->memdesc.size = ALIGN(param.len, PAGE_SIZE); - - /*we shouldn't need to write here from kernel mode */ - entry->memdesc.hostptr = NULL; - - /* ensure that MMU mappings are at page boundary */ - entry->memdesc.physaddr = start + (param.offset & KGSL_PAGEMASK); - result = kgsl_mmu_map(private->pagetable, entry->memdesc.physaddr, - entry->memdesc.size, GSL_PT_PAGE_RV | GSL_PT_PAGE_WV, - &entry->memdesc.gpuaddr, - KGSL_MEMFLAGS_ALIGN4K | KGSL_MEMFLAGS_CONPHYS); - if (result) - goto error_free_entry; - - /* If the offset is not at 4K boundary then add the correct offset - * value to gpuaddr */ - entry->memdesc.gpuaddr += (param.offset & ~KGSL_PAGEMASK); - param.gpuaddr = entry->memdesc.gpuaddr; - - if (copy_to_user(arg, ¶m, sizeof(param))) { - result = -EFAULT; - goto error_unmap_entry; - } - list_add(&entry->list, &private->mem_list); - return result; - -error_unmap_entry: - kgsl_mmu_unmap(entry->memdesc.pagetable, - entry->memdesc.gpuaddr & KGSL_PAGEMASK, - entry->memdesc.size); -error_free_entry: - kfree(entry); - -error_put_pmem: - kgsl_put_phys_file(pmem_file); - -error: - return result; -} - -#ifdef CONFIG_GPU_MSM_KGSL_MMU -/*This function flushes a graphics memory allocation from CPU cache - *when caching is enabled with MMU*/ -static int kgsl_ioctl_sharedmem_flush_cache(struct kgsl_file_private *private, - void __user *arg) -{ - int result = 0; - struct kgsl_mem_entry *entry; - struct kgsl_sharedmem_free param; - - if (copy_from_user(¶m, arg, sizeof(param))) { - result = -EFAULT; - goto done; - } - - entry = kgsl_sharedmem_find(private, param.gpuaddr); - if (!entry) { - KGSL_DRV_ERR("invalid gpuaddr %08x\n", param.gpuaddr); - result = -EINVAL; - goto done; - } - result = flush_l1_cache_range((unsigned long)entry->memdesc.hostptr, - entry->memdesc.size); - /* Mark memory as being flushed so we don't flush it again */ - entry->memdesc.priv &= ~KGSL_MEMFLAGS_MEM_REQUIRES_FLUSH; -done: - return result; -} -#else -static int kgsl_ioctl_sharedmem_flush_cache(struct kgsl_file_private *private, - void __user *arg) -{ - return -ENOSYS; -} -#endif - - -static long kgsl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) -{ - int result = 0; - struct kgsl_file_private *private = filep->private_data; - struct kgsl_drawctxt_set_bin_base_offset binbase; - - BUG_ON(private == NULL); - - KGSL_DRV_VDBG("filep %p cmd 0x%08x arg 0x%08lx\n", filep, cmd, arg); - - mutex_lock(&kgsl_driver.mutex); - - kgsl_hw_get_locked(); - - switch (cmd) { - - case IOCTL_KGSL_DEVICE_GETPROPERTY: - result = - kgsl_ioctl_device_getproperty(private, (void __user *)arg); - break; - - case IOCTL_KGSL_DEVICE_REGREAD: - result = kgsl_ioctl_device_regread(private, (void __user *)arg); - break; - - case IOCTL_KGSL_DEVICE_WAITTIMESTAMP: - result = kgsl_ioctl_device_waittimestamp(private, - (void __user *)arg); - break; - - case IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS: - if (kgsl_cache_enable) - flush_l1_cache_all(private); - result = kgsl_ioctl_rb_issueibcmds(private, (void __user *)arg); - break; - - case IOCTL_KGSL_CMDSTREAM_READTIMESTAMP: - result = - kgsl_ioctl_cmdstream_readtimestamp(private, - (void __user *)arg); - break; - - case IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP: - result = - kgsl_ioctl_cmdstream_freememontimestamp(private, - (void __user *)arg); - break; - - case IOCTL_KGSL_DRAWCTXT_CREATE: - result = kgsl_ioctl_drawctxt_create(private, - (void __user *)arg); - break; - - case IOCTL_KGSL_DRAWCTXT_DESTROY: - result = - kgsl_ioctl_drawctxt_destroy(private, (void __user *)arg); - break; - - case IOCTL_KGSL_SHAREDMEM_FREE: - result = kgsl_ioctl_sharedmem_free(private, (void __user *)arg); - break; - - case IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC: - kgsl_yamato_runpending(&kgsl_driver.yamato_device); - result = kgsl_ioctl_sharedmem_from_vmalloc(private, - (void __user *)arg); - break; - - case IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE: - if (kgsl_cache_enable) - result = kgsl_ioctl_sharedmem_flush_cache(private, - (void __user *)arg); - break; - case IOCTL_KGSL_SHAREDMEM_FROM_PMEM: - kgsl_yamato_runpending(&kgsl_driver.yamato_device); - result = kgsl_ioctl_sharedmem_from_pmem(private, - (void __user *)arg); - break; - - case IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET: - if (copy_from_user(&binbase, (void __user *)arg, - sizeof(binbase))) { - result = -EFAULT; - break; - } - - if (private->ctxt_id_mask & (1 << binbase.drawctxt_id)) { - result = kgsl_drawctxt_set_bin_base_offset( - &kgsl_driver.yamato_device, - binbase.drawctxt_id, - binbase.offset); - } else { - result = -EINVAL; - KGSL_DRV_ERR("invalid drawctxt drawctxt_id %d\n", - binbase.drawctxt_id); - } - break; - - default: - KGSL_DRV_ERR("invalid ioctl code %08x\n", cmd); - result = -EINVAL; - break; - } - - kgsl_hw_put_locked(true); - mutex_unlock(&kgsl_driver.mutex); - KGSL_DRV_VDBG("result %d\n", result); - return result; -} - -static struct file_operations kgsl_fops = { - .owner = THIS_MODULE, - .release = kgsl_release, - .open = kgsl_open, - .unlocked_ioctl = kgsl_ioctl, -}; - - -struct kgsl_driver kgsl_driver = { - .misc = { - .name = DRIVER_NAME, - .minor = MISC_DYNAMIC_MINOR, - .fops = &kgsl_fops, - }, - .open_count = ATOMIC_INIT(0), - .mutex = __MUTEX_INITIALIZER(kgsl_driver.mutex), -}; - -static void kgsl_driver_cleanup(void) -{ - - wake_lock_destroy(&kgsl_driver.wake_lock); - - if (kgsl_driver.interrupt_num > 0) { - if (kgsl_driver.have_irq) { - free_irq(kgsl_driver.interrupt_num, NULL); - kgsl_driver.have_irq = 0; - } - kgsl_driver.interrupt_num = 0; - } - - /* shutdown memory apertures */ - kgsl_sharedmem_close(&kgsl_driver.shmem); - - if (kgsl_driver.grp_clk) { - clk_put(kgsl_driver.grp_clk); - kgsl_driver.grp_clk = NULL; - } - - if (kgsl_driver.imem_clk != NULL) { - clk_put(kgsl_driver.imem_clk); - kgsl_driver.imem_clk = NULL; - } - - if (kgsl_driver.ebi1_clk != NULL) { - clk_put(kgsl_driver.ebi1_clk); - kgsl_driver.ebi1_clk = NULL; - } - - kgsl_driver.pdev = NULL; - -} - - -static int __devinit kgsl_platform_probe(struct platform_device *pdev) -{ - int result = 0; - struct clk *clk; - struct resource *res = NULL; - - kgsl_debug_init(); - - INIT_LIST_HEAD(&kgsl_driver.client_list); - - /*acquire clocks */ - BUG_ON(kgsl_driver.grp_clk != NULL); - BUG_ON(kgsl_driver.imem_clk != NULL); - BUG_ON(kgsl_driver.ebi1_clk != NULL); - - kgsl_driver.pdev = pdev; - - setup_timer(&kgsl_driver.standby_timer, kgsl_do_standby_timer, 0); - wake_lock_init(&kgsl_driver.wake_lock, WAKE_LOCK_SUSPEND, "kgsl"); - - clk = clk_get(&pdev->dev, "grp_clk"); - if (IS_ERR(clk)) { - result = PTR_ERR(clk); - KGSL_DRV_ERR("clk_get(grp_clk) returned %d\n", result); - goto done; - } - kgsl_driver.grp_clk = clk; - - clk = clk_get(&pdev->dev, "grp_pclk"); - if (IS_ERR(clk)) { - KGSL_DRV_ERR("no grp_pclk, continuing\n"); - clk = NULL; - } - kgsl_driver.grp_pclk = clk; - - clk = clk_get(&pdev->dev, "imem_clk"); - if (IS_ERR(clk)) { - result = PTR_ERR(clk); - KGSL_DRV_ERR("clk_get(imem_clk) returned %d\n", result); - goto done; - } - kgsl_driver.imem_clk = clk; - - clk = clk_get(&pdev->dev, "ebi1_clk"); - if (IS_ERR(clk)) { - result = PTR_ERR(clk); - KGSL_DRV_ERR("clk_get(ebi1_clk) returned %d\n", result); - goto done; - } - kgsl_driver.ebi1_clk = clk; - - /*acquire interrupt */ - kgsl_driver.interrupt_num = platform_get_irq(pdev, 0); - if (kgsl_driver.interrupt_num <= 0) { - KGSL_DRV_ERR("platform_get_irq() returned %d\n", - kgsl_driver.interrupt_num); - result = -EINVAL; - goto done; - } - - result = request_irq(kgsl_driver.interrupt_num, kgsl_yamato_isr, - IRQF_TRIGGER_HIGH, DRIVER_NAME, NULL); - if (result) { - KGSL_DRV_ERR("request_irq(%d) returned %d\n", - kgsl_driver.interrupt_num, result); - goto done; - } - kgsl_driver.have_irq = 1; - disable_irq(kgsl_driver.interrupt_num); - - result = kgsl_yamato_config(&kgsl_driver.yamato_config, pdev); - if (result != 0) - goto done; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "kgsl_phys_memory"); - if (res == NULL) { - result = -EINVAL; - goto done; - } - - kgsl_driver.shmem.physbase = res->start; - kgsl_driver.shmem.size = resource_size(res); - - /* init memory apertures */ - result = kgsl_sharedmem_init(&kgsl_driver.shmem); - -done: - if (result) - kgsl_driver_cleanup(); - else - result = misc_register(&kgsl_driver.misc); - - return result; -} - -static int kgsl_platform_remove(struct platform_device *pdev) -{ - - kgsl_driver_cleanup(); - misc_deregister(&kgsl_driver.misc); - - return 0; -} - -static int kgsl_platform_suspend(struct platform_device *pdev, - pm_message_t state) -{ - mutex_lock(&kgsl_driver.mutex); - if (atomic_read(&kgsl_driver.open_count) > 0) { - if (kgsl_driver.active) - pr_err("%s: Suspending while active???\n", __func__); - } - mutex_unlock(&kgsl_driver.mutex); - return 0; -} - -static struct platform_driver kgsl_platform_driver = { - .probe = kgsl_platform_probe, - .remove = __devexit_p(kgsl_platform_remove), - .suspend = kgsl_platform_suspend, - .driver = { - .owner = THIS_MODULE, - .name = DRIVER_NAME - } -}; - -static int __init kgsl_mod_init(void) -{ - return platform_driver_register(&kgsl_platform_driver); -} - -static void __exit kgsl_mod_exit(void) -{ - platform_driver_unregister(&kgsl_platform_driver); -} - -module_init(kgsl_mod_init); -module_exit(kgsl_mod_exit); - -MODULE_AUTHOR("QUALCOMM"); -MODULE_DESCRIPTION("3D graphics driver for QSD8x50 and MSM7x27"); -MODULE_VERSION("1.0"); -MODULE_LICENSE("Dual BSD/GPL"); -MODULE_ALIAS("platform:kgsl"); diff --git a/drivers/video/msm/gpu/kgsl/kgsl.h b/drivers/video/msm/gpu/kgsl/kgsl.h deleted file mode 100644 index e9f0d7cc..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl.h +++ /dev/null @@ -1,84 +0,0 @@ -/* -* Copyright (c) 2008-2009 QUALCOMM USA, INC. -* -* All source code in this file is licensed under the following license -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* version 2 as published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -* See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, you can find it at http://www.fsf.org -*/ -#ifndef _GSL_DRIVER_H -#define _GSL_DRIVER_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "kgsl_device.h" -#include "kgsl_sharedmem.h" - -#define DRIVER_NAME "kgsl" - -struct kgsl_driver { - struct miscdevice misc; - struct platform_device *pdev; - atomic_t open_count; - struct mutex mutex; - - int interrupt_num; - int have_irq; - - struct clk *grp_clk; - struct clk *grp_pclk; - struct clk *imem_clk; - struct clk *ebi1_clk; - - struct kgsl_devconfig yamato_config; - - uint32_t flags_debug; - - struct kgsl_sharedmem shmem; - struct kgsl_device yamato_device; - - struct list_head client_list; - - bool active; - int active_cnt; - struct timer_list standby_timer; - - struct wake_lock wake_lock; -}; - -extern struct kgsl_driver kgsl_driver; - -struct kgsl_mem_entry { - struct kgsl_memdesc memdesc; - struct file *pmem_file; - struct list_head list; - struct list_head free_list; - uint32_t free_timestamp; - - /* back pointer to private structure under whose context this - * allocation is made */ - struct kgsl_file_private *priv; -}; - -void kgsl_remove_mem_entry(struct kgsl_mem_entry *entry); - -#endif /* _GSL_DRIVER_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_cmdstream.c b/drivers/video/msm/gpu/kgsl/kgsl_cmdstream.c deleted file mode 100644 index d8a16551..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_cmdstream.c +++ /dev/null @@ -1,105 +0,0 @@ -/* -* Copyright (c) 2008-2009 QUALCOMM USA, INC. -* -* All source code in this file is licensed under the following license -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* version 2 as published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -* See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, you can find it at http://www.fsf.org -*/ - -#include "kgsl.h" -#include "kgsl_device.h" -#include "kgsl_cmdstream.h" -#include "kgsl_sharedmem.h" - -int kgsl_cmdstream_init(struct kgsl_device *device) -{ - return 0; -} - -int kgsl_cmdstream_close(struct kgsl_device *device) -{ - return 0; -} - -uint32_t -kgsl_cmdstream_readtimestamp(struct kgsl_device *device, - enum kgsl_timestamp_type type) -{ - uint32_t timestamp = 0; - - KGSL_CMD_VDBG("enter (device_id=%d, type=%d)\n", device->id, type); - - if (type == KGSL_TIMESTAMP_CONSUMED) - KGSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, - (unsigned int *)×tamp); - else if (type == KGSL_TIMESTAMP_RETIRED) - KGSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, - (unsigned int *)×tamp); - - rmb(); - - KGSL_CMD_VDBG("return %d\n", timestamp); - - return timestamp; -} - -int kgsl_cmdstream_check_timestamp(struct kgsl_device *device, - unsigned int timestamp) -{ - unsigned int ts_processed; - - ts_processed = kgsl_cmdstream_readtimestamp(device, - KGSL_TIMESTAMP_RETIRED); - return timestamp_cmp(ts_processed, timestamp); -} - -void kgsl_cmdstream_memqueue_drain(struct kgsl_device *device) -{ - struct kgsl_mem_entry *entry, *entry_tmp; - uint32_t ts_processed; - struct kgsl_ringbuffer *rb = &device->ringbuffer; - - /* get current EOP timestamp */ - ts_processed = - kgsl_cmdstream_readtimestamp(device, KGSL_TIMESTAMP_RETIRED); - - list_for_each_entry_safe(entry, entry_tmp, &rb->memqueue, free_list) { - /*NOTE: this assumes that the free list is sorted by - * timestamp, but I'm not yet sure that it is a valid - * assumption - */ - if (!timestamp_cmp(ts_processed, entry->free_timestamp)) - break; - KGSL_MEM_DBG("ts_processed %d ts_free %d gpuaddr %x)\n", - ts_processed, entry->free_timestamp, - entry->memdesc.gpuaddr); - kgsl_remove_mem_entry(entry); - } -} - -int -kgsl_cmdstream_freememontimestamp(struct kgsl_device *device, - struct kgsl_mem_entry *entry, - uint32_t timestamp, - enum kgsl_timestamp_type type) -{ - struct kgsl_ringbuffer *rb = &device->ringbuffer; - KGSL_MEM_DBG("enter (dev %p gpuaddr %x ts %d)\n", - device, entry->memdesc.gpuaddr, timestamp); - (void)type; /* unref. For now just use EOP timestamp */ - - list_add_tail(&entry->free_list, &rb->memqueue); - entry->free_timestamp = timestamp; - - return 0; -} diff --git a/drivers/video/msm/gpu/kgsl/kgsl_cmdstream.h b/drivers/video/msm/gpu/kgsl/kgsl_cmdstream.h deleted file mode 100644 index f81ef546..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_cmdstream.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef __KGSL_CMDSTREAM_H -#define __KGSL_CMDSTREAM_H - -#include -#include "kgsl_device.h" -#include "kgsl_log.h" - -#ifdef KGSL_DEVICE_SHADOW_MEMSTORE_TO_USER -#define KGSL_CMDSTREAM_USE_MEM_TIMESTAMP -#endif /* KGSL_DEVICE_SHADOW_MEMSTORE_TO_USER */ - -#ifdef KGSL_CMDSTREAM_USE_MEM_TIMESTAMP -#define KGSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data) \ - kgsl_sharedmem_read(&device->memstore, (data), \ - KGSL_DEVICE_MEMSTORE_OFFSET(soptimestamp), 4) -#else -#define KGSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data) \ - kgsl_yamato_regread(device, REG_CP_TIMESTAMP, (data)) -#endif /* KGSL_CMDSTREAM_USE_MEM_TIMESTAMP */ - -#define KGSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data) \ - kgsl_sharedmem_read(&device->memstore, (data), \ - KGSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), 4) - -/* Flags to control command packet settings */ -#define KGSL_CMD_FLAGS_PMODE 0x00000001 -#define KGSL_CMD_FLAGS_NO_TS_CMP 0x00000002 - -int kgsl_cmdstream_init(struct kgsl_device *device); - -int kgsl_cmdstream_close(struct kgsl_device *device); - -void kgsl_cmdstream_memqueue_drain(struct kgsl_device *device); - -uint32_t -kgsl_cmdstream_readtimestamp(struct kgsl_device *device, - enum kgsl_timestamp_type type); - -int kgsl_cmdstream_check_timestamp(struct kgsl_device *device, - unsigned int timestamp); - -int -kgsl_cmdstream_freememontimestamp(struct kgsl_device *device, - struct kgsl_mem_entry *entry, - uint32_t timestamp, - enum kgsl_timestamp_type type); - -static inline bool timestamp_cmp(unsigned int new, unsigned int old) -{ - int ts_diff = new - old; - return (ts_diff >= 0) || (ts_diff < -20000); -} - -#endif /* __KGSL_CMDSTREAM_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_device.h b/drivers/video/msm/gpu/kgsl/kgsl_device.h deleted file mode 100644 index c88e0cb5..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_device.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#ifndef _KGSL_DEVICE_H -#define _KGSL_DEVICE_H - -#include - -#include -#include -#include -#include - -#include "kgsl_drawctxt.h" -#include "kgsl_mmu.h" -#include "kgsl_ringbuffer.h" - -#define KGSL_CONTEXT_MAX 8 - -#define KGSL_TIMEOUT_NONE 0 -#define KGSL_TIMEOUT_DEFAULT 0xFFFFFFFF - -#define KGSL_DEV_FLAGS_INITIALIZED0 0x00000001 -#define KGSL_DEV_FLAGS_INITIALIZED 0x00000002 -#define KGSL_DEV_FLAGS_STARTED 0x00000004 -#define KGSL_DEV_FLAGS_ACTIVE 0x00000008 - -#define KGSL_CHIPID_YAMATODX_REV21 0x20100 -#define KGSL_CHIPID_YAMATODX_REV211 0x20101 - -/* Private memory flags for use with memdesc->priv feild */ -#define KGSL_MEMFLAGS_MEM_REQUIRES_FLUSH 0x00000001 -#define KGSL_MEMFLAGS_VMALLOC_MEM 0x00000002 - -#define KGSL_GRAPHICS_MEMORY_LOW_WATERMARK 0x1000000 -#define KGSL_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK))) - -struct kgsl_device; -struct platform_device; - - -struct kgsl_memregion { - unsigned char *mmio_virt_base; - unsigned int mmio_phys_base; - uint32_t gpu_base; - unsigned int sizebytes; -}; - -struct kgsl_device { - - unsigned int refcnt; - uint32_t flags; - enum kgsl_deviceid id; - unsigned int chip_id; - struct kgsl_memregion regspace; - struct kgsl_memdesc memstore; - - struct kgsl_mmu mmu; - struct kgsl_memregion gmemspace; - struct kgsl_ringbuffer ringbuffer; - unsigned int drawctxt_count; - struct kgsl_drawctxt *drawctxt_active; - struct kgsl_drawctxt drawctxt[KGSL_CONTEXT_MAX]; - - wait_queue_head_t ib1_wq; -}; - -struct kgsl_devconfig { - struct kgsl_memregion regspace; - - unsigned int mmu_config; - uint32_t mpu_base; - int mpu_range; - uint32_t va_base; - unsigned int va_range; - - struct kgsl_memregion gmemspace; -}; - -int kgsl_yamato_start(struct kgsl_device *device, uint32_t flags); - -int kgsl_yamato_stop(struct kgsl_device *device); - -bool kgsl_yamato_is_idle(struct kgsl_device *device); - -int kgsl_yamato_idle(struct kgsl_device *device, unsigned int timeout); - -int kgsl_yamato_getproperty(struct kgsl_device *device, - enum kgsl_property_type type, void *value, - unsigned int sizebytes); - -int kgsl_yamato_regread(struct kgsl_device *device, unsigned int offsetwords, - unsigned int *value); - -int kgsl_yamato_regwrite(struct kgsl_device *device, unsigned int offsetwords, - unsigned int value); - -int kgsl_yamato_waittimestamp(struct kgsl_device *device, - unsigned int timestamp, unsigned int timeout); - - -int kgsl_yamato_init(struct kgsl_device *, struct kgsl_devconfig *); - -int kgsl_yamato_close(struct kgsl_device *device); - -int kgsl_yamato_runpending(struct kgsl_device *device); - -int __init kgsl_yamato_config(struct kgsl_devconfig *, - struct platform_device *pdev); - -void kgsl_register_dump(struct kgsl_device *device); - -int kgsl_yamato_setup_pt(struct kgsl_device *device, - struct kgsl_pagetable *pagetable); -int kgsl_yamato_cleanup_pt(struct kgsl_device *device, - struct kgsl_pagetable *pagetable); -#ifdef CONFIG_GPU_MSM_KGSL_MMU -int kgsl_yamato_setstate(struct kgsl_device *device, uint32_t flags); -#else -static inline int kgsl_yamato_setstate(struct kgsl_device *device, uint32_t flags) -{ return 0; } -#endif - -irqreturn_t kgsl_yamato_isr(int irq, void *data); - -#endif /* _KGSL_DEVICE_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_drawctxt.c b/drivers/video/msm/gpu/kgsl/kgsl_drawctxt.c deleted file mode 100644 index 3e5262e8..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_drawctxt.c +++ /dev/null @@ -1,1823 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#include -#include -#include - -#include "kgsl_drawctxt.h" - -#include "yamato_reg.h" -#include "kgsl.h" -#include "kgsl_log.h" -#include "kgsl_pm4types.h" -#include "kgsl_cmdstream.h" - -/* -* -* Memory Map for Register, Constant & Instruction Shadow, and Command Buffers -* (34.5KB) -* -* +---------------------+------------+-------------+---+---------------------+ -* | ALU Constant Shadow | Reg Shadow | C&V Buffers |Tex| Shader Instr Shadow | -* +---------------------+------------+-------------+---+---------------------+ -* ________________________________/ \____________________ -* / | -* +--------------+-----------+------+-----------+------------------------+ -* | Restore Regs | Save Regs | Quad | Gmem Save | Gmem Restore | unused | -* +--------------+-----------+------+-----------+------------------------+ -* -* 8K - ALU Constant Shadow (8K aligned) -* 4K - H/W Register Shadow (8K aligned) -* 4K - Command and Vertex Buffers -* - Indirect command buffer : Const/Reg restore -* - includes Loop & Bool const shadows -* - Indirect command buffer : Const/Reg save -* - Quad vertices & texture coordinates -* - Indirect command buffer : Gmem save -* - Indirect command buffer : Gmem restore -* - Unused (padding to 8KB boundary) -* <1K - Texture Constant Shadow (768 bytes) (8K aligned) -* 18K - Shader Instruction Shadow -* - 6K vertex (32 byte aligned) -* - 6K pixel (32 byte aligned) -* - 6K shared (32 byte aligned) -* -* Note: Reading constants into a shadow, one at a time using REG_TO_MEM, takes -* 3 DWORDS per DWORD transfered, plus 1 DWORD for the shadow, for a total of -* 16 bytes per constant. If the texture constants were transfered this way, -* the Command & Vertex Buffers section would extend past the 16K boundary. -* By moving the texture constant shadow area to start at 16KB boundary, we -* only require approximately 40 bytes more memory, but are able to use the -* LOAD_CONSTANT_CONTEXT shadowing feature for the textures, speeding up -* context switching. -* -* [Using LOAD_CONSTANT_CONTEXT shadowing feature for the Loop and/or Bool -* constants would require an additional 8KB each, for alignment.] -* -*/ - -/* Constants */ - -#define ALU_CONSTANTS 2048 /* DWORDS */ -#define NUM_REGISTERS 1024 /* DWORDS */ -#ifdef DISABLE_SHADOW_WRITES -#define CMD_BUFFER_LEN 9216 /* DWORDS */ -#else -#define CMD_BUFFER_LEN 3072 /* DWORDS */ -#endif -#define TEX_CONSTANTS (32*6) /* DWORDS */ -#define BOOL_CONSTANTS 8 /* DWORDS */ -#define LOOP_CONSTANTS 56 /* DWORDS */ -#define SHADER_INSTRUCT_LOG2 9U /* 2^n == SHADER_INSTRUCTIONS */ - -#if defined(PM4_IM_STORE) -/* 96-bit instructions */ -#define SHADER_INSTRUCT (1<= 0x10000) { - exp += 16; - u >>= 16; - } - if (u >= 0x100) { - exp += 8; - u >>= 8; - } - if (u >= 0x10) { - exp += 4; - u >>= 4; - } - if (u >= 0x4) { - exp += 2; - u >>= 2; - } - if (u >= 0x2) { - exp += 1; - u >>= 1; - } - - /* Calculate fraction */ - frac = (uintval & (~(1 << exp))) << (23 - exp); - - /* Exp is biased by 127 and shifted 23 bits */ - exp = (exp + 127) << 23; - - return exp | frac; -} - -/* context save (gmem -> sys) */ - -/* pre-compiled vertex shader program -* -* attribute vec4 P; -* void main(void) -* { -* gl_Position = P; -* } -*/ -#define GMEM2SYS_VTX_PGM_LEN 0x12 - -static unsigned int gmem2sys_vtx_pgm[GMEM2SYS_VTX_PGM_LEN] = { - 0x00011003, 0x00001000, 0xc2000000, - 0x00001004, 0x00001000, 0xc4000000, - 0x00001005, 0x00002000, 0x00000000, - 0x1cb81000, 0x00398a88, 0x00000003, - 0x140f803e, 0x00000000, 0xe2010100, - 0x14000000, 0x00000000, 0xe2000000 -}; - -/* pre-compiled fragment shader program -* -* precision highp float; -* uniform vec4 clear_color; -* void main(void) -* { -* gl_FragColor = clear_color; -* } -*/ - -#define GMEM2SYS_FRAG_PGM_LEN 0x0c - -static unsigned int gmem2sys_frag_pgm[GMEM2SYS_FRAG_PGM_LEN] = { - 0x00000000, 0x1002c400, 0x10000000, - 0x00001003, 0x00002000, 0x00000000, - 0x140f8000, 0x00000000, 0x22000000, - 0x14000000, 0x00000000, 0xe2000000 -}; - -/* context restore (sys -> gmem) */ -/* pre-compiled vertex shader program -* -* attribute vec4 position; -* attribute vec4 texcoord; -* varying vec4 texcoord0; -* void main() -* { -* gl_Position = position; -* texcoord0 = texcoord; -* } -*/ - -#define SYS2GMEM_VTX_PGM_LEN 0x18 - -static unsigned int sys2gmem_vtx_pgm[SYS2GMEM_VTX_PGM_LEN] = { - 0x00052003, 0x00001000, 0xc2000000, 0x00001005, - 0x00001000, 0xc4000000, 0x00001006, 0x10071000, - 0x20000000, 0x18981000, 0x0039ba88, 0x00000003, - 0x12982000, 0x40257b08, 0x00000002, 0x140f803e, - 0x00000000, 0xe2010100, 0x140f8000, 0x00000000, - 0xe2020200, 0x14000000, 0x00000000, 0xe2000000 -}; - -/* pre-compiled fragment shader program -* -* precision mediump float; -* uniform sampler2D tex0; -* varying vec4 texcoord0; -* void main() -* { -* gl_FragColor = texture2D(tex0, texcoord0.xy); -* } -*/ - -#define SYS2GMEM_FRAG_PGM_LEN 0x0f - -static unsigned int sys2gmem_frag_pgm[SYS2GMEM_FRAG_PGM_LEN] = { - 0x00011002, 0x00001000, 0xc4000000, 0x00001003, - 0x10041000, 0x20000000, 0x10000001, 0x1ffff688, - 0x00000002, 0x140f8000, 0x00000000, 0xe2000000, - 0x14000000, 0x00000000, 0xe2000000 -}; - -/* shader texture constants (sysmem -> gmem) */ -#define SYS2GMEM_TEX_CONST_LEN 6 - -static unsigned int sys2gmem_tex_const[SYS2GMEM_TEX_CONST_LEN] = { - /* Texture, FormatXYZW=Unsigned, ClampXYZ=Wrap/Repeat, - * RFMode=ZeroClamp-1, Dim=1:2d - */ - 0x00000002, /* Pitch = TBD */ - - /* Format=6:8888_WZYX, EndianSwap=0:None, ReqSize=0:256bit, DimHi=0, - * NearestClamp=1:OGL Mode - */ - 0x00000800, /* Address[31:12] = TBD */ - - /* Width, Height, EndianSwap=0:None */ - 0, /* Width & Height = TBD */ - - /* NumFormat=0:RF, DstSelXYZW=XYZW, ExpAdj=0, MagFilt=MinFilt=0:Point, - * Mip=2:BaseMap - */ - 0 << 1 | 1 << 4 | 2 << 7 | 3 << 10 | 2 << 23, - - /* VolMag=VolMin=0:Point, MinMipLvl=0, MaxMipLvl=1, LodBiasH=V=0, - * Dim3d=0 - */ - 0, - - /* BorderColor=0:ABGRBlack, ForceBC=0:diable, TriJuice=0, Aniso=0, - * Dim=1:2d, MipPacking=0 - */ - 1 << 9 /* Mip Address[31:12] = TBD */ -}; - -/* quad for copying GMEM to context shadow */ -#define QUAD_LEN 12 - -static unsigned int gmem_copy_quad[QUAD_LEN] = { - 0x00000000, 0x00000000, 0x3f800000, - 0x00000000, 0x00000000, 0x3f800000, - 0x00000000, 0x00000000, 0x3f800000, - 0x00000000, 0x00000000, 0x3f800000 -}; - -#define TEXCOORD_LEN 8 - -static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = { - 0x00000000, 0x3f800000, - 0x3f800000, 0x3f800000, - 0x00000000, 0x00000000, - 0x3f800000, 0x00000000 -}; - -#define NUM_COLOR_FORMATS 13 - -static enum SURFACEFORMAT surface_format_table[NUM_COLOR_FORMATS] = { - FMT_4_4_4_4, /* COLORX_4_4_4_4 */ - FMT_1_5_5_5, /* COLORX_1_5_5_5 */ - FMT_5_6_5, /* COLORX_5_6_5 */ - FMT_8, /* COLORX_8 */ - FMT_8_8, /* COLORX_8_8 */ - FMT_8_8_8_8, /* COLORX_8_8_8_8 */ - FMT_8_8_8_8, /* COLORX_S8_8_8_8 */ - FMT_16_FLOAT, /* COLORX_16_FLOAT */ - FMT_16_16_FLOAT, /* COLORX_16_16_FLOAT */ - FMT_16_16_16_16_FLOAT, /* COLORX_16_16_16_16_FLOAT */ - FMT_32_FLOAT, /* COLORX_32_FLOAT */ - FMT_32_32_FLOAT, /* COLORX_32_32_FLOAT */ - FMT_32_32_32_32_FLOAT, /* COLORX_32_32_32_32_FLOAT */ -}; - -static unsigned int format2bytesperpixel[NUM_COLOR_FORMATS] = { - 2, /* COLORX_4_4_4_4 */ - 2, /* COLORX_1_5_5_5 */ - 2, /* COLORX_5_6_5 */ - 1, /* COLORX_8 */ - 2, /* COLORX_8_8 8*/ - 4, /* COLORX_8_8_8_8 */ - 4, /* COLORX_S8_8_8_8 */ - 2, /* COLORX_16_FLOAT */ - 4, /* COLORX_16_16_FLOAT */ - 8, /* COLORX_16_16_16_16_FLOAT */ - 4, /* COLORX_32_FLOAT */ - 8, /* COLORX_32_32_FLOAT */ - 16, /* COLORX_32_32_32_32_FLOAT */ -}; - -/* shader linkage info */ -#define SHADER_CONST_ADDR (11 * 6 + 3) - -/* gmem command buffer length */ -#define PM4_REG(reg) ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg))) - -/* functions */ -static void config_gmemsize(struct gmem_shadow_t *shadow, int gmem_size) -{ - int w = 64, h = 64; /* 16KB surface, minimum */ - - shadow->format = COLORX_8_8_8_8; - /* convert from bytes to 32-bit words */ - gmem_size = (gmem_size + 3) / 4; - - /* find the right surface size, close to a square. */ - while (w * h < gmem_size) - if (w < h) - w *= 2; - else - h *= 2; - - shadow->width = w; - shadow->pitch = w; - shadow->height = h; - shadow->gmem_pitch = shadow->pitch; - - shadow->size = shadow->pitch * shadow->height * 4; -} - -static unsigned int gpuaddr(unsigned int *cmd, struct kgsl_memdesc *memdesc) -{ - return memdesc->gpuaddr + ((char *)cmd - (char *)memdesc->hostptr); -} - -static void -create_ib1(struct kgsl_drawctxt *drawctxt, unsigned int *cmd, - unsigned int *start, unsigned int *end) -{ - cmd[0] = PM4_HDR_INDIRECT_BUFFER_PFD; - cmd[1] = gpuaddr(start, &drawctxt->gpustate); - cmd[2] = end - start; -} - -static unsigned int *program_shader(unsigned int *cmds, int vtxfrag, - unsigned int *shader_pgm, int dwords) -{ - /* load the patched vertex shader stream */ - *cmds++ = pm4_type3_packet(PM4_IM_LOAD_IMMEDIATE, 2 + dwords); - /* 0=vertex shader, 1=fragment shader */ - *cmds++ = vtxfrag; - /* instruction start & size (in 32-bit words) */ - *cmds++ = ((0 << 16) | dwords); - - memcpy(cmds, shader_pgm, dwords << 2); - cmds += dwords; - - return cmds; -} - -static unsigned int *reg_to_mem(unsigned int *cmds, uint32_t dst, - uint32_t src, int dwords) -{ - while (dwords-- > 0) { - *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmds++ = src++; - *cmds++ = dst; - dst += 4; - } - - return cmds; -} - -#ifdef DISABLE_SHADOW_WRITES - -static void build_reg_to_mem_range(unsigned int start, unsigned int end, - unsigned int **cmd, - struct kgsl_drawctxt *drawctxt) -{ - unsigned int i = start; - - for (i = start; i <= end; i++) { - *(*cmd)++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *(*cmd)++ = i | (1 << 30); - *(*cmd)++ = - ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) + - (i - 0x2000) * 4; - } -} - -#endif - -/* chicken restore */ -static unsigned int *build_chicken_restore_cmds(struct kgsl_drawctxt *drawctxt, - struct tmp_ctx *ctx) -{ - unsigned int *start = ctx->cmd; - unsigned int *cmds = start; - - *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmds++ = 0; - - *cmds++ = pm4_type0_packet(REG_TP0_CHICKEN, 1); - ctx->chicken_restore = gpuaddr(cmds, &drawctxt->gpustate); - *cmds++ = 0x00000000; - - /* create indirect buffer command for above command sequence */ - create_ib1(drawctxt, drawctxt->chicken_restore, start, cmds); - - return cmds; -} - -/* save h/w regs, alu constants, texture contants, etc. ... -* requires: bool_shadow_gpuaddr, loop_shadow_gpuaddr -*/ -static void build_regsave_cmds(struct kgsl_device *device, - struct kgsl_drawctxt *drawctxt, - struct tmp_ctx *ctx) -{ - unsigned int *start = ctx->cmd; - unsigned int *cmd = start; - unsigned int pm_override1; - - kgsl_yamato_regread(device, REG_RBBM_PM_OVERRIDE1, &pm_override1); - - *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmd++ = 0; - -#ifdef DISABLE_SHADOW_WRITES - /* Make sure the HW context has the correct register values - * before reading them. */ - *cmd++ = pm4_type3_packet(PM4_CONTEXT_UPDATE, 1); - *cmd++ = 0; -#endif - - /* Enable clock override for REG_FIFOS_SCLK */ - *cmd++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - *cmd++ = pm_override1 | (1 << 6); - -#ifdef DISABLE_SHADOW_WRITES - /* Write HW registers into shadow */ - build_reg_to_mem_range(REG_RB_SURFACE_INFO, REG_RB_DEPTH_INFO, &cmd, - drawctxt); - build_reg_to_mem_range(REG_COHER_DEST_BASE_0, - REG_PA_SC_SCREEN_SCISSOR_BR, &cmd, drawctxt); - build_reg_to_mem_range(REG_PA_SC_WINDOW_OFFSET, - REG_PA_SC_WINDOW_SCISSOR_BR, &cmd, drawctxt); - build_reg_to_mem_range(REG_VGT_MAX_VTX_INDX, REG_RB_FOG_COLOR, &cmd, - drawctxt); - build_reg_to_mem_range(REG_RB_STENCILREFMASK_BF, - REG_PA_CL_VPORT_ZOFFSET, &cmd, drawctxt); - build_reg_to_mem_range(REG_SQ_PROGRAM_CNTL, REG_SQ_WRAPPING_1, &cmd, - drawctxt); - build_reg_to_mem_range(REG_RB_DEPTHCONTROL, REG_RB_MODECONTROL, &cmd, - drawctxt); - build_reg_to_mem_range(REG_PA_SU_POINT_SIZE, REG_PA_SC_LINE_STIPPLE, - &cmd, drawctxt); - build_reg_to_mem_range(REG_PA_SC_VIZ_QUERY, REG_PA_SC_VIZ_QUERY, &cmd, - drawctxt); - build_reg_to_mem_range(REG_PA_SC_LINE_CNTL, REG_SQ_PS_CONST, &cmd, - drawctxt); - build_reg_to_mem_range(REG_PA_SC_AA_MASK, REG_PA_SC_AA_MASK, &cmd, - drawctxt); - build_reg_to_mem_range(REG_VGT_VERTEX_REUSE_BLOCK_CNTL, - REG_RB_DEPTH_CLEAR, &cmd, drawctxt); - build_reg_to_mem_range(REG_RB_SAMPLE_COUNT_CTL, REG_RB_COLOR_DEST_MASK, - &cmd, drawctxt); - build_reg_to_mem_range(REG_PA_SU_POLY_OFFSET_FRONT_SCALE, - REG_PA_SU_POLY_OFFSET_BACK_OFFSET, &cmd, - drawctxt); - - /* Copy ALU constants */ - cmd = - reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr) & 0xFFFFE000, - REG_SQ_CONSTANT_0, ALU_CONSTANTS); - - /* Copy Tex constants */ - cmd = - reg_to_mem(cmd, - (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000, - REG_SQ_FETCH_0, TEX_CONSTANTS); -#else - - /* Insert a wait for idle packet before reading the registers. - * This is to fix a hang/reset seen during stress testing. In this - * hang, CP encountered a timeout reading SQ's boolean constant - * register. There is logic in the HW that blocks reading of this - * register when the SQ block is not idle, which we believe is - * contributing to the hang.*/ - *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmd++ = 0; - /* H/w registers are already shadowed; just need to disable shadowing - * to prevent corruption. - */ - *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); - *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; - *cmd++ = 4 << 16; /* regs, start=0 */ - *cmd++ = 0x0; /* count = 0 */ - - /* ALU constants are already shadowed; just need to disable shadowing - * to prevent corruption. - */ - *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); - *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; - *cmd++ = 0 << 16; /* ALU, start=0 */ - *cmd++ = 0x0; /* count = 0 */ - - /* Tex constants are already shadowed; just need to disable shadowing - * to prevent corruption. - */ - *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); - *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; - *cmd++ = 1 << 16; /* Tex, start=0 */ - *cmd++ = 0x0; /* count = 0 */ -#endif - - /* Need to handle some of the registers separately */ - *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmd++ = REG_SQ_GPR_MANAGEMENT; - *cmd++ = ctx->reg_values[0]; - - *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmd++ = REG_TP0_CHICKEN; - *cmd++ = ctx->reg_values[1]; - - *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmd++ = REG_RBBM_PM_OVERRIDE1; - *cmd++ = ctx->reg_values[2]; - - *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmd++ = REG_RBBM_PM_OVERRIDE2; - *cmd++ = ctx->reg_values[3]; - - /* Copy Boolean constants */ - cmd = reg_to_mem(cmd, ctx->bool_shadow, REG_SQ_CF_BOOLEANS, - BOOL_CONSTANTS); - - /* Copy Loop constants */ - cmd = reg_to_mem(cmd, ctx->loop_shadow, REG_SQ_CF_LOOP, LOOP_CONSTANTS); - - /* Restore RBBM_PM_OVERRIDE1 */ - *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmd++ = 0; - *cmd++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - *cmd++ = pm_override1; - - /* create indirect buffer command for above command sequence */ - create_ib1(drawctxt, drawctxt->reg_save, start, cmd); - - ctx->cmd = cmd; -} - -/*copy colour, depth, & stencil buffers from graphics memory to system memory*/ -static unsigned int *build_gmem2sys_cmds(struct kgsl_device *device, - struct kgsl_drawctxt *drawctxt, - struct tmp_ctx *ctx, - struct gmem_shadow_t *shadow) -{ - unsigned int *cmds = shadow->gmem_save_commands; - unsigned int *start = cmds; - unsigned int pm_override1; - /* Calculate the new offset based on the adjusted base */ - unsigned int bytesperpixel = format2bytesperpixel[shadow->format]; - unsigned int addr = - (shadow->gmemshadow.gpuaddr + shadow->offset * bytesperpixel); - unsigned int offset = (addr - (addr & 0xfffff000)) / bytesperpixel; - - kgsl_yamato_regread(device, REG_RBBM_PM_OVERRIDE1, &pm_override1); - - /* Store TP0_CHICKEN register */ - *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmds++ = REG_TP0_CHICKEN; - if (ctx) - *cmds++ = ctx->chicken_restore; - else - cmds++; - - *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmds++ = 0; - - /* Enable clock override for REG_FIFOS_SCLK */ - *cmds++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - *cmds++ = pm_override1 | (1 << 6); - - /* Set TP0_CHICKEN to zero */ - *cmds++ = pm4_type0_packet(REG_TP0_CHICKEN, 1); - *cmds++ = 0x00000000; - - /* Set PA_SC_AA_CONFIG to 0 */ - *cmds++ = pm4_type0_packet(REG_PA_SC_AA_CONFIG, 1); - *cmds++ = 0x00000000; - - /* program shader */ - - /* load shader vtx constants ... 5 dwords */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); - *cmds++ = (0x1 << 16) | SHADER_CONST_ADDR; - *cmds++ = 0; - /* valid(?) vtx constant flag & addr */ - *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; - /* limit = 12 dwords */ - *cmds++ = 0x00000030; - - /* Invalidate L2 cache to make sure vertices are updated */ - *cmds++ = pm4_type0_packet(REG_TC_CNTL_STATUS, 1); - *cmds++ = 0x1; - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); - *cmds++ = PM4_REG(REG_VGT_MAX_VTX_INDX); - *cmds++ = 0x00ffffff; /* REG_VGT_MAX_VTX_INDX */ - *cmds++ = 0x0; /* REG_VGT_MIN_VTX_INDX */ - *cmds++ = 0x00000000; /* REG_VGT_INDX_OFFSET */ - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_PA_SC_AA_MASK); - *cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */ - - /* load the patched vertex shader stream */ - cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN); - - /* Load the patched fragment shader stream */ - cmds = - program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN); - - /* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_SQ_PROGRAM_CNTL); - *cmds++ = 0x10010001; - *cmds++ = 0x00000008; - - /* resolve */ - - /* PA_CL_VTE_CNTL */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_PA_CL_VTE_CNTL); - /* disable X/Y/Z transforms, X/Y/Z are premultiplied by W */ - *cmds++ = 0x00000b00; - - /* program surface info */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_RB_SURFACE_INFO); - *cmds++ = shadow->gmem_pitch; /* pitch, MSAA = 1 */ - - /* RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0, - * Base=gmem_base - */ - /* gmem base assumed 4K aligned. */ - if (ctx) { - BUG_ON(ctx->gmem_base & 0xFFF); - *cmds++ = - (shadow-> - format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx-> - gmem_base; - } else { - unsigned int temp = *cmds; - *cmds++ = (temp & ~RB_COLOR_INFO__COLOR_FORMAT_MASK) | - (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT); - } - - /* disable Z */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_RB_DEPTHCONTROL); - *cmds++ = 0; - - /* set REG_PA_SU_SC_MODE_CNTL - * Front_ptype = draw triangles - * Back_ptype = draw triangles - * Provoking vertex = last - */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_PA_SU_SC_MODE_CNTL); - *cmds++ = 0x00080240; - - /* Use maximum scissor values -- quad vertices already have the - * correct bounds */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_PA_SC_SCREEN_SCISSOR_TL); - *cmds++ = (0 << 16) | 0; - *cmds++ = (0x1fff << 16) | (0x1fff); - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_PA_SC_WINDOW_SCISSOR_TL); - *cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0); - *cmds++ = (0x1fff << 16) | (0x1fff); - - /* load the viewport so that z scale = clear depth and - * z offset = 0.0f - */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_PA_CL_VPORT_ZSCALE); - *cmds++ = 0xbf800000; /* -1.0f */ - *cmds++ = 0x0; - - /* load the stencil ref value - * $AAM - do this later - */ - - /* load the COPY state */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 6); - *cmds++ = PM4_REG(REG_RB_COPY_CONTROL); - *cmds++ = 0; /* RB_COPY_CONTROL */ - *cmds++ = addr & 0xfffff000; /* RB_COPY_DEST_BASE */ - *cmds++ = shadow->pitch >> 5; /* RB_COPY_DEST_PITCH */ - - /* Endian=none, Linear, Format=RGBA8888,Swap=0,!Dither, - * MaskWrite:R=G=B=A=1 - */ - *cmds++ = 0x0003c008 | - (shadow->format << RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT); - /* Make sure we stay in offsetx field. */ - BUG_ON(offset & 0xfffff000); - *cmds++ = offset; - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_RB_MODECONTROL); - *cmds++ = 0x6; /* EDRAM copy */ - - /* queue the draw packet */ - *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2); - *cmds++ = 0; /* viz query info. */ - /* PrimType=RectList, NumIndices=3, SrcSel=AutoIndex */ - *cmds++ = 0x00030088; - - /* Restore RBBM_PM_OVERRIDE1 */ - *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmds++ = 0; - *cmds++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - *cmds++ = pm_override1; - /* create indirect buffer command for above command sequence */ - create_ib1(drawctxt, shadow->gmem_save, start, cmds); - - return cmds; -} - -/* context restore */ - -/*copy colour, depth, & stencil buffers from system memory to graphics memory*/ -static unsigned int *build_sys2gmem_cmds(struct kgsl_device *device, - struct kgsl_drawctxt *drawctxt, - struct tmp_ctx *ctx, - struct gmem_shadow_t *shadow) -{ - unsigned int *cmds = shadow->gmem_restore_commands; - unsigned int *start = cmds; - unsigned int pm_override1; - - kgsl_yamato_regread(device, REG_RBBM_PM_OVERRIDE1, &pm_override1); - - /* Store TP0_CHICKEN register */ - *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmds++ = REG_TP0_CHICKEN; - if (ctx) - *cmds++ = ctx->chicken_restore; - else - cmds++; - - *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmds++ = 0; - - /* Enable clock override for REG_FIFOS_SCLK */ - *cmds++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - *cmds++ = pm_override1 | (1 << 6); - - /* Set TP0_CHICKEN to zero */ - *cmds++ = pm4_type0_packet(REG_TP0_CHICKEN, 1); - *cmds++ = 0x00000000; - - /* Set PA_SC_AA_CONFIG to 0 */ - *cmds++ = pm4_type0_packet(REG_PA_SC_AA_CONFIG, 1); - *cmds++ = 0x00000000; - /* shader constants */ - - /* vertex buffer constants */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 7); - - *cmds++ = (0x1 << 16) | (9 * 6); - /* valid(?) vtx constant flag & addr */ - *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; - /* limit = 12 dwords */ - *cmds++ = 0x00000030; - /* valid(?) vtx constant flag & addr */ - *cmds++ = shadow->quad_texcoords.gpuaddr | 0x3; - /* limit = 8 dwords */ - *cmds++ = 0x00000020; - *cmds++ = 0; - *cmds++ = 0; - - /* Invalidate L2 cache to make sure vertices are updated */ - *cmds++ = pm4_type0_packet(REG_TC_CNTL_STATUS, 1); - *cmds++ = 0x1; - - cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN); - - /* Load the patched fragment shader stream */ - cmds = - program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN); - - /* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_SQ_PROGRAM_CNTL); - *cmds++ = 0x10030002; - *cmds++ = 0x00000008; - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_PA_SC_AA_MASK); - *cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */ - - /* PA_SC_VIZ_QUERY */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_PA_SC_VIZ_QUERY); - *cmds++ = 0x0; /*REG_PA_SC_VIZ_QUERY */ - - /* RB_COLORCONTROL */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_RB_COLORCONTROL); - *cmds++ = 0x00000c20; - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); - *cmds++ = PM4_REG(REG_VGT_MAX_VTX_INDX); - *cmds++ = 0x00ffffff; /* mmVGT_MAX_VTX_INDX */ - *cmds++ = 0x0; /* mmVGT_MIN_VTX_INDX */ - *cmds++ = 0x00000000; /* mmVGT_INDX_OFFSET */ - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL); - *cmds++ = 0x00000002; /* mmVGT_VERTEX_REUSE_BLOCK_CNTL */ - *cmds++ = 0x00000002; /* mmVGT_OUT_DEALLOC_CNTL */ - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_SQ_INTERPOLATOR_CNTL); - //*cmds++ = 0x0000ffff; //mmSQ_INTERPOLATOR_CNTL - *cmds++ = 0xffffffff; //mmSQ_INTERPOLATOR_CNTL - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_PA_SC_AA_CONFIG); - *cmds++ = 0x00000000; /* REG_PA_SC_AA_CONFIG */ - - /* set REG_PA_SU_SC_MODE_CNTL - * Front_ptype = draw triangles - * Back_ptype = draw triangles - * Provoking vertex = last - */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_PA_SU_SC_MODE_CNTL); - *cmds++ = 0x00080240; - - /* texture constants */ - *cmds++ = - pm4_type3_packet(PM4_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1)); - *cmds++ = (0x1 << 16) | (0 * 6); - memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN << 2); - cmds[0] |= (shadow->pitch >> 5) << 22; - cmds[1] |= - shadow->gmemshadow.gpuaddr | surface_format_table[shadow->format]; - cmds[2] |= - (shadow->width + shadow->offset_x - 1) | (shadow->height + - shadow->offset_y - - 1) << 13; - cmds += SYS2GMEM_TEX_CONST_LEN; - - /* program surface info */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_RB_SURFACE_INFO); - *cmds++ = shadow->gmem_pitch; /* pitch, MSAA = 1 */ - - /* RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0, - * Base=gmem_base - */ - if (ctx) - *cmds++ = - (shadow-> - format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx-> - gmem_base; - else { - unsigned int temp = *cmds; - *cmds++ = (temp & ~RB_COLOR_INFO__COLOR_FORMAT_MASK) | - (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT); - } - - /* RB_DEPTHCONTROL */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_RB_DEPTHCONTROL); - *cmds++ = 0; /* disable Z */ - - /* Use maximum scissor values -- quad vertices already - * have the correct bounds */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_PA_SC_SCREEN_SCISSOR_TL); - *cmds++ = (0 << 16) | 0; - *cmds++ = ((0x1fff) << 16) | 0x1fff; - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_PA_SC_WINDOW_SCISSOR_TL); - *cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0); - *cmds++ = ((0x1fff) << 16) | 0x1fff; - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_PA_CL_VTE_CNTL); - /* disable X/Y/Z transforms, X/Y/Z are premultiplied by W */ - *cmds++ = 0x00000b00; - - /*load the viewport so that z scale = clear depth and z offset = 0.0f */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_PA_CL_VPORT_ZSCALE); - *cmds++ = 0xbf800000; - *cmds++ = 0x0; - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_RB_COLOR_MASK); - *cmds++ = 0x0000000f; /* R = G = B = 1:enabled */ - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_RB_COLOR_DEST_MASK); - *cmds++ = 0xffffffff; - - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); - *cmds++ = PM4_REG(REG_SQ_WRAPPING_0); - *cmds++ = 0x00000000; - *cmds++ = 0x00000000; - - /* load the stencil ref value - * $AAM - do this later - */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = PM4_REG(REG_RB_MODECONTROL); - /* draw pixels with color and depth/stencil component */ - *cmds++ = 0x4; - - /* queue the draw packet */ - *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2); - *cmds++ = 0; /* viz query info. */ - /* PrimType=RectList, NumIndices=3, SrcSel=AutoIndex */ - *cmds++ = 0x00030088; - - /* Restore RBBM_PM_OVERRIDE1 */ - *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmds++ = 0; - *cmds++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - *cmds++ = pm_override1; - - /* create indirect buffer command for above command sequence */ - create_ib1(drawctxt, shadow->gmem_restore, start, cmds); - - return cmds; -} - -/* restore h/w regs, alu constants, texture constants, etc. ... */ -static unsigned *reg_range(unsigned int *cmd, unsigned int start, - unsigned int end) -{ - *cmd++ = PM4_REG(start); /* h/w regs, start addr */ - *cmd++ = end - start + 1; /* count */ - return cmd; -} - -static void build_regrestore_cmds(struct kgsl_device *device, - struct kgsl_drawctxt *drawctxt, - struct tmp_ctx *ctx) -{ - unsigned int *start = ctx->cmd; - unsigned int *cmd = start; - unsigned int pm_override1; - - kgsl_yamato_regread(device, REG_RBBM_PM_OVERRIDE1, &pm_override1); - - *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmd++ = 0; - - /* Enable clock override for REG_FIFOS_SCLK */ - *cmd++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - *cmd++ = pm_override1 | (1 << 6); - - /* H/W Registers */ - /* deferred pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, ???); */ - cmd++; -#ifdef DISABLE_SHADOW_WRITES - /* Force mismatch */ - *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; -#else - *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; -#endif - - cmd = reg_range(cmd, REG_RB_SURFACE_INFO, REG_PA_SC_SCREEN_SCISSOR_BR); - cmd = reg_range(cmd, REG_PA_SC_WINDOW_OFFSET, - REG_PA_SC_WINDOW_SCISSOR_BR); - cmd = reg_range(cmd, REG_VGT_MAX_VTX_INDX, REG_PA_CL_VPORT_ZOFFSET); - cmd = reg_range(cmd, REG_SQ_PROGRAM_CNTL, REG_SQ_WRAPPING_1); - cmd = reg_range(cmd, REG_RB_DEPTHCONTROL, REG_RB_MODECONTROL); - cmd = reg_range(cmd, REG_PA_SU_POINT_SIZE, - REG_PA_SC_VIZ_QUERY); /*REG_VGT_ENHANCE */ - cmd = reg_range(cmd, REG_PA_SC_LINE_CNTL, REG_RB_COLOR_DEST_MASK); - cmd = reg_range(cmd, REG_PA_SU_POLY_OFFSET_FRONT_SCALE, - REG_PA_SU_POLY_OFFSET_BACK_OFFSET); - - /* Now we know how many register blocks we have, we can compute command - * length - */ - start[4] = - pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, (cmd - start) - 5); - /* Enable shadowing for the entire register block. */ -#ifdef DISABLE_SHADOW_WRITES - start[6] |= (0 << 24) | (4 << 16); /* Disable shadowing. */ -#else - start[6] |= (1 << 24) | (4 << 16); -#endif - - /* Need to handle some of the registers separately */ - *cmd++ = pm4_type0_packet(REG_SQ_GPR_MANAGEMENT, 1); - ctx->reg_values[0] = gpuaddr(cmd, &drawctxt->gpustate); - *cmd++ = 0x00040400; - - *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmd++ = 0; - *cmd++ = pm4_type0_packet(REG_TP0_CHICKEN, 1); - ctx->reg_values[1] = gpuaddr(cmd, &drawctxt->gpustate); - *cmd++ = 0x00000000; - - *cmd++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - ctx->reg_values[2] = gpuaddr(cmd, &drawctxt->gpustate); - *cmd++ = 0x00000000; - - *cmd++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE2, 1); - ctx->reg_values[3] = gpuaddr(cmd, &drawctxt->gpustate); - *cmd++ = 0x00000000; - - /* ALU Constants */ - *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); - *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; -#ifdef DISABLE_SHADOW_WRITES - *cmd++ = (0 << 24) | (0 << 16) | 0; /* Disable shadowing */ -#else - *cmd++ = (1 << 24) | (0 << 16) | 0; -#endif - *cmd++ = ALU_CONSTANTS; - - /* Texture Constants */ - *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); - *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; -#ifdef DISABLE_SHADOW_WRITES - /* Disable shadowing */ - *cmd++ = (0 << 24) | (1 << 16) | 0; -#else - *cmd++ = (1 << 24) | (1 << 16) | 0; -#endif - *cmd++ = TEX_CONSTANTS; - - /* Boolean Constants */ - *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + BOOL_CONSTANTS); - *cmd++ = (2 << 16) | 0; - - /* the next BOOL_CONSTANT dwords is the shadow area for - * boolean constants. - */ - ctx->bool_shadow = gpuaddr(cmd, &drawctxt->gpustate); - cmd += BOOL_CONSTANTS; - - /* Loop Constants */ - *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + LOOP_CONSTANTS); - *cmd++ = (3 << 16) | 0; - - /* the next LOOP_CONSTANTS dwords is the shadow area for - * loop constants. - */ - ctx->loop_shadow = gpuaddr(cmd, &drawctxt->gpustate); - cmd += LOOP_CONSTANTS; - - /* Restore RBBM_PM_OVERRIDE1 */ - *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmd++ = 0; - *cmd++ = pm4_type0_packet(REG_RBBM_PM_OVERRIDE1, 1); - *cmd++ = pm_override1; - - /* create indirect buffer command for above command sequence */ - create_ib1(drawctxt, drawctxt->reg_restore, start, cmd); - - ctx->cmd = cmd; -} - -/* quad for saving/restoring gmem */ -static void set_gmem_copy_quad(struct gmem_shadow_t *shadow) -{ - /* set vertex buffer values */ - gmem_copy_quad[1] = uint2float(shadow->height + shadow->gmem_offset_y); - gmem_copy_quad[3] = uint2float(shadow->width + shadow->gmem_offset_x); - gmem_copy_quad[4] = uint2float(shadow->height + shadow->gmem_offset_y); - gmem_copy_quad[9] = uint2float(shadow->width + shadow->gmem_offset_x); - - gmem_copy_quad[0] = uint2float(shadow->gmem_offset_x); - gmem_copy_quad[6] = uint2float(shadow->gmem_offset_x); - gmem_copy_quad[7] = uint2float(shadow->gmem_offset_y); - gmem_copy_quad[10] = uint2float(shadow->gmem_offset_y); - - BUG_ON(shadow->offset_x); - BUG_ON(shadow->offset_y); - - memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2); - - memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord, - TEXCOORD_LEN << 2); -} - -/* quad for saving/restoring gmem */ -static void build_quad_vtxbuff(struct kgsl_drawctxt *drawctxt, - struct tmp_ctx *ctx, struct gmem_shadow_t *shadow) -{ - unsigned int *cmd = ctx->cmd; - - /* quad vertex buffer location (in GPU space) */ - shadow->quad_vertices.hostptr = cmd; - shadow->quad_vertices.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate); - - cmd += QUAD_LEN; - - /* tex coord buffer location (in GPU space) */ - shadow->quad_texcoords.hostptr = cmd; - shadow->quad_texcoords.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate); - - cmd += TEXCOORD_LEN; - - set_gmem_copy_quad(shadow); - - ctx->cmd = cmd; -} - -static void -build_shader_save_restore_cmds(struct kgsl_drawctxt *drawctxt, - struct tmp_ctx *ctx) -{ - unsigned int *cmd = ctx->cmd; - unsigned int *save, *restore, *fixup; -#if defined(PM4_IM_STORE) - unsigned int *startSizeVtx, *startSizePix, *startSizeShared; -#endif - unsigned int *partition1; - unsigned int *shaderBases, *partition2; - -#if defined(PM4_IM_STORE) - /* compute vertex, pixel and shared instruction shadow GPU addresses */ - ctx->shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET; - ctx->shader_pixel = ctx->shader_vertex + SHADER_SHADOW_SIZE; - ctx->shader_shared = ctx->shader_pixel + SHADER_SHADOW_SIZE; -#endif - - /* restore shader partitioning and instructions */ - - restore = cmd; /* start address */ - - /* Invalidate Vertex & Pixel instruction code address and sizes */ - *cmd++ = pm4_type3_packet(PM4_INVALIDATE_STATE, 1); - *cmd++ = 0x00000300; /* 0x100 = Vertex, 0x200 = Pixel */ - - /* Restore previous shader vertex & pixel instruction bases. */ - *cmd++ = pm4_type3_packet(PM4_SET_SHADER_BASES, 1); - shaderBases = cmd++; /* TBD #5: shader bases (from fixup) */ - - /* write the shader partition information to a scratch register */ - *cmd++ = pm4_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1); - partition1 = cmd++; /* TBD #4a: partition info (from save) */ - -#if defined(PM4_IM_STORE) - /* load vertex shader instructions from the shadow. */ - *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); - *cmd++ = ctx->shader_vertex + 0x0; /* 0x0 = Vertex */ - startSizeVtx = cmd++; /* TBD #1: start/size (from save) */ - - /* load pixel shader instructions from the shadow. */ - *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); - *cmd++ = ctx->shader_pixel + 0x1; /* 0x1 = Pixel */ - startSizePix = cmd++; /* TBD #2: start/size (from save) */ - - /* load shared shader instructions from the shadow. */ - *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); - *cmd++ = ctx->shader_shared + 0x2; /* 0x2 = Shared */ - startSizeShared = cmd++; /* TBD #3: start/size (from save) */ -#endif - - /* create indirect buffer command for above command sequence */ - create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd); - - /* - * fixup SET_SHADER_BASES data - * - * since self-modifying PM4 code is being used here, a seperate - * command buffer is used for this fixup operation, to ensure the - * commands are not read by the PM4 engine before the data fields - * have been written. - */ - - fixup = cmd; /* start address */ - - /* write the shader partition information to a scratch register */ - *cmd++ = pm4_type0_packet(REG_SCRATCH_REG2, 1); - partition2 = cmd++; /* TBD #4b: partition info (from save) */ - - /* mask off unused bits, then OR with shader instruction memory size */ - *cmd++ = pm4_type3_packet(PM4_REG_RMW, 3); - *cmd++ = REG_SCRATCH_REG2; - /* AND off invalid bits. */ - *cmd++ = 0x0FFF0FFF; - /* OR in instruction memory size */ - *cmd++ = (unsigned int)((SHADER_INSTRUCT_LOG2 - 5U) << 29); - - /* write the computed value to the SET_SHADER_BASES data field */ - *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmd++ = REG_SCRATCH_REG2; - /* TBD #5: shader bases (to restore) */ - *cmd++ = gpuaddr(shaderBases, &drawctxt->gpustate); - - /* create indirect buffer command for above command sequence */ - create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd); - - /* save shader partitioning and instructions */ - - save = cmd; /* start address */ - - *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmd++ = 0; - - /* fetch the SQ_INST_STORE_MANAGMENT register value, - * store the value in the data fields of the SET_CONSTANT commands - * above. - */ - *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmd++ = REG_SQ_INST_STORE_MANAGMENT; - /* TBD #4a: partition info (to restore) */ - *cmd++ = gpuaddr(partition1, &drawctxt->gpustate); - *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); - *cmd++ = REG_SQ_INST_STORE_MANAGMENT; - /* TBD #4b: partition info (to fixup) */ - *cmd++ = gpuaddr(partition2, &drawctxt->gpustate); - -#if defined(PM4_IM_STORE) - - /* store the vertex shader instructions */ - *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); - *cmd++ = ctx->shader_vertex + 0x0; /* 0x0 = Vertex */ - /* TBD #1: start/size (to restore) */ - *cmd++ = gpuaddr(startSizeVtx, &drawctxt->gpustate); - - /* store the pixel shader instructions */ - *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); - *cmd++ = ctx->shader_pixel + 0x1; /* 0x1 = Pixel */ - /* TBD #2: start/size (to restore) */ - *cmd++ = gpuaddr(startSizePix, &drawctxt->gpustate); - - /* store the shared shader instructions if vertex base is nonzero */ - - *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); - *cmd++ = ctx->shader_shared + 0x2; /* 0x2 = Shared */ - /* TBD #3: start/size (to restore) */ - *cmd++ = gpuaddr(startSizeShared, &drawctxt->gpustate); - -#endif - - *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmd++ = 0; - - /* create indirect buffer command for above command sequence */ - create_ib1(drawctxt, drawctxt->shader_save, save, cmd); - - ctx->cmd = cmd; -} - -/* create buffers for saving/restoring registers, constants, & GMEM */ -static int -create_gpustate_shadow(struct kgsl_device *device, - struct kgsl_drawctxt *drawctxt, struct tmp_ctx *ctx) -{ - uint32_t flags; - - flags = (KGSL_MEMFLAGS_CONPHYS | KGSL_MEMFLAGS_ALIGN8K); - - /* allocate memory to allow HW to save sub-blocks for efficient context - * save/restore - */ - if (kgsl_sharedmem_alloc(flags, CONTEXT_SIZE, &drawctxt->gpustate) != 0) - return -ENOMEM; - if (kgsl_mmu_map(drawctxt->pagetable, drawctxt->gpustate.physaddr, - drawctxt->gpustate.size, - GSL_PT_PAGE_RV | GSL_PT_PAGE_WV, - &drawctxt->gpustate.gpuaddr, - KGSL_MEMFLAGS_CONPHYS | KGSL_MEMFLAGS_ALIGN8K)) - return -EINVAL; - - drawctxt->flags |= CTXT_FLAGS_STATE_SHADOW; - - /* Blank out h/w register, constant, and command buffer shadows. */ - kgsl_sharedmem_set(&drawctxt->gpustate, 0, 0, CONTEXT_SIZE); - - /* set-up command and vertex buffer pointers */ - ctx->cmd = ctx->start - = (unsigned int *)((char *)drawctxt->gpustate.hostptr + CMD_OFFSET); - - /* build indirect command buffers to save & restore regs/constants */ - kgsl_yamato_idle(device, KGSL_TIMEOUT_DEFAULT); - build_regrestore_cmds(device, drawctxt, ctx); - build_regsave_cmds(device, drawctxt, ctx); - - build_shader_save_restore_cmds(drawctxt, ctx); - - return 0; -} - -/* create buffers for saving/restoring registers, constants, & GMEM */ -static int -create_gmem_shadow(struct kgsl_device *device, struct kgsl_drawctxt *drawctxt, - struct tmp_ctx *ctx) -{ - unsigned int flags = KGSL_MEMFLAGS_CONPHYS | KGSL_MEMFLAGS_ALIGN8K, i; - - config_gmemsize(&drawctxt->context_gmem_shadow, - device->gmemspace.sizebytes); - ctx->gmem_base = device->gmemspace.gpu_base; - - /* allocate memory for GMEM shadow */ - if (kgsl_sharedmem_alloc(flags, drawctxt->context_gmem_shadow.size, - &drawctxt->context_gmem_shadow.gmemshadow) != - 0) - return -ENOMEM; - if (kgsl_mmu_map(drawctxt->pagetable, - drawctxt->context_gmem_shadow.gmemshadow.physaddr, - drawctxt->context_gmem_shadow.gmemshadow.size, - GSL_PT_PAGE_RV | GSL_PT_PAGE_WV, - &drawctxt->context_gmem_shadow.gmemshadow.gpuaddr, - KGSL_MEMFLAGS_CONPHYS | KGSL_MEMFLAGS_ALIGN8K)) - return -EINVAL; - - /* we've allocated the shadow, when swapped out, GMEM must be saved. */ - drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW | CTXT_FLAGS_GMEM_SAVE; - - /* blank out gmem shadow. */ - kgsl_sharedmem_set(&drawctxt->context_gmem_shadow.gmemshadow, 0, 0, - drawctxt->context_gmem_shadow.size); - - /* build quad vertex buffer */ - build_quad_vtxbuff(drawctxt, ctx, &drawctxt->context_gmem_shadow); - - /* build TP0_CHICKEN register restore command buffer */ - ctx->cmd = build_chicken_restore_cmds(drawctxt, ctx); - - /* build indirect command buffers to save & restore gmem */ - /* Idle because we are reading PM override registers */ - kgsl_yamato_idle(device, KGSL_TIMEOUT_DEFAULT); - drawctxt->context_gmem_shadow.gmem_save_commands = ctx->cmd; - ctx->cmd = - build_gmem2sys_cmds(device, drawctxt, ctx, - &drawctxt->context_gmem_shadow); - drawctxt->context_gmem_shadow.gmem_restore_commands = ctx->cmd; - ctx->cmd = - build_sys2gmem_cmds(device, drawctxt, ctx, - &drawctxt->context_gmem_shadow); - - for (i = 0; i < KGSL_MAX_GMEM_SHADOW_BUFFERS; i++) { - build_quad_vtxbuff(drawctxt, ctx, - &drawctxt->user_gmem_shadow[i]); - - drawctxt->user_gmem_shadow[i].gmem_save_commands = ctx->cmd; - ctx->cmd = - build_gmem2sys_cmds(device, drawctxt, ctx, - &drawctxt->user_gmem_shadow[i]); - - drawctxt->user_gmem_shadow[i].gmem_restore_commands = ctx->cmd; - ctx->cmd = - build_sys2gmem_cmds(device, drawctxt, ctx, - &drawctxt->user_gmem_shadow[i]); - } - - return 0; -} - -/* init draw context */ - -int kgsl_drawctxt_init(struct kgsl_device *device) -{ - return 0; -} - -/* close draw context */ -int kgsl_drawctxt_close(struct kgsl_device *device) -{ - return 0; -} - -/* create a new drawing context */ - -int -kgsl_drawctxt_create(struct kgsl_device *device, - struct kgsl_pagetable *pagetable, - unsigned int flags, unsigned int *drawctxt_id) -{ - struct kgsl_drawctxt *drawctxt; - int index; - struct tmp_ctx ctx; - - KGSL_CTXT_INFO("pt %p flags %08x\n", pagetable, flags); - if (device->drawctxt_count >= KGSL_CONTEXT_MAX) - return -EINVAL; - - /* find a free context slot */ - index = 0; - while (index < KGSL_CONTEXT_MAX) { - if (device->drawctxt[index].flags == CTXT_FLAGS_NOT_IN_USE) - break; - - index++; - } - - if (index >= KGSL_CONTEXT_MAX) - return -EINVAL; - - drawctxt = &device->drawctxt[index]; - drawctxt->pagetable = pagetable; - drawctxt->flags = CTXT_FLAGS_IN_USE; - drawctxt->bin_base_offset = 0; - - device->drawctxt_count++; - - if (create_gpustate_shadow(device, drawctxt, &ctx) - != 0) { - kgsl_drawctxt_destroy(device, index); - return -EINVAL; - } - - /* Save the shader instruction memory on context switching */ - drawctxt->flags |= CTXT_FLAGS_SHADER_SAVE; - - if (!(flags & KGSL_CONTEXT_NO_GMEM_ALLOC)) { - /* create gmem shadow */ - memset(drawctxt->user_gmem_shadow, 0, - sizeof(struct gmem_shadow_t) * - KGSL_MAX_GMEM_SHADOW_BUFFERS); - - if (create_gmem_shadow(device, drawctxt, &ctx) - != 0) { - kgsl_drawctxt_destroy(device, index); - return -EINVAL; - } - } - - BUG_ON(ctx.cmd - ctx.start > CMD_BUFFER_LEN); - - *drawctxt_id = index; - - KGSL_CTXT_INFO("return drawctxt_id %d\n", *drawctxt_id); - return 0; -} - -/* destroy a drawing context */ - -int kgsl_drawctxt_destroy(struct kgsl_device *device, unsigned int drawctxt_id) -{ - struct kgsl_drawctxt *drawctxt; - - drawctxt = &device->drawctxt[drawctxt_id]; - - KGSL_CTXT_INFO("drawctxt_id %d ptr %p\n", drawctxt_id, drawctxt); - if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE) { - /* deactivate context */ - if (device->drawctxt_active == drawctxt) { - /* no need to save GMEM or shader, the context is - * being destroyed. - */ - drawctxt->flags &= ~(CTXT_FLAGS_GMEM_SAVE | - CTXT_FLAGS_SHADER_SAVE | - CTXT_FLAGS_GMEM_SHADOW | - CTXT_FLAGS_STATE_SHADOW); - - kgsl_drawctxt_switch(device, NULL, 0); - } - - kgsl_yamato_idle(device, KGSL_TIMEOUT_DEFAULT); - - /* destroy state shadow, if allocated */ - if (drawctxt->gpustate.gpuaddr != 0) { - kgsl_mmu_unmap(drawctxt->pagetable, - drawctxt->gpustate.gpuaddr, - drawctxt->gpustate.size); - drawctxt->gpustate.gpuaddr = 0; - } - if (drawctxt->gpustate.physaddr != 0) - kgsl_sharedmem_free(&drawctxt->gpustate); - - /* destroy gmem shadow, if allocated */ - if (drawctxt->context_gmem_shadow.gmemshadow.gpuaddr != 0) { - kgsl_mmu_unmap(drawctxt->pagetable, - drawctxt->context_gmem_shadow.gmemshadow.gpuaddr, - drawctxt->context_gmem_shadow.gmemshadow.size); - drawctxt->context_gmem_shadow.gmemshadow.gpuaddr = 0; - } - - if (drawctxt->context_gmem_shadow.gmemshadow.physaddr != 0) - kgsl_sharedmem_free(&drawctxt->context_gmem_shadow. - gmemshadow); - - drawctxt->flags = CTXT_FLAGS_NOT_IN_USE; - - BUG_ON(device->drawctxt_count == 0); - device->drawctxt_count--; - } - KGSL_CTXT_INFO("return\n"); - return 0; -} - -/* Binds a user specified buffer as GMEM shadow area */ -int kgsl_drawctxt_bind_gmem_shadow(struct kgsl_device *device, - unsigned int drawctxt_id, - const struct kgsl_gmem_desc *gmem_desc, - unsigned int shadow_x, - unsigned int shadow_y, - const struct kgsl_buffer_desc - *shadow_buffer, unsigned int buffer_id) -{ - struct kgsl_drawctxt *drawctxt; - - /* Shadow struct being modified */ - struct gmem_shadow_t *shadow; - unsigned int i; - - if (device->flags & KGSL_FLAGS_SAFEMODE) - /* No need to bind any buffers since safe mode - * skips context switch */ - return 0; - - drawctxt = &device->drawctxt[drawctxt_id]; - - shadow = &drawctxt->user_gmem_shadow[buffer_id]; - - if (!shadow_buffer->enabled) { - /* Disable shadow */ - KGSL_MEM_ERR("shadow is disabled in bind_gmem\n"); - shadow->gmemshadow.size = 0; - } else { - /* Binding to a buffer */ - unsigned int width, height; - - BUG_ON(gmem_desc->x % 2); /* Needs to be a multiple of 2 */ - BUG_ON(gmem_desc->y % 2); /* Needs to be a multiple of 2 */ - BUG_ON(gmem_desc->width % 2); /* Needs to be a multiple of 2 */ - /* Needs to be a multiple of 2 */ - BUG_ON(gmem_desc->height % 2); - /* Needs to be a multiple of 32 */ - BUG_ON(gmem_desc->pitch % 32); - - BUG_ON(shadow_x % 2); /* Needs to be a multiple of 2 */ - BUG_ON(shadow_y % 2); /* Needs to be a multiple of 2 */ - - BUG_ON(shadow_buffer->format < COLORX_4_4_4_4); - BUG_ON(shadow_buffer->format > COLORX_32_32_32_32_FLOAT); - /* Needs to be a multiple of 32 */ - BUG_ON(shadow_buffer->pitch % 32); - - BUG_ON(buffer_id < 0); - BUG_ON(buffer_id > KGSL_MAX_GMEM_SHADOW_BUFFERS); - - width = gmem_desc->width; - height = gmem_desc->height; - - shadow->width = width; - shadow->format = shadow_buffer->format; - - shadow->height = height; - shadow->pitch = shadow_buffer->pitch; - - memset(&shadow->gmemshadow, 0, sizeof(struct kgsl_memdesc)); - shadow->gmemshadow.hostptr = shadow_buffer->hostptr; - shadow->gmemshadow.gpuaddr = shadow_buffer->gpuaddr; - shadow->gmemshadow.physaddr = shadow->gmemshadow.gpuaddr; - shadow->gmemshadow.size = shadow_buffer->size; - - /* Calculate offset */ - shadow->offset = - (int)(shadow_buffer->pitch) * ((int)shadow_y - - (int)gmem_desc->y) + - (int)shadow_x - (int)gmem_desc->x; - - shadow->offset_x = shadow_x; - shadow->offset_y = shadow_y; - shadow->gmem_offset_x = gmem_desc->x; - shadow->gmem_offset_y = gmem_desc->y; - - shadow->size = shadow->gmemshadow.size; - - shadow->gmem_pitch = gmem_desc->pitch; - - /* Modify quad vertices */ - set_gmem_copy_quad(shadow); - - /* Idle because we are reading PM override registers */ - kgsl_yamato_idle(device, KGSL_TIMEOUT_DEFAULT); - - /* Modify commands */ - build_gmem2sys_cmds(device, drawctxt, NULL, shadow); - build_sys2gmem_cmds(device, drawctxt, NULL, shadow); - - /* Release context GMEM shadow if found */ - if (drawctxt->context_gmem_shadow.gmemshadow.physaddr != 0) { - kgsl_sharedmem_free(&drawctxt->context_gmem_shadow. - gmemshadow); - drawctxt->context_gmem_shadow.gmemshadow.physaddr = 0; - } - } - - /* Enable GMEM shadowing if we have any of the user buffers enabled */ - drawctxt->flags &= ~CTXT_FLAGS_GMEM_SHADOW; - for (i = 0; i < KGSL_MAX_GMEM_SHADOW_BUFFERS; i++) { - if (drawctxt->user_gmem_shadow[i].gmemshadow.size > 0) - drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW; - } - - return 0; -} - -/* set bin base offset */ -int kgsl_drawctxt_set_bin_base_offset(struct kgsl_device *device, - unsigned int drawctxt_id, - unsigned int offset) -{ - struct kgsl_drawctxt *drawctxt; - - drawctxt = &device->drawctxt[drawctxt_id]; - - drawctxt->bin_base_offset = offset; - - return 0; -} - -/* switch drawing contexts */ -void -kgsl_drawctxt_switch(struct kgsl_device *device, struct kgsl_drawctxt *drawctxt, - unsigned int flags) -{ - struct kgsl_drawctxt *active_ctxt = device->drawctxt_active; - unsigned int cmds[2]; - - if (drawctxt) { - /* Set the flag in context so that the save is done - * when this context is switched out. */ - if (flags & KGSL_CONTEXT_SAVE_GMEM) - drawctxt->flags |= CTXT_FLAGS_GMEM_SAVE; - else - drawctxt->flags &= ~CTXT_FLAGS_GMEM_SAVE; - } - /* already current? */ - if (active_ctxt == drawctxt) - return; - - KGSL_CTXT_INFO("from %p to %p flags %d\n", - device->drawctxt_active, drawctxt, flags); - /* save old context*/ - if (active_ctxt != NULL) { - KGSL_CTXT_INFO("active_ctxt flags %08x\n", active_ctxt->flags); - /* save registers and constants. */ - KGSL_CTXT_DBG("save regs"); - kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->reg_save, 3); - - if (active_ctxt->flags & CTXT_FLAGS_SHADER_SAVE) { - /* save shader partitioning and instructions. */ - KGSL_CTXT_DBG("save shader"); - kgsl_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE, - active_ctxt->shader_save, 3); - - /* fixup shader partitioning parameter for - * SET_SHADER_BASES. - */ - KGSL_CTXT_DBG("save shader fixup"); - kgsl_ringbuffer_issuecmds(device, 0, - active_ctxt->shader_fixup, 3); - - active_ctxt->flags |= CTXT_FLAGS_SHADER_RESTORE; - } - - if (active_ctxt->flags & CTXT_FLAGS_GMEM_SAVE - && active_ctxt->flags & CTXT_FLAGS_GMEM_SHADOW) { - /* save gmem. - * (note: changes shader. shader must already be saved.) - */ - unsigned int i, numbuffers = 0; - KGSL_CTXT_DBG("save gmem"); - for (i = 0; i < KGSL_MAX_GMEM_SHADOW_BUFFERS; i++) { - if (active_ctxt->user_gmem_shadow[i].gmemshadow. - size > 0) { - kgsl_ringbuffer_issuecmds(device, - KGSL_CMD_FLAGS_PMODE, - active_ctxt->user_gmem_shadow[i]. - gmem_save, 3); - - /* Restore TP0_CHICKEN */ - kgsl_ringbuffer_issuecmds(device, 0, - active_ctxt->chicken_restore, 3); - - numbuffers++; - } - } - if (numbuffers == 0) { - kgsl_ringbuffer_issuecmds(device, - KGSL_CMD_FLAGS_PMODE, - active_ctxt->context_gmem_shadow.gmem_save, - 3); - - /* Restore TP0_CHICKEN */ - kgsl_ringbuffer_issuecmds(device, 0, - active_ctxt->chicken_restore, 3); - } - - active_ctxt->flags |= CTXT_FLAGS_GMEM_RESTORE; - } - } - - device->drawctxt_active = drawctxt; - - /* restore new context */ - if (drawctxt != NULL) { - - KGSL_CTXT_INFO("drawctxt flags %08x\n", drawctxt->flags); - KGSL_CTXT_DBG("restore pagetable"); - kgsl_mmu_setstate(device, drawctxt->pagetable); - - /* restore gmem. - * (note: changes shader. shader must not already be restored.) - */ - if (drawctxt->flags & CTXT_FLAGS_GMEM_RESTORE) { - unsigned int i, numbuffers = 0; - KGSL_CTXT_DBG("restore gmem"); - - for (i = 0; i < KGSL_MAX_GMEM_SHADOW_BUFFERS; i++) { - if (drawctxt->user_gmem_shadow[i].gmemshadow. - size > 0) { - kgsl_ringbuffer_issuecmds(device, - KGSL_CMD_FLAGS_PMODE, - drawctxt->user_gmem_shadow[i]. - gmem_restore, 3); - - /* Restore TP0_CHICKEN */ - kgsl_ringbuffer_issuecmds(device, 0, - drawctxt->chicken_restore, 3); - numbuffers++; - } - } - if (numbuffers == 0) { - kgsl_ringbuffer_issuecmds(device, - KGSL_CMD_FLAGS_PMODE, - drawctxt->context_gmem_shadow.gmem_restore, - 3); - - /* Restore TP0_CHICKEN */ - kgsl_ringbuffer_issuecmds(device, 0, - drawctxt->chicken_restore, 3); - } - drawctxt->flags &= ~CTXT_FLAGS_GMEM_RESTORE; - } - - /* restore registers and constants. */ - KGSL_CTXT_DBG("restore regs"); - kgsl_ringbuffer_issuecmds(device, 0, - drawctxt->reg_restore, 3); - - /* restore shader instructions & partitioning. */ - if (drawctxt->flags & CTXT_FLAGS_SHADER_RESTORE) - KGSL_CTXT_DBG("restore shader"); - kgsl_ringbuffer_issuecmds(device, 0, - drawctxt->shader_restore, 3); - - cmds[0] = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1); - cmds[1] = drawctxt->bin_base_offset; - kgsl_ringbuffer_issuecmds(device, 0, cmds, 2); - - } else - kgsl_mmu_setstate(device, device->mmu.defaultpagetable); - KGSL_CTXT_INFO("return\n"); -} diff --git a/drivers/video/msm/gpu/kgsl/kgsl_drawctxt.h b/drivers/video/msm/gpu/kgsl/kgsl_drawctxt.h deleted file mode 100644 index 3090373e..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_drawctxt.h +++ /dev/null @@ -1,120 +0,0 @@ -/* -* (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 -* Copyright (c) 2008-2009 QUALCOMM USA, INC. -* -* All source code in this file is licensed under the following license -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* version 2 as published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -* See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, you can find it at http://www.fsf.org -*/ -#ifndef __GSL_DRAWCTXT_H -#define __GSL_DRAWCTXT_H - -/* Flags */ - -#define CTXT_FLAGS_NOT_IN_USE 0x00000000 -#define CTXT_FLAGS_IN_USE 0x00000001 - -/* state shadow memory allocated */ -#define CTXT_FLAGS_STATE_SHADOW 0x00000010 - -/* gmem shadow memory allocated */ -#define CTXT_FLAGS_GMEM_SHADOW 0x00000100 -/* gmem must be copied to shadow */ -#define CTXT_FLAGS_GMEM_SAVE 0x00000200 -/* gmem can be restored from shadow */ -#define CTXT_FLAGS_GMEM_RESTORE 0x00000400 -/* shader must be copied to shadow */ -#define CTXT_FLAGS_SHADER_SAVE 0x00002000 -/* shader can be restored from shadow */ -#define CTXT_FLAGS_SHADER_RESTORE 0x00004000 - -#include "kgsl_sharedmem.h" -#include "yamato_reg.h" - -#define KGSL_MAX_GMEM_SHADOW_BUFFERS 2 - -struct kgsl_device; - -/* types */ - -/* draw context */ -struct gmem_shadow_t { - struct kgsl_memdesc gmemshadow; /* Shadow buffer address */ - - /* 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x - * 256 rows. */ - /* width & height must be a multiples of 32, in case tiled textures - * are used. */ - enum COLORFORMATX format; - unsigned int size; /* Size of surface used to store GMEM */ - unsigned int width; /* Width of surface used to store GMEM */ - unsigned int height; /* Height of surface used to store GMEM */ - unsigned int pitch; /* Pitch of surface used to store GMEM */ - int offset; - unsigned int offset_x; - unsigned int offset_y; - unsigned int gmem_offset_x; - unsigned int gmem_offset_y; - unsigned int gmem_pitch; /* Pitch value used for GMEM */ - unsigned int *gmem_save_commands; - unsigned int *gmem_restore_commands; - unsigned int gmem_save[3]; - unsigned int gmem_restore[3]; - struct kgsl_memdesc quad_vertices; - struct kgsl_memdesc quad_texcoords; -}; - -struct kgsl_drawctxt { - uint32_t flags; - struct kgsl_pagetable *pagetable; - struct kgsl_memdesc gpustate; - unsigned int reg_save[3]; - unsigned int reg_restore[3]; - unsigned int shader_save[3]; - unsigned int shader_fixup[3]; - unsigned int shader_restore[3]; - unsigned int chicken_restore[3]; - unsigned int bin_base_offset; - /* Information of the GMEM shadow that is created in context create */ - struct gmem_shadow_t context_gmem_shadow; - /* User defined GMEM shadow buffers */ - struct gmem_shadow_t user_gmem_shadow[KGSL_MAX_GMEM_SHADOW_BUFFERS]; -}; - - -int kgsl_drawctxt_create(struct kgsl_device *, struct kgsl_pagetable *, - unsigned int flags, - unsigned int *drawctxt_id); - -int kgsl_drawctxt_destroy(struct kgsl_device *device, unsigned int drawctxt_id); - -int kgsl_drawctxt_init(struct kgsl_device *device); - -int kgsl_drawctxt_close(struct kgsl_device *device); - -void kgsl_drawctxt_switch(struct kgsl_device *device, - struct kgsl_drawctxt *drawctxt, - unsigned int flags); -int kgsl_drawctxt_bind_gmem_shadow(struct kgsl_device *device, - unsigned int drawctxt_id, - const struct kgsl_gmem_desc *gmem_desc, - unsigned int shadow_x, - unsigned int shadow_y, - const struct kgsl_buffer_desc - *shadow_buffer, unsigned int buffer_id); - -int kgsl_drawctxt_set_bin_base_offset(struct kgsl_device *device, - unsigned int drawctxt_id, - unsigned int offset); - -#endif /* __GSL_DRAWCTXT_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_log.c b/drivers/video/msm/gpu/kgsl/kgsl_log.c deleted file mode 100644 index d39f3447..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_log.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2008 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#include -#include "kgsl_log.h" -#include "kgsl_ringbuffer.h" -#include "kgsl_device.h" -#include "kgsl.h" - -/*default log levels is error for everything*/ -#define KGSL_LOG_LEVEL_DEFAULT 3 -#define KGSL_LOG_LEVEL_MAX 7 -unsigned int kgsl_drv_log = KGSL_LOG_LEVEL_DEFAULT; -unsigned int kgsl_cmd_log = KGSL_LOG_LEVEL_DEFAULT; -unsigned int kgsl_ctxt_log = KGSL_LOG_LEVEL_DEFAULT; -unsigned int kgsl_mem_log = KGSL_LOG_LEVEL_DEFAULT; - -unsigned int kgsl_cache_enable; - -#ifdef CONFIG_DEBUG_FS -static int kgsl_log_set(unsigned int *log_val, void *data, u64 val) -{ - *log_val = min((unsigned int)val, (unsigned int)KGSL_LOG_LEVEL_MAX); - return 0; -} - -static int kgsl_drv_log_set(void *data, u64 val) -{ - return kgsl_log_set(&kgsl_drv_log, data, val); -} - -static int kgsl_drv_log_get(void *data, u64 *val) -{ - *val = kgsl_drv_log; - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(kgsl_drv_log_fops, kgsl_drv_log_get, - kgsl_drv_log_set, "%llu\n"); - -static int kgsl_cmd_log_set(void *data, u64 val) -{ - return kgsl_log_set(&kgsl_cmd_log, data, val); -} - -static int kgsl_cmd_log_get(void *data, u64 *val) -{ - *val = kgsl_cmd_log; - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(kgsl_cmd_log_fops, kgsl_cmd_log_get, - kgsl_cmd_log_set, "%llu\n"); - -static int kgsl_ctxt_log_set(void *data, u64 val) -{ - return kgsl_log_set(&kgsl_ctxt_log, data, val); -} - -static int kgsl_ctxt_log_get(void *data, u64 *val) -{ - *val = kgsl_ctxt_log; - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(kgsl_ctxt_log_fops, kgsl_ctxt_log_get, - kgsl_ctxt_log_set, "%llu\n"); - -static int kgsl_mem_log_set(void *data, u64 val) -{ - return kgsl_log_set(&kgsl_mem_log, data, val); -} - -static int kgsl_mem_log_get(void *data, u64 *val) -{ - *val = kgsl_mem_log; - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(kgsl_mem_log_fops, kgsl_mem_log_get, - kgsl_mem_log_set, "%llu\n"); - -#ifdef DEBUG -static ssize_t rb_regs_open(struct inode *inode, struct file *file) -{ - file->private_data = inode->i_private; - return 0; -} - -static ssize_t rb_regs_read(struct file *file, char __user *buf, size_t count, - loff_t *ppos) -{ - const int debug_bufmax = 4096; - static char buffer[4096]; - int n = 0; - struct kgsl_device *device = NULL; - struct kgsl_ringbuffer *rb = NULL; - struct kgsl_rb_debug rb_debug; - - device = &kgsl_driver.yamato_device; - - rb = &device->ringbuffer; - - kgsl_ringbuffer_debug(rb, &rb_debug); - - n += scnprintf(buffer + n, debug_bufmax - n, - "rbbm_status %08x mem_rptr %08x mem_wptr_poll %08x\n", - rb_debug.rbbm_status, - rb_debug.mem_rptr, - rb_debug.mem_wptr_poll); - - n += scnprintf(buffer + n, debug_bufmax - n, - "rb_base %08x rb_cntl %08x rb_rptr_addr %08x" - " rb_rptr %08x rb_rptr_wr %08x\n", - rb_debug.cp_rb_base, - rb_debug.cp_rb_cntl, - rb_debug.cp_rb_rptr_addr, - rb_debug.cp_rb_rptr, - rb_debug.cp_rb_rptr_wr); - - n += scnprintf(buffer + n, debug_bufmax - n, - "rb_wptr %08x rb_wptr_delay %08x rb_wptr_base %08x" - " ib1_base %08x ib1_bufsz %08x\n", - rb_debug.cp_rb_wptr, - rb_debug.cp_rb_wptr_delay, - rb_debug.cp_rb_wptr_base, - rb_debug.cp_ib1_base, - rb_debug.cp_ib1_bufsz); - - n += scnprintf(buffer + n, debug_bufmax - n, - "ib2_base %08x ib2_bufsz %08x st_base %08x" - " st_bufsz %08x cp_me_cntl %08x cp_me_status %08x\n", - rb_debug.cp_ib2_base, - rb_debug.cp_ib2_bufsz, - rb_debug.cp_st_base, - rb_debug.cp_st_bufsz, - rb_debug.cp_me_cntl, - rb_debug.cp_me_status); - - n += scnprintf(buffer + n, debug_bufmax - n, - "csq_cp_rb %08x csq_cp_ib1 %08x csq_cp_ib2 %08x\n", - rb_debug.cp_csq_rb_stat, - rb_debug.cp_csq_ib1_stat, - rb_debug.cp_csq_ib2_stat); - - n += scnprintf(buffer + n, debug_bufmax - n, - "cp_debug %08x cp_stat %08x cp_int_status %08x" - " cp_int_cntl %08x\n", - rb_debug.cp_debug, - rb_debug.cp_stat, - rb_debug.cp_int_status, - rb_debug.cp_int_cntl); - - n += scnprintf(buffer + n, debug_bufmax - n, - "sop_timestamp: %0d eop_timestamp: %d\n", - rb_debug.sop_timestamp, - rb_debug.eop_timestamp); - n++; - buffer[n] = 0; - return simple_read_from_buffer(buf, count, ppos, buffer, n); -} - -static struct file_operations kgsl_rb_regs_fops = { - .read = rb_regs_read, - .open = rb_regs_open, -}; -#endif /*DEBUG*/ - -#ifdef DEBUG -static ssize_t mmu_regs_open(struct inode *inode, struct file *file) -{ - file->private_data = inode->i_private; - return 0; -} - -static ssize_t mmu_regs_read(struct file *file, char __user *buf, size_t count, - loff_t *ppos) -{ - const int debug_bufmax = 4096; - static char buffer[4096]; - int n = 0; - struct kgsl_device *device = NULL; - struct kgsl_mmu *mmu = NULL; - struct kgsl_mmu_debug mmu_debug; - - device = &kgsl_driver.yamato_device; - - mmu = &device->mmu; - - kgsl_mmu_debug(mmu, &mmu_debug); - - n += scnprintf(buffer + n, debug_bufmax - n, - "config %08x mpu_base %08x mpu_end %08x\n", - mmu_debug.config, - mmu_debug.mpu_base, - mmu_debug.mpu_end); - - n += scnprintf(buffer + n, debug_bufmax - n, - "va_range %08x pt_base %08x\n", - mmu_debug.va_range, - mmu_debug.pt_base); - - n += scnprintf(buffer + n, debug_bufmax - n, - "page_fault %08x trans_error %08x axi_error %08x\n", - mmu_debug.page_fault, - mmu_debug.trans_error, - mmu_debug.axi_error); - - n += scnprintf(buffer + n, debug_bufmax - n, - "interrupt_mask %08x interrupt_status %08x\n", - mmu_debug.interrupt_mask, - mmu_debug.interrupt_status); - - n++; - buffer[n] = 0; - return simple_read_from_buffer(buf, count, ppos, buffer, n); -} - -static struct file_operations kgsl_mmu_regs_fops = { - .read = mmu_regs_read, - .open = mmu_regs_open, -}; -#endif /*DEBUG*/ - -#ifdef CONFIG_GPU_MSM_KGSL_MMU -static int kgsl_cache_enable_set(void *data, u64 val) -{ - kgsl_cache_enable = (val != 0); - return 0; -} - -static int kgsl_cache_enable_get(void *data, u64 *val) -{ - *val = kgsl_cache_enable; - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(kgsl_cache_enable_fops, kgsl_cache_enable_get, - kgsl_cache_enable_set, "%llu\n"); -#endif - -#endif /* CONFIG_DEBUG_FS */ - -int kgsl_debug_init(void) -{ -#ifdef CONFIG_DEBUG_FS - struct dentry *dent; - dent = debugfs_create_dir("kgsl", 0); - if (IS_ERR(dent)) - return 0; - - debugfs_create_file("log_level_cmd", 0644, dent, 0, - &kgsl_cmd_log_fops); - debugfs_create_file("log_level_ctxt", 0644, dent, 0, - &kgsl_ctxt_log_fops); - debugfs_create_file("log_level_drv", 0644, dent, 0, - &kgsl_drv_log_fops); - debugfs_create_file("log_level_mem", 0644, dent, 0, - &kgsl_mem_log_fops); -#ifdef DEBUG - debugfs_create_file("rb_regs", 0444, dent, 0, - &kgsl_rb_regs_fops); -#endif - -#ifdef DEBUG - debugfs_create_file("mmu_regs", 0444, dent, 0, - &kgsl_mmu_regs_fops); -#endif - -#ifdef CONFIG_GPU_MSM_KGSL_MMU - debugfs_create_file("cache_enable", 0644, dent, 0, - &kgsl_cache_enable_fops); -#endif - -#endif /* CONFIG_DEBUG_FS */ - return 0; -} diff --git a/drivers/video/msm/gpu/kgsl/kgsl_log.h b/drivers/video/msm/gpu/kgsl/kgsl_log.h deleted file mode 100644 index 3869ff74..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_log.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2008 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#ifndef _GSL_LOG_H -#define _GSL_LOG_H - -#include -#include -#include -#include - -extern unsigned int kgsl_drv_log; -extern unsigned int kgsl_cmd_log; -extern unsigned int kgsl_ctxt_log; -extern unsigned int kgsl_mem_log; - -struct device *kgsl_driver_getdevnode(void); -int kgsl_debug_init(void); - -#define KGSL_LOG_VDBG(lvl, fmt, args...) \ - do { \ - if ((lvl) >= 7) \ - dev_vdbg(kgsl_driver_getdevnode(), "|%s| " fmt, \ - __func__, ##args);\ - } while (0) - -#define KGSL_LOG_DBG(lvl, fmt, args...) \ - do { \ - if ((lvl) >= 7) \ - dev_dbg(kgsl_driver_getdevnode(), "|%s| " fmt, \ - __func__, ##args);\ - } while (0) - -#define KGSL_LOG_INFO(lvl, fmt, args...) \ - do { \ - if ((lvl) >= 6) \ - dev_info(kgsl_driver_getdevnode(), "|%s| " fmt, \ - __func__, ##args);\ - } while (0) - -#define KGSL_LOG_WARN(lvl, fmt, args...) \ - do { \ - if ((lvl) >= 4) \ - dev_warn(kgsl_driver_getdevnode(), "|%s| " fmt, \ - __func__, ##args);\ - } while (0) - -#define KGSL_LOG_ERR(lvl, fmt, args...) \ - do { \ - if ((lvl) >= 3) \ - dev_err(kgsl_driver_getdevnode(), "|%s| " fmt, \ - __func__, ##args);\ - } while (0) - -#define KGSL_LOG_FATAL(lvl, fmt, args...) \ - do { \ - if ((lvl) >= 2) \ - dev_crit(kgsl_driver_getdevnode(), "|%s| " fmt, \ - __func__, ##args);\ - } while (0) - -#define KGSL_DRV_VDBG(fmt, args...) KGSL_LOG_VDBG(kgsl_drv_log, fmt, ##args) -#define KGSL_DRV_DBG(fmt, args...) KGSL_LOG_DBG(kgsl_drv_log, fmt, ##args) -#define KGSL_DRV_INFO(fmt, args...) KGSL_LOG_INFO(kgsl_drv_log, fmt, ##args) -#define KGSL_DRV_WARN(fmt, args...) KGSL_LOG_WARN(kgsl_drv_log, fmt, ##args) -#define KGSL_DRV_ERR(fmt, args...) KGSL_LOG_ERR(kgsl_drv_log, fmt, ##args) -#define KGSL_DRV_FATAL(fmt, args...) KGSL_LOG_FATAL(kgsl_drv_log, fmt, ##args) - -#define KGSL_CMD_VDBG(fmt, args...) KGSL_LOG_VDBG(kgsl_cmd_log, fmt, ##args) -#define KGSL_CMD_DBG(fmt, args...) KGSL_LOG_DBG(kgsl_cmd_log, fmt, ##args) -#define KGSL_CMD_INFO(fmt, args...) KGSL_LOG_INFO(kgsl_cmd_log, fmt, ##args) -#define KGSL_CMD_WARN(fmt, args...) KGSL_LOG_WARN(kgsl_cmd_log, fmt, ##args) -#define KGSL_CMD_ERR(fmt, args...) KGSL_LOG_ERR(kgsl_cmd_log, fmt, ##args) -#define KGSL_CMD_FATAL(fmt, args...) KGSL_LOG_FATAL(kgsl_cmd_log, fmt, ##args) - -#define KGSL_CTXT_VDBG(fmt, args...) KGSL_LOG_VDBG(kgsl_ctxt_log, fmt, ##args) -#define KGSL_CTXT_DBG(fmt, args...) KGSL_LOG_DBG(kgsl_ctxt_log, fmt, ##args) -#define KGSL_CTXT_INFO(fmt, args...) KGSL_LOG_INFO(kgsl_ctxt_log, fmt, ##args) -#define KGSL_CTXT_WARN(fmt, args...) KGSL_LOG_WARN(kgsl_ctxt_log, fmt, ##args) -#define KGSL_CTXT_ERR(fmt, args...) KGSL_LOG_ERR(kgsl_ctxt_log, fmt, ##args) -#define KGSL_CTXT_FATAL(fmt, args...) KGSL_LOG_FATAL(kgsl_ctxt_log, fmt, ##args) - -#define KGSL_MEM_VDBG(fmt, args...) KGSL_LOG_VDBG(kgsl_mem_log, fmt, ##args) -#define KGSL_MEM_DBG(fmt, args...) KGSL_LOG_DBG(kgsl_mem_log, fmt, ##args) -#define KGSL_MEM_INFO(fmt, args...) KGSL_LOG_INFO(kgsl_mem_log, fmt, ##args) -#define KGSL_MEM_WARN(fmt, args...) KGSL_LOG_WARN(kgsl_mem_log, fmt, ##args) -#define KGSL_MEM_ERR(fmt, args...) KGSL_LOG_ERR(kgsl_mem_log, fmt, ##args) -#define KGSL_MEM_FATAL(fmt, args...) KGSL_LOG_FATAL(kgsl_mem_log, fmt, ##args) - -#endif /* _GSL_LOG_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_mmu.c b/drivers/video/msm/gpu/kgsl/kgsl_mmu.c deleted file mode 100644 index eb7794ba..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_mmu.c +++ /dev/null @@ -1,672 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#include -#include -#include -#include - -#include -#include - -#include "kgsl_mmu.h" -#include "kgsl.h" -#include "kgsl_log.h" -#include "yamato_reg.h" - -struct kgsl_pte_debug { - unsigned int read:1; - unsigned int write:1; - unsigned int dirty:1; - unsigned int reserved:9; - unsigned int phyaddr:20; -}; - -#define GSL_PTE_SIZE 4 -#define GSL_PT_EXTRA_ENTRIES 16 - - -#define GSL_PT_PAGE_BITS_MASK 0x00000007 -#define GSL_PT_PAGE_ADDR_MASK (~(KGSL_PAGESIZE - 1)) - -#define GSL_MMU_INT_MASK \ - (MH_INTERRUPT_MASK__AXI_READ_ERROR | \ - MH_INTERRUPT_MASK__AXI_WRITE_ERROR) - -uint32_t kgsl_pt_entry_get(struct kgsl_pagetable *pt, uint32_t va) -{ - return (va - pt->va_base) >> KGSL_PAGESIZE_SHIFT; -} - -uint32_t kgsl_pt_map_get(struct kgsl_pagetable *pt, uint32_t pte) -{ - uint32_t *baseptr = (uint32_t *)pt->base.hostptr; - return baseptr[pte]; -} - -void kgsl_pt_map_set(struct kgsl_pagetable *pt, uint32_t pte, uint32_t val) -{ - uint32_t *baseptr = (uint32_t *)pt->base.hostptr; - baseptr[pte] = val; -} -#define GSL_PT_MAP_DEBUG(pte) ((struct kgsl_pte_debug *) \ - &gsl_pt_map_get(pagetable, pte)) - -void kgsl_pt_map_setbits(struct kgsl_pagetable *pt, uint32_t pte, uint32_t bits) -{ - uint32_t *baseptr = (uint32_t *)pt->base.hostptr; - baseptr[pte] |= bits; -} - -void kgsl_pt_map_setaddr(struct kgsl_pagetable *pt, uint32_t pte, - uint32_t pageaddr) -{ - uint32_t *baseptr = (uint32_t *)pt->base.hostptr; - uint32_t val = baseptr[pte]; - val &= ~GSL_PT_PAGE_ADDR_MASK; - val |= (pageaddr & GSL_PT_PAGE_ADDR_MASK); - baseptr[pte] = val; -} - -void kgsl_pt_map_resetall(struct kgsl_pagetable *pt, uint32_t pte) -{ - uint32_t *baseptr = (uint32_t *)pt->base.hostptr; - baseptr[pte] &= GSL_PT_PAGE_DIRTY; -} - -void kgsl_pt_map_resetbits(struct kgsl_pagetable *pt, uint32_t pte, - uint32_t bits) -{ - uint32_t *baseptr = (uint32_t *)pt->base.hostptr; - baseptr[pte] &= ~(bits & GSL_PT_PAGE_BITS_MASK); -} - -int kgsl_pt_map_isdirty(struct kgsl_pagetable *pt, uint32_t pte) -{ - uint32_t *baseptr = (uint32_t *)pt->base.hostptr; - return baseptr[pte] & GSL_PT_PAGE_DIRTY; -} - -uint32_t kgsl_pt_map_getaddr(struct kgsl_pagetable *pt, uint32_t pte) -{ - uint32_t *baseptr = (uint32_t *)pt->base.hostptr; - return baseptr[pte] & GSL_PT_PAGE_ADDR_MASK; -} - -void kgsl_mh_intrcallback(struct kgsl_device *device) -{ - unsigned int status = 0; - unsigned int reg; - unsigned int axi_error; - struct kgsl_mmu_debug dbg; - - KGSL_MEM_VDBG("enter (device=%p)\n", device); - - kgsl_yamato_regread(device, REG_MH_INTERRUPT_STATUS, &status); - - if (status & MH_INTERRUPT_MASK__AXI_READ_ERROR) { - kgsl_yamato_regread(device, REG_MH_AXI_ERROR, &axi_error); - KGSL_MEM_FATAL("axi read error interrupt (%08x)\n", axi_error); - kgsl_mmu_debug(&device->mmu, &dbg); - } else if (status & MH_INTERRUPT_MASK__AXI_WRITE_ERROR) { - kgsl_yamato_regread(device, REG_MH_AXI_ERROR, &axi_error); - KGSL_MEM_FATAL("axi write error interrupt (%08x)\n", axi_error); - kgsl_mmu_debug(&device->mmu, &dbg); - } else if (status & MH_INTERRUPT_MASK__MMU_PAGE_FAULT) { - kgsl_yamato_regread(device, REG_MH_MMU_PAGE_FAULT, ®); - KGSL_MEM_FATAL("mmu page fault interrupt: %08x\n", reg); - kgsl_mmu_debug(&device->mmu, &dbg); - } else { - KGSL_MEM_DBG("bad bits in REG_MH_INTERRUPT_STATUS %08x\n", - status); - } - - kgsl_yamato_regwrite(device, REG_MH_INTERRUPT_CLEAR, status); - - /*TODO: figure out how to handle errror interupts. - * specifically, page faults should probably nuke the client that - * caused them, but we don't have enough info to figure that out yet. - */ - - KGSL_MEM_VDBG("return\n"); -} - -#ifdef DEBUG -void kgsl_mmu_debug(struct kgsl_mmu *mmu, struct kgsl_mmu_debug *regs) -{ - memset(regs, 0, sizeof(struct kgsl_mmu_debug)); - - kgsl_yamato_regread(mmu->device, REG_MH_MMU_CONFIG, - ®s->config); - kgsl_yamato_regread(mmu->device, REG_MH_MMU_MPU_BASE, - ®s->mpu_base); - kgsl_yamato_regread(mmu->device, REG_MH_MMU_MPU_END, - ®s->mpu_end); - kgsl_yamato_regread(mmu->device, REG_MH_MMU_VA_RANGE, - ®s->va_range); - kgsl_yamato_regread(mmu->device, REG_MH_MMU_PT_BASE, - ®s->pt_base); - kgsl_yamato_regread(mmu->device, REG_MH_MMU_PAGE_FAULT, - ®s->page_fault); - kgsl_yamato_regread(mmu->device, REG_MH_MMU_TRAN_ERROR, - ®s->trans_error); - kgsl_yamato_regread(mmu->device, REG_MH_AXI_ERROR, - ®s->axi_error); - kgsl_yamato_regread(mmu->device, REG_MH_INTERRUPT_MASK, - ®s->interrupt_mask); - kgsl_yamato_regread(mmu->device, REG_MH_INTERRUPT_STATUS, - ®s->interrupt_status); - - KGSL_MEM_DBG("mmu config %08x mpu_base %08x mpu_end %08x\n", - regs->config, regs->mpu_base, regs->mpu_end); - KGSL_MEM_DBG("mmu va_range %08x pt_base %08x \n", - regs->va_range, regs->pt_base); - KGSL_MEM_DBG("mmu page_fault %08x tran_err %08x\n", - regs->page_fault, regs->trans_error); - KGSL_MEM_DBG("mmu int mask %08x int status %08x\n", - regs->interrupt_mask, regs->interrupt_status); -} -#endif - -struct kgsl_pagetable *kgsl_mmu_createpagetableobject(struct kgsl_mmu *mmu) -{ - int status = 0; - struct kgsl_pagetable *pagetable = NULL; - uint32_t flags; - - KGSL_MEM_VDBG("enter (mmu=%p)\n", mmu); - - pagetable = kzalloc(sizeof(struct kgsl_pagetable), GFP_KERNEL); - if (pagetable == NULL) { - KGSL_MEM_ERR("Unable to allocate pagetable object.\n"); - return NULL; - } - - pagetable->mmu = mmu; - pagetable->va_base = mmu->va_base; - pagetable->va_range = mmu->va_range; - pagetable->last_superpte = 0; - pagetable->max_entries = (mmu->va_range >> KGSL_PAGESIZE_SHIFT) - + GSL_PT_EXTRA_ENTRIES; - - pagetable->pool = gen_pool_create(KGSL_PAGESIZE_SHIFT, -1); - if (pagetable->pool == NULL) { - KGSL_MEM_ERR("Unable to allocate virtualaddr pool.\n"); - goto err_gen_pool_create; - } - - if (gen_pool_add(pagetable->pool, pagetable->va_base, - pagetable->va_range, -1)) { - KGSL_MEM_ERR("gen_pool_create failed for pagetable %p\n", - pagetable); - goto err_gen_pool_add; - } - - /* allocate page table memory */ - flags = (KGSL_MEMFLAGS_ALIGN4K | KGSL_MEMFLAGS_CONPHYS - | KGSL_MEMFLAGS_STRICTREQUEST); - status = kgsl_sharedmem_alloc(flags, - pagetable->max_entries * GSL_PTE_SIZE, - &pagetable->base); - - if (status) { - KGSL_MEM_ERR("cannot alloc page tables\n"); - goto err_kgsl_sharedmem_alloc; - } - - /* reset page table entries - * -- all pte's are marked as not dirty initially - */ - kgsl_sharedmem_set(&pagetable->base, 0, 0, pagetable->base.size); - pagetable->base.gpuaddr = pagetable->base.physaddr; - - KGSL_MEM_VDBG("return %p\n", pagetable); - - return pagetable; - -err_kgsl_sharedmem_alloc: -err_gen_pool_add: - gen_pool_destroy(pagetable->pool); -err_gen_pool_create: - kfree(pagetable); - return NULL; -} - -int kgsl_mmu_destroypagetableobject(struct kgsl_pagetable *pagetable) -{ - KGSL_MEM_VDBG("enter (pagetable=%p)\n", pagetable); - - if (pagetable) { - if (pagetable->base.gpuaddr) - kgsl_sharedmem_free(&pagetable->base); - - if (pagetable->pool) { - gen_pool_destroy(pagetable->pool); - pagetable->pool = NULL; - } - - kfree(pagetable); - - } - KGSL_MEM_VDBG("return 0x%08x\n", 0); - - return 0; -} - -int kgsl_mmu_setstate(struct kgsl_device *device, - struct kgsl_pagetable *pagetable) -{ - int status = 0; - struct kgsl_mmu *mmu = &device->mmu; - - KGSL_MEM_VDBG("enter (device=%p, pagetable=%p)\n", device, pagetable); - - if (mmu->flags & KGSL_FLAGS_STARTED) { - /* page table not current, then setup mmu to use new - * specified page table - */ - KGSL_MEM_INFO("from %p to %p\n", mmu->hwpagetable, pagetable); - if (mmu->hwpagetable != pagetable) { - mmu->hwpagetable = pagetable; - - /* call device specific set page table */ - status = kgsl_yamato_setstate(mmu->device, - KGSL_MMUFLAGS_TLBFLUSH | - KGSL_MMUFLAGS_PTUPDATE); - } - } - - KGSL_MEM_VDBG("return %d\n", status); - - return status; -} - -int kgsl_mmu_init(struct kgsl_device *device) -{ - /* - * intialize device mmu - * - * call this with the global lock held - */ - int status; - uint32_t flags; - struct kgsl_mmu *mmu = &device->mmu; -#ifdef _DEBUG - struct kgsl_mmu_debug regs; -#endif /* _DEBUG */ - - KGSL_MEM_VDBG("enter (device=%p)\n", device); - - if (mmu->flags & KGSL_FLAGS_INITIALIZED0) { - KGSL_MEM_INFO("MMU already initialized.\n"); - return 0; - } - - mmu->device = device; - -#ifndef CONFIG_GPU_MSM_KGSL_MMU - mmu->config = 0x00000000; -#endif - - /* setup MMU and sub-client behavior */ - kgsl_yamato_regwrite(device, REG_MH_MMU_CONFIG, mmu->config); - - /* enable axi interrupts */ - KGSL_MEM_DBG("enabling mmu interrupts mask=0x%08lx\n", - GSL_MMU_INT_MASK); - kgsl_yamato_regwrite(device, REG_MH_INTERRUPT_MASK, GSL_MMU_INT_MASK); - - mmu->flags |= KGSL_FLAGS_INITIALIZED0; - - /* MMU not enabled */ - if ((mmu->config & 0x1) == 0) { - KGSL_MEM_VDBG("return %d\n", 0); - return 0; - } - - /* idle device */ - kgsl_yamato_idle(device, KGSL_TIMEOUT_DEFAULT); - - /* make sure aligned to pagesize */ - BUG_ON(mmu->mpu_base & (KGSL_PAGESIZE - 1)); - BUG_ON((mmu->mpu_base + mmu->mpu_range) & (KGSL_PAGESIZE - 1)); - - /* define physical memory range accessible by the core */ - kgsl_yamato_regwrite(device, REG_MH_MMU_MPU_BASE, - mmu->mpu_base); - kgsl_yamato_regwrite(device, REG_MH_MMU_MPU_END, - mmu->mpu_base + mmu->mpu_range); - - /* enable axi interrupts */ - KGSL_MEM_DBG("enabling mmu interrupts mask=0x%08lx\n", - GSL_MMU_INT_MASK | MH_INTERRUPT_MASK__MMU_PAGE_FAULT); - kgsl_yamato_regwrite(device, REG_MH_INTERRUPT_MASK, - GSL_MMU_INT_MASK | MH_INTERRUPT_MASK__MMU_PAGE_FAULT); - - mmu->flags |= KGSL_FLAGS_INITIALIZED; - - /* sub-client MMU lookups require address translation */ - if ((mmu->config & ~0x1) > 0) { - /*make sure virtual address range is a multiple of 64Kb */ - BUG_ON(mmu->va_range & ((1 << 16) - 1)); - - /* allocate memory used for completing r/w operations that - * cannot be mapped by the MMU - */ - flags = (KGSL_MEMFLAGS_ALIGN4K | KGSL_MEMFLAGS_CONPHYS - | KGSL_MEMFLAGS_STRICTREQUEST); - status = kgsl_sharedmem_alloc(flags, 64, &mmu->dummyspace); - if (status != 0) { - KGSL_MEM_ERR - ("Unable to allocate dummy space memory.\n"); - kgsl_mmu_close(device); - return status; - } - - kgsl_sharedmem_set(&mmu->dummyspace, 0, 0, - mmu->dummyspace.size); - /* TRAN_ERROR needs a 32 byte (32 byte aligned) chunk of memory - * to complete transactions in case of an MMU fault. Note that - * we'll leave the bottom 32 bytes of the dummyspace for other - * purposes (e.g. use it when dummy read cycles are needed - * for other blocks */ - kgsl_yamato_regwrite(device, - REG_MH_MMU_TRAN_ERROR, - mmu->dummyspace.physaddr + 32); - - mmu->defaultpagetable = kgsl_mmu_createpagetableobject(mmu); - if (!mmu->defaultpagetable) { - KGSL_MEM_ERR("Failed to create global page table\n"); - kgsl_mmu_close(device); - return -ENOMEM; - } - mmu->hwpagetable = mmu->defaultpagetable; - mmu->tlbflushfilter.size = (mmu->va_range / - (PAGE_SIZE * GSL_PT_SUPER_PTE * 8)) + 1; - mmu->tlbflushfilter.base = (unsigned int *) - kzalloc(mmu->tlbflushfilter.size, GFP_KERNEL); - if (!mmu->tlbflushfilter.base) { - KGSL_MEM_ERR("Failed to create tlbflushfilter\n"); - kgsl_mmu_close(device); - return -ENOMEM; - } - GSL_TLBFLUSH_FILTER_RESET(); - kgsl_yamato_regwrite(device, REG_MH_MMU_PT_BASE, - mmu->hwpagetable->base.gpuaddr); - kgsl_yamato_regwrite(device, REG_MH_MMU_VA_RANGE, - (mmu->hwpagetable->va_base | - (mmu->hwpagetable->va_range >> 16))); - status = kgsl_yamato_setstate(device, KGSL_MMUFLAGS_TLBFLUSH); - if (status) { - kgsl_mmu_close(device); - return status; - } - - mmu->flags |= KGSL_FLAGS_STARTED; - } - - KGSL_MEM_VDBG("return %d\n", 0); - - return 0; -} - -#ifdef CONFIG_GPU_MSM_KGSL_MMU -pte_t *kgsl_get_pte_from_vaddr(unsigned int vaddr) -{ - pgd_t *pgd_ptr = NULL; - pmd_t *pmd_ptr = NULL; - pte_t *pte_ptr = NULL; - - pgd_ptr = pgd_offset(current->mm, vaddr); - if (pgd_none(*pgd) || pgd_bad(*pgd)) { - KGSL_MEM_ERR - ("Invalid pgd entry found while trying to convert virtual " - "address to physical\n"); - return 0; - } - - pmd_ptr = pmd_offset(pgd_ptr, vaddr); - if (pmd_none(*pmd_ptr) || pmd_bad(*pmd_ptr)) { - KGSL_MEM_ERR - ("Invalid pmd entry found while trying to convert virtual " - "address to physical\n"); - return 0; - } - - pte_ptr = pte_offset_map(pmd_ptr, vaddr); - if (!pte_ptr) { - KGSL_MEM_ERR - ("Unable to map pte entry while trying to convert virtual " - "address to physical\n"); - return 0; - } - return pte_ptr; -} - -int kgsl_mmu_map(struct kgsl_pagetable *pagetable, - unsigned int address, - int range, - unsigned int protflags, - unsigned int *gpuaddr, - unsigned int flags) -{ - int numpages; - unsigned int pte, ptefirst, ptelast, physaddr; - int flushtlb, alloc_size; - struct kgsl_mmu *mmu = NULL; - int phys_contiguous = flags & KGSL_MEMFLAGS_CONPHYS; - unsigned int align = flags & KGSL_MEMFLAGS_ALIGN_MASK; - - KGSL_MEM_VDBG("enter (pt=%p, physaddr=%08x, range=%08d, gpuaddr=%p)\n", - pagetable, address, range, gpuaddr); - - mmu = pagetable->mmu; - - BUG_ON(mmu == NULL); - BUG_ON(protflags & ~(GSL_PT_PAGE_RV | GSL_PT_PAGE_WV)); - BUG_ON(protflags == 0); - BUG_ON(range <= 0); - - /* Only support 4K and 8K alignment for now */ - if (align != KGSL_MEMFLAGS_ALIGN8K && align != KGSL_MEMFLAGS_ALIGN4K) { - KGSL_MEM_ERR("Cannot map memory according to " - "requested flags: %08x\n", flags); - return -EINVAL; - } - - /* Make sure address being mapped is at 4K boundary */ - if (!IS_ALIGNED(address, KGSL_PAGESIZE) || range & ~KGSL_PAGEMASK) { - KGSL_MEM_ERR("Cannot map address not aligned " - "at page boundary: address: %08x, range: %08x\n", - address, range); - return -EINVAL; - } - alloc_size = range; - if (align == KGSL_MEMFLAGS_ALIGN8K) - alloc_size += KGSL_PAGESIZE; - - *gpuaddr = gen_pool_alloc(pagetable->pool, alloc_size); - if (*gpuaddr == 0) { - KGSL_MEM_ERR("gen_pool_alloc failed: %d\n", alloc_size); - return -ENOMEM; - } - - if (align == KGSL_MEMFLAGS_ALIGN8K) { - if (*gpuaddr & ((1 << 13) - 1)) { - /* Not 8k aligned, align it */ - gen_pool_free(pagetable->pool, *gpuaddr, KGSL_PAGESIZE); - *gpuaddr = *gpuaddr + KGSL_PAGESIZE; - } else - gen_pool_free(pagetable->pool, *gpuaddr + range, - KGSL_PAGESIZE); - } - - numpages = (range >> KGSL_PAGESIZE_SHIFT); - - ptefirst = kgsl_pt_entry_get(pagetable, *gpuaddr); - ptelast = ptefirst + numpages; - - pte = ptefirst; - flushtlb = 0; - - /* tlb needs to be flushed when the first and last pte are not at - * superpte boundaries */ - if ((ptefirst & (GSL_PT_SUPER_PTE - 1)) != 0 || - ((ptelast + 1) & (GSL_PT_SUPER_PTE-1)) != 0) - flushtlb = 1; - - for (pte = ptefirst; pte < ptelast; pte++) { -#ifdef VERBOSE_DEBUG - /* check if PTE exists */ - uint32_t val = kgsl_pt_map_getaddr(pagetable, pte); - BUG_ON(val != 0 && val != GSL_PT_PAGE_DIRTY); -#endif - if ((pte & (GSL_PT_SUPER_PTE-1)) == 0) - if (GSL_TLBFLUSH_FILTER_ISDIRTY(pte / GSL_PT_SUPER_PTE)) - flushtlb = 1; - - /* mark pte as in use */ - if (phys_contiguous) - physaddr = address; - else { - physaddr = vmalloc_to_pfn((void *)address); - physaddr <<= PAGE_SHIFT; - } - - if (physaddr) - kgsl_pt_map_set(pagetable, pte, physaddr | protflags); - else { - KGSL_MEM_ERR - ("Unable to find physaddr for vmallloc address: %x\n", - address); - kgsl_mmu_unmap(pagetable, *gpuaddr, range); - return -EFAULT; - } - address += KGSL_PAGESIZE; - } - - KGSL_MEM_INFO("pt %p p %08x g %08x pte f %d l %d n %d f %d\n", - pagetable, address, *gpuaddr, ptefirst, ptelast, - numpages, flushtlb); - - dmb(); - - /* Invalidate tlb only if current page table used by GPU is the - * pagetable that we used to allocate */ - if (flushtlb && (pagetable == mmu->hwpagetable)) { - kgsl_yamato_setstate(mmu->device, KGSL_MMUFLAGS_TLBFLUSH); - GSL_TLBFLUSH_FILTER_RESET(); - } - - - KGSL_MEM_VDBG("return %d\n", 0); - - return 0; -} - -int -kgsl_mmu_unmap(struct kgsl_pagetable *pagetable, unsigned int gpuaddr, - int range) -{ - unsigned int numpages; - unsigned int pte, ptefirst, ptelast, superpte; - struct kgsl_mmu *mmu = NULL; - - KGSL_MEM_VDBG("enter (pt=%p, gpuaddr=0x%08x, range=%d)\n", - pagetable, gpuaddr, range); - - BUG_ON(range <= 0); - - numpages = (range >> KGSL_PAGESIZE_SHIFT); - if (range & (KGSL_PAGESIZE - 1)) - numpages++; - - ptefirst = kgsl_pt_entry_get(pagetable, gpuaddr); - ptelast = ptefirst + numpages; - - KGSL_MEM_INFO("pt %p gpu %08x pte first %d last %d numpages %d\n", - pagetable, gpuaddr, ptefirst, ptelast, numpages); - - mmu = pagetable->mmu; - - superpte = ptefirst - (ptefirst & (GSL_PT_SUPER_PTE-1)); - GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE); - for (pte = ptefirst; pte < ptelast; pte++) { -#ifdef VERBOSE_DEBUG - /* check if PTE exists */ - BUG_ON(!kgsl_pt_map_getaddr(pagetable, pte)); -#endif - kgsl_pt_map_set(pagetable, pte, GSL_PT_PAGE_DIRTY); - superpte = pte - (pte & (GSL_PT_SUPER_PTE - 1)); - if (pte == superpte) - GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / - GSL_PT_SUPER_PTE); - } - - dmb(); - - gen_pool_free(pagetable->pool, gpuaddr, range); - - KGSL_MEM_VDBG("return %d\n", 0); - - return 0; -} -#endif - -int kgsl_mmu_close(struct kgsl_device *device) -{ - /* - * close device mmu - * - * call this with the global lock held - */ - struct kgsl_mmu *mmu = &device->mmu; -#ifdef _DEBUG - int i; -#endif /* _DEBUG */ - - KGSL_MEM_VDBG("enter (device=%p)\n", device); - - if (mmu->flags & KGSL_FLAGS_INITIALIZED0) { - /* disable mh interrupts */ - KGSL_MEM_DBG("disabling mmu interrupts\n"); - kgsl_yamato_regwrite(device, REG_MH_INTERRUPT_MASK, 0); - - /* disable MMU */ - kgsl_yamato_regwrite(device, REG_MH_MMU_CONFIG, 0x00000000); - - if (mmu->dummyspace.gpuaddr) - kgsl_sharedmem_free(&mmu->dummyspace); - - if (mmu->tlbflushfilter.base) { - mmu->tlbflushfilter.size = 0; - kfree(mmu->tlbflushfilter.base); - mmu->tlbflushfilter.base = NULL; - } - - mmu->flags &= ~KGSL_FLAGS_STARTED; - mmu->flags &= ~KGSL_FLAGS_INITIALIZED; - mmu->flags &= ~KGSL_FLAGS_INITIALIZED0; - kgsl_mmu_destroypagetableobject(mmu->defaultpagetable); - mmu->defaultpagetable = NULL; - } - - KGSL_MEM_VDBG("return %d\n", 0); - - return 0; -} diff --git a/drivers/video/msm/gpu/kgsl/kgsl_mmu.h b/drivers/video/msm/gpu/kgsl/kgsl_mmu.h deleted file mode 100644 index 627a6b82..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_mmu.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#ifndef __GSL_MMU_H -#define __GSL_MMU_H -#include -#include -#include "kgsl_log.h" -#include "kgsl_sharedmem.h" - -#define GSL_PT_SUPER_PTE 8 -#define GSL_PT_PAGE_WV 0x00000001 -#define GSL_PT_PAGE_RV 0x00000002 -#define GSL_PT_PAGE_DIRTY 0x00000004 -/* MMU Flags */ -#define KGSL_MMUFLAGS_TLBFLUSH 0x10000000 -#define KGSL_MMUFLAGS_PTUPDATE 0x20000000 - -/* Macros to manage TLB flushing */ -#define GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS (sizeof(unsigned char) * 8) -#define GSL_TLBFLUSH_FILTER_GET(superpte) \ - (*((unsigned char *) \ - (((unsigned int)mmu->tlbflushfilter.base) \ - + (superpte / GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)))) -#define GSL_TLBFLUSH_FILTER_SETDIRTY(superpte) \ - (GSL_TLBFLUSH_FILTER_GET((superpte)) |= 1 << \ - (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)) -#define GSL_TLBFLUSH_FILTER_ISDIRTY(superpte) \ - (GSL_TLBFLUSH_FILTER_GET((superpte)) & \ - (1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS))) -#define GSL_TLBFLUSH_FILTER_RESET() memset(mmu->tlbflushfilter.base,\ - 0, mmu->tlbflushfilter.size) - -extern unsigned int kgsl_cache_enable; - -struct kgsl_device; - -struct kgsl_mmu_debug { - unsigned int config; - unsigned int mpu_base; - unsigned int mpu_end; - unsigned int va_range; - unsigned int pt_base; - unsigned int page_fault; - unsigned int trans_error; - unsigned int axi_error; - unsigned int interrupt_mask; - unsigned int interrupt_status; -}; - -struct kgsl_ptstats { - int64_t maps; - int64_t unmaps; - int64_t superpteallocs; - int64_t superptefrees; - int64_t ptswitches; - int64_t tlbflushes[KGSL_DEVICE_MAX]; -}; - -struct kgsl_pagetable { - unsigned int refcnt; - struct kgsl_mmu *mmu; - struct kgsl_memdesc base; - uint32_t va_base; - unsigned int va_range; - unsigned int last_superpte; - unsigned int max_entries; - struct gen_pool *pool; -}; - -struct kgsl_tlbflushfilter { - unsigned int *base; - unsigned int size; -}; - -struct kgsl_mmu { - unsigned int refcnt; - uint32_t flags; - struct kgsl_device *device; - unsigned int config; - uint32_t mpu_base; - int mpu_range; - uint32_t va_base; - unsigned int va_range; - struct kgsl_memdesc dummyspace; - /* current page table object being used by device mmu */ - struct kgsl_pagetable *defaultpagetable; - struct kgsl_pagetable *hwpagetable; - /* Maintain filter to manage tlb flushing */ - struct kgsl_tlbflushfilter tlbflushfilter; -}; - - -static inline int -kgsl_mmu_isenabled(struct kgsl_mmu *mmu) -{ - return ((mmu)->flags & KGSL_FLAGS_STARTED) ? 1 : 0; -} - - -int kgsl_mmu_init(struct kgsl_device *device); - -int kgsl_mmu_close(struct kgsl_device *device); - -struct kgsl_pagetable *kgsl_mmu_createpagetableobject(struct kgsl_mmu *mmu); - -int kgsl_mmu_destroypagetableobject(struct kgsl_pagetable *pagetable); - -int kgsl_mmu_setstate(struct kgsl_device *device, - struct kgsl_pagetable *pagetable); - -#ifdef CONFIG_GPU_MSM_KGSL_MMU -int kgsl_mmu_map(struct kgsl_pagetable *pagetable, - unsigned int address, - int range, - unsigned int protflags, - unsigned int *gpuaddr, - unsigned int flags); - -int kgsl_mmu_unmap(struct kgsl_pagetable *pagetable, - unsigned int gpuaddr, int range); - -pte_t *kgsl_get_pte_from_vaddr(unsigned int vaddr); -#else -static inline int kgsl_mmu_map(struct kgsl_pagetable *pagetable, - unsigned int address, - int range, - unsigned int protflags, - unsigned int *gpuaddr, - unsigned int flags) -{ - *gpuaddr = address; - return 0; -} - -static inline int kgsl_mmu_unmap(struct kgsl_pagetable *pagetable, - unsigned int gpuaddr, int range) { return 0; } - -static inline pte_t *kgsl_get_pte_from_vaddr(unsigned int vaddr) {return NULL;} -#endif - -int kgsl_mmu_querystats(struct kgsl_pagetable *pagetable, - struct kgsl_ptstats *stats); - -void kgsl_mh_intrcallback(struct kgsl_device *device); - -#ifdef DEBUG -void kgsl_mmu_debug(struct kgsl_mmu *, struct kgsl_mmu_debug*); -#else -static inline void kgsl_mmu_debug(struct kgsl_mmu *mmu, - struct kgsl_mmu_debug *mmu_debug) { } -#endif /* DEBUG */ - -#endif /* __GSL_MMU_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_pm4types.h b/drivers/video/msm/gpu/kgsl/kgsl_pm4types.h deleted file mode 100644 index bc224b41..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_pm4types.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#ifndef __GSL_PM4TYPES_H -#define __GSL_PM4TYPES_H - - -#define PM4_PKT_MASK 0xc0000000 - -#define PM4_TYPE0_PKT ((unsigned int)0 << 30) -#define PM4_TYPE1_PKT ((unsigned int)1 << 30) -#define PM4_TYPE2_PKT ((unsigned int)2 << 30) -#define PM4_TYPE3_PKT ((unsigned int)3 << 30) - - -/* type3 packets */ -/* initialize CP's micro-engine */ -#define PM4_ME_INIT 0x48 - -/* skip N 32-bit words to get to the next packet */ -#define PM4_NOP 0x10 - -/* indirect buffer dispatch. prefetch parser uses this packet type to determine -* whether to pre-fetch the IB -*/ -#define PM4_INDIRECT_BUFFER 0x3f - -/* indirect buffer dispatch. same as IB, but init is pipelined */ -#define PM4_INDIRECT_BUFFER_PFD 0x37 - -/* wait for the IDLE state of the engine */ -#define PM4_WAIT_FOR_IDLE 0x26 - -/* wait until a register or memory location is a specific value */ -#define PM4_WAIT_REG_MEM 0x3c - -/* wait until a register location is equal to a specific value */ -#define PM4_WAIT_REG_EQ 0x52 - -/* wait until a register location is >= a specific value */ -#define PM4_WAT_REG_GTE 0x53 - -/* wait until a read completes */ -#define PM4_WAIT_UNTIL_READ 0x5c - -/* wait until all base/size writes from an IB_PFD packet have completed */ -#define PM4_WAIT_IB_PFD_COMPLETE 0x5d - -/* register read/modify/write */ -#define PM4_REG_RMW 0x21 - -/* reads register in chip and writes to memory */ -#define PM4_REG_TO_MEM 0x3e - -/* write N 32-bit words to memory */ -#define PM4_MEM_WRITE 0x3d - -/* write CP_PROG_COUNTER value to memory */ -#define PM4_MEM_WRITE_CNTR 0x4f - -/* conditional execution of a sequence of packets */ -#define PM4_COND_EXEC 0x44 - -/* conditional write to memory or register */ -#define PM4_COND_WRITE 0x45 - -/* generate an event that creates a write to memory when completed */ -#define PM4_EVENT_WRITE 0x46 - -/* generate a VS|PS_done event */ -#define PM4_EVENT_WRITE_SHD 0x58 - -/* generate a cache flush done event */ -#define PM4_EVENT_WRITE_CFL 0x59 - -/* generate a z_pass done event */ -#define PM4_EVENT_WRITE_ZPD 0x5b - - -/* initiate fetch of index buffer and draw */ -#define PM4_DRAW_INDX 0x22 - -/* draw using supplied indices in packet */ -#define PM4_DRAW_INDX_2 0x36 - -/* initiate fetch of index buffer and binIDs and draw */ -#define PM4_DRAW_INDX_BIN 0x34 - -/* initiate fetch of bin IDs and draw using supplied indices */ -#define PM4_DRAW_INDX_2_BIN 0x35 - - -/* begin/end initiator for viz query extent processing */ -#define PM4_VIZ_QUERY 0x23 - -/* fetch state sub-blocks and initiate shader code DMAs */ -#define PM4_SET_STATE 0x25 - -/* load constant into chip and to memory */ -#define PM4_SET_CONSTANT 0x2d - -/* load sequencer instruction memory (pointer-based) */ -#define PM4_IM_LOAD 0x27 - -/* load sequencer instruction memory (code embedded in packet) */ -#define PM4_IM_LOAD_IMMEDIATE 0x2b - -/* load constants from a location in memory */ -#define PM4_LOAD_CONSTANT_CONTEXT 0x2e - -/* selective invalidation of state pointers */ -#define PM4_INVALIDATE_STATE 0x3b - - -/* dynamically changes shader instruction memory partition */ -#define PM4_SET_SHADER_BASES 0x4A - -/* sets the 64-bit BIN_MASK register in the PFP */ -#define PM4_SET_BIN_MASK 0x50 - -/* sets the 64-bit BIN_SELECT register in the PFP */ -#define PM4_SET_BIN_SELECT 0x51 - - -/* updates the current context, if needed */ -#define PM4_CONTEXT_UPDATE 0x5e - -/* generate interrupt from the command stream */ -#define PM4_INTERRUPT 0x40 - - -/* copy sequencer instruction memory to system memory */ -#define PM4_IM_STORE 0x2c - -/* program an offset that will added to the BIN_BASE value of - * the 3D_DRAW_INDX_BIN packet */ -#define PM4_SET_BIN_BASE_OFFSET 0x4B - -#define PM4_SET_PROTECTED_MODE 0x5f /* sets the register protection mode */ - -/* packet header building macros */ -#define pm4_type0_packet(regindx, cnt) \ - (PM4_TYPE0_PKT | (((cnt)-1) << 16) | ((regindx) & 0x7FFF)) - -#define pm4_type0_packet_for_sameregister(regindx, cnt) \ - ((PM4_TYPE0_PKT | (((cnt)-1) << 16) | ((1 << 15) | \ - ((regindx) & 0x7FFF))) - -#define pm4_type1_packet(reg0, reg1) \ - (PM4_TYPE1_PKT | ((reg1) << 12) | (reg0)) - -#define pm4_type3_packet(opcode, cnt) \ - (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (((opcode) & 0xFF) << 8)) - -#define pm4_predicated_type3_packet(opcode, cnt) \ - (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (((opcode) & 0xFF) << 8) | 0x1) - -#define pm4_nop_packet(cnt) \ - (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (PM4_NOP << 8)) - - -/* packet headers */ -#define PM4_HDR_ME_INIT pm4_type3_packet(PM4_ME_INIT, 18) -#define PM4_HDR_INDIRECT_BUFFER_PFD pm4_type3_packet(PM4_INDIRECT_BUFFER_PFD, 2) -#define PM4_HDR_INDIRECT_BUFFER pm4_type3_packet(PM4_INDIRECT_BUFFER, 2) - -#endif /* __GSL_PM4TYPES_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_ringbuffer.c b/drivers/video/msm/gpu/kgsl/kgsl_ringbuffer.c deleted file mode 100644 index 472d10c1..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_ringbuffer.c +++ /dev/null @@ -1,837 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#include -#include -#include -#include - -#include "kgsl.h" -#include "kgsl_device.h" -#include "kgsl_log.h" -#include "kgsl_pm4types.h" -#include "kgsl_ringbuffer.h" -#include "kgsl_cmdstream.h" - -#include "yamato_reg.h" - -#define GSL_RB_NOP_SIZEDWORDS 2 -/* protected mode error checking below register address 0x800 -* note: if CP_INTERRUPT packet is used then checking needs -* to change to below register address 0x7C8 -*/ -#define GSL_RB_PROTECTED_MODE_CONTROL 0x200001F2 - -#define GSL_CP_INT_MASK \ - (CP_INT_CNTL__SW_INT_MASK | \ - CP_INT_CNTL__T0_PACKET_IN_IB_MASK | \ - CP_INT_CNTL__OPCODE_ERROR_MASK | \ - CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK | \ - CP_INT_CNTL__RESERVED_BIT_ERROR_MASK | \ - CP_INT_CNTL__IB_ERROR_MASK | \ - CP_INT_CNTL__IB2_INT_MASK | \ - CP_INT_CNTL__IB1_INT_MASK | \ - CP_INT_CNTL__RB_INT_MASK) - -#define YAMATO_PFP_FW "yamato_pfp.fw" -#define YAMATO_PM4_FW "yamato_pm4.fw" - -/* ringbuffer size log2 quadwords equivalent */ -inline unsigned int kgsl_ringbuffer_sizelog2quadwords(unsigned int sizedwords) -{ - unsigned int sizelog2quadwords = 0; - int i = sizedwords >> 1; - - while (i >>= 1) - sizelog2quadwords++; - - return sizelog2quadwords; -} - - -/* functions */ -void kgsl_cp_intrcallback(struct kgsl_device *device) -{ - unsigned int status = 0; - struct kgsl_ringbuffer *rb = &device->ringbuffer; - - KGSL_CMD_VDBG("enter (device=%p)\n", device); - - kgsl_yamato_regread(device, REG_CP_INT_STATUS, &status); - - if (status & CP_INT_CNTL__RB_INT_MASK) { - /* signal intr completion event */ - int init_reftimestamp = 0x7fffffff; - int enableflag = 0; - kgsl_sharedmem_write(&rb->device->memstore, - KGSL_DEVICE_MEMSTORE_OFFSET(ts_cmp_enable), - &enableflag, 4); - kgsl_sharedmem_write(&rb->device->memstore, - KGSL_DEVICE_MEMSTORE_OFFSET(ref_wait_ts), - &init_reftimestamp, 4); - KGSL_CMD_WARN("ringbuffer rb interrupt\n"); - } - - if (status & (CP_INT_CNTL__IB1_INT_MASK | CP_INT_CNTL__RB_INT_MASK)) { - KGSL_CMD_WARN("ringbuffer ib1/rb interrupt\n"); - wake_up_interruptible_all(&device->ib1_wq); - } - if (status & CP_INT_CNTL__T0_PACKET_IN_IB_MASK) { - KGSL_CMD_FATAL("ringbuffer TO packet in IB interrupt\n"); - kgsl_yamato_regwrite(rb->device, REG_CP_INT_CNTL, 0); - kgsl_ringbuffer_dump(rb); - } - if (status & CP_INT_CNTL__OPCODE_ERROR_MASK) { - KGSL_CMD_FATAL("ringbuffer opcode error interrupt\n"); - kgsl_yamato_regwrite(rb->device, REG_CP_INT_CNTL, 0); - kgsl_ringbuffer_dump(rb); - } - if (status & CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK) { - KGSL_CMD_FATAL("ringbuffer protected mode error interrupt\n"); - kgsl_yamato_regwrite(rb->device, REG_CP_INT_CNTL, 0); - kgsl_ringbuffer_dump(rb); - } - if (status & CP_INT_CNTL__RESERVED_BIT_ERROR_MASK) { - KGSL_CMD_FATAL("ringbuffer reserved bit error interrupt\n"); - kgsl_yamato_regwrite(rb->device, REG_CP_INT_CNTL, 0); - kgsl_ringbuffer_dump(rb); - } - if (status & CP_INT_CNTL__IB_ERROR_MASK) { - KGSL_CMD_FATAL("ringbuffer IB error interrupt\n"); - kgsl_yamato_regwrite(rb->device, REG_CP_INT_CNTL, 0); - kgsl_ringbuffer_dump(rb); - } - if (status & CP_INT_CNTL__SW_INT_MASK) - KGSL_CMD_DBG("ringbuffer software interrupt\n"); - - if (status & CP_INT_CNTL__IB2_INT_MASK) - KGSL_CMD_DBG("ringbuffer ib2 interrupt\n"); - - if (status & (~GSL_CP_INT_MASK)) - KGSL_CMD_DBG("bad bits in REG_CP_INT_STATUS %08x\n", status); - - /* only ack bits we understand */ - status &= GSL_CP_INT_MASK; - kgsl_yamato_regwrite(device, REG_CP_INT_ACK, status); - - KGSL_CMD_VDBG("return\n"); -} - - -void kgsl_ringbuffer_watchdog() -{ - struct kgsl_device *device = NULL; - struct kgsl_ringbuffer *rb = NULL; - - device = &kgsl_driver.yamato_device; - - BUG_ON(device == NULL); - - rb = &device->ringbuffer; - - KGSL_CMD_VDBG("enter\n"); - - if ((rb->flags & KGSL_FLAGS_STARTED) == 0) { - KGSL_CMD_VDBG("not started\n"); - return; - } - - GSL_RB_GET_READPTR(rb, &rb->rptr); - - if (rb->rptr == rb->wptr) { - /* clear rptr sample for interval n */ - rb->watchdog.flags &= ~KGSL_FLAGS_ACTIVE; - goto done; - } - /* ringbuffer is currently not empty */ - /* and a rptr sample was taken during interval n-1 */ - if (rb->watchdog.flags & KGSL_FLAGS_ACTIVE) { - /* and the rptr did not advance between - * interval n-1 and n */ - if (rb->rptr == rb->watchdog.rptr_sample) { - /* then the core has hung */ - KGSL_CMD_FATAL("Watchdog detected core hung.\n"); - goto done; - } - /* save rptr sample for interval n */ - rb->watchdog.flags |= KGSL_FLAGS_ACTIVE; - rb->watchdog.rptr_sample = rb->rptr; - } -done: - KGSL_CMD_VDBG("return\n"); -} - -static void kgsl_ringbuffer_submit(struct kgsl_ringbuffer *rb) -{ - BUG_ON(rb->wptr == 0); - - GSL_RB_UPDATE_WPTR_POLLING(rb); - /* Drain write buffer and data memory barrier */ - dsb(); - dmb(); - - /* Memory fence to ensure all data has posted. On some systems, - * like 7x27, the register block is not allocated as strongly ordered - * memory. Adding a memory fence ensures ordering during ringbuffer - * submits.*/ - mb(); - - kgsl_yamato_regwrite(rb->device, REG_CP_RB_WPTR, rb->wptr); - - rb->flags |= KGSL_FLAGS_ACTIVE; -} - -static int -kgsl_ringbuffer_waitspace(struct kgsl_ringbuffer *rb, unsigned int numcmds, - int wptr_ahead) -{ - int nopcount; - unsigned int freecmds; - unsigned int *cmds; - - KGSL_CMD_VDBG("enter (rb=%p, numcmds=%d, wptr_ahead=%d)\n", - rb, numcmds, wptr_ahead); - - /* if wptr ahead, fill the remaining with NOPs */ - if (wptr_ahead) { - /* -1 for header */ - nopcount = rb->sizedwords - rb->wptr - 1; - - cmds = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr; - GSL_RB_WRITE(cmds, pm4_nop_packet(nopcount)); - rb->wptr++; - - kgsl_ringbuffer_submit(rb); - - rb->wptr = 0; - } - - /* wait for space in ringbuffer */ - do { - GSL_RB_GET_READPTR(rb, &rb->rptr); - - freecmds = rb->rptr - rb->wptr; - - } while ((freecmds != 0) && (freecmds < numcmds)); - - KGSL_CMD_VDBG("return %d\n", 0); - - return 0; -} - - -static unsigned int *kgsl_ringbuffer_allocspace(struct kgsl_ringbuffer *rb, - unsigned int numcmds) -{ - unsigned int *ptr = NULL; - int status = 0; - - BUG_ON(numcmds >= rb->sizedwords); - - /* check for available space */ - if (rb->wptr >= rb->rptr) { - /* wptr ahead or equal to rptr */ - /* reserve dwords for nop packet */ - if ((rb->wptr + numcmds) > (rb->sizedwords - - GSL_RB_NOP_SIZEDWORDS)) - status = kgsl_ringbuffer_waitspace(rb, numcmds, 1); - } else { - /* wptr behind rptr */ - if ((rb->wptr + numcmds) >= rb->rptr) - status = kgsl_ringbuffer_waitspace(rb, numcmds, 0); - /* check for remaining space */ - /* reserve dwords for nop packet */ - if ((rb->wptr + numcmds) > (rb->sizedwords - - GSL_RB_NOP_SIZEDWORDS)) - status = kgsl_ringbuffer_waitspace(rb, numcmds, 1); - } - - if (status == 0) { - ptr = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr; - rb->wptr += numcmds; - } - - return ptr; -} - -static int kgsl_ringbuffer_load_pm4_ucode(struct kgsl_device *device) -{ - int status = 0; - int i; - const struct firmware *fw = NULL; - unsigned int *fw_ptr = NULL; - size_t fw_word_size = 0; - - status = request_firmware(&fw, YAMATO_PM4_FW, - kgsl_driver.misc.this_device); - if (status != 0) { - KGSL_DRV_ERR("request_firmware failed for %s with error %d\n", - YAMATO_PM4_FW, status); - goto done; - } - /*this firmware must come in 3 word chunks. plus 1 word of version*/ - if ((fw->size % (sizeof(uint32_t)*3)) != 4) { - KGSL_DRV_ERR("bad firmware size %d.\n", fw->size); - status = -EINVAL; - goto done; - } - fw_ptr = (unsigned int *)fw->data; - fw_word_size = fw->size/sizeof(uint32_t); - KGSL_DRV_INFO("loading pm4 ucode version: %d\n", fw_ptr[0]); - - kgsl_yamato_regwrite(device, REG_CP_DEBUG, 0x02000000); - kgsl_yamato_regwrite(device, REG_CP_ME_RAM_WADDR, 0); - for (i = 1; i < fw_word_size; i++) - kgsl_yamato_regwrite(device, REG_CP_ME_RAM_DATA, fw_ptr[i]); - -done: - release_firmware(fw); - return status; -} - -static int kgsl_ringbuffer_load_pfp_ucode(struct kgsl_device *device) -{ - int status = 0; - int i; - const struct firmware *fw = NULL; - unsigned int *fw_ptr = NULL; - size_t fw_word_size = 0; - - status = request_firmware(&fw, YAMATO_PFP_FW, - kgsl_driver.misc.this_device); - if (status != 0) { - KGSL_DRV_ERR("request_firmware for %s failed with error %d\n", - YAMATO_PFP_FW, status); - return status; - } - /*this firmware must come in 1 word chunks. */ - if ((fw->size % sizeof(uint32_t)) != 0) { - KGSL_DRV_ERR("bad firmware size %d.\n", fw->size); - release_firmware(fw); - return -EINVAL; - } - fw_ptr = (unsigned int *)fw->data; - fw_word_size = fw->size/sizeof(uint32_t); - - KGSL_DRV_INFO("loading pfp ucode version: %d\n", fw_ptr[0]); - - kgsl_yamato_regwrite(device, REG_CP_PFP_UCODE_ADDR, 0); - for (i = 1; i < fw_word_size; i++) - kgsl_yamato_regwrite(device, REG_CP_PFP_UCODE_DATA, fw_ptr[i]); - - release_firmware(fw); - return status; -} - -static int kgsl_ringbuffer_start(struct kgsl_ringbuffer *rb) -{ - int status; - /*cp_rb_cntl_u cp_rb_cntl; */ - union reg_cp_rb_cntl cp_rb_cntl; - unsigned int *cmds, rb_cntl; - struct kgsl_device *device = rb->device; - - KGSL_CMD_VDBG("enter (rb=%p)\n", rb); - - if (rb->flags & KGSL_FLAGS_STARTED) { - KGSL_CMD_VDBG("return %d\n", 0); - return 0; - } - kgsl_sharedmem_set(&rb->memptrs_desc, 0, 0, - sizeof(struct kgsl_rbmemptrs)); - - kgsl_sharedmem_set(&rb->buffer_desc, 0, 0xAA, - (rb->sizedwords << 2)); - - kgsl_yamato_regwrite(device, REG_CP_RB_WPTR_BASE, - (rb->memptrs_desc.gpuaddr - + GSL_RB_MEMPTRS_WPTRPOLL_OFFSET)); - - /* setup WPTR delay */ - kgsl_yamato_regwrite(device, REG_CP_RB_WPTR_DELAY, 0 /*0x70000010 */); - - /*setup REG_CP_RB_CNTL */ - kgsl_yamato_regread(device, REG_CP_RB_CNTL, &rb_cntl); - cp_rb_cntl.val = rb_cntl; - /* size of ringbuffer */ - cp_rb_cntl.f.rb_bufsz = - kgsl_ringbuffer_sizelog2quadwords(rb->sizedwords); - /* quadwords to read before updating mem RPTR */ - cp_rb_cntl.f.rb_blksz = rb->blksizequadwords; - cp_rb_cntl.f.rb_poll_en = GSL_RB_CNTL_POLL_EN; /* WPTR polling */ - /* mem RPTR writebacks */ - cp_rb_cntl.f.rb_no_update = GSL_RB_CNTL_NO_UPDATE; - - kgsl_yamato_regwrite(device, REG_CP_RB_CNTL, cp_rb_cntl.val); - - kgsl_yamato_regwrite(device, REG_CP_RB_BASE, rb->buffer_desc.gpuaddr); - - kgsl_yamato_regwrite(device, REG_CP_RB_RPTR_ADDR, - rb->memptrs_desc.gpuaddr + - GSL_RB_MEMPTRS_RPTR_OFFSET); - - /* explicitly clear all cp interrupts */ - kgsl_yamato_regwrite(device, REG_CP_INT_ACK, 0xFFFFFFFF); - - /* setup scratch/timestamp */ - kgsl_yamato_regwrite(device, REG_SCRATCH_ADDR, - device->memstore.gpuaddr + - KGSL_DEVICE_MEMSTORE_OFFSET(soptimestamp)); - - kgsl_yamato_regwrite(device, REG_SCRATCH_UMSK, - GSL_RB_MEMPTRS_SCRATCH_MASK); - - /* load the CP ucode */ - - status = kgsl_ringbuffer_load_pm4_ucode(device); - if (status != 0) { - KGSL_DRV_ERR("kgsl_ringbuffer_load_pm4_ucode failed %d\n", - status); - return status; - } - - - /* load the prefetch parser ucode */ - status = kgsl_ringbuffer_load_pfp_ucode(device); - if (status != 0) { - KGSL_DRV_ERR("kgsl_ringbuffer_load_pm4_ucode failed %d\n", - status); - return status; - } - - kgsl_yamato_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000C0804); - - rb->rptr = 0; - rb->wptr = 0; - - rb->timestamp = 0; - GSL_RB_INIT_TIMESTAMP(rb); - - INIT_LIST_HEAD(&rb->memqueue); - - /* clear ME_HALT to start micro engine */ - kgsl_yamato_regwrite(device, REG_CP_ME_CNTL, 0); - - /* ME_INIT */ - cmds = kgsl_ringbuffer_allocspace(rb, 19); - - GSL_RB_WRITE(cmds, PM4_HDR_ME_INIT); - /* All fields present (bits 9:0) */ - GSL_RB_WRITE(cmds, 0x000003ff); - /* Disable/Enable Real-Time Stream processing (present but ignored) */ - GSL_RB_WRITE(cmds, 0x00000000); - /* Enable (2D <-> 3D) implicit synchronization (present but ignored) */ - GSL_RB_WRITE(cmds, 0x00000000); - - GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(REG_RB_SURFACE_INFO)); - GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SC_WINDOW_OFFSET)); - GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(REG_VGT_MAX_VTX_INDX)); - GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(REG_SQ_PROGRAM_CNTL)); - GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(REG_RB_DEPTHCONTROL)); - GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SU_POINT_SIZE)); - GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SC_LINE_CNTL)); - GSL_RB_WRITE(cmds, - GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE)); - - /* Vertex and Pixel Shader Start Addresses in instructions - * (3 DWORDS per instruction) */ - GSL_RB_WRITE(cmds, 0x80000180); - /* Maximum Contexts */ - GSL_RB_WRITE(cmds, 0x00000001); - /* Write Confirm Interval and The CP will wait the - * wait_interval * 16 clocks between polling */ - GSL_RB_WRITE(cmds, 0x00000000); - - /* NQ and External Memory Swap */ - GSL_RB_WRITE(cmds, 0x00000000); - /* Protected mode error checking */ - GSL_RB_WRITE(cmds, GSL_RB_PROTECTED_MODE_CONTROL); - /* Disable header dumping and Header dump address */ - GSL_RB_WRITE(cmds, 0x00000000); - /* Header dump size */ - GSL_RB_WRITE(cmds, 0x00000000); - - kgsl_ringbuffer_submit(rb); - - /* idle device to validate ME INIT */ - status = kgsl_yamato_idle(device, KGSL_TIMEOUT_DEFAULT); - - KGSL_CMD_DBG("enabling CP interrupts: mask %08lx\n", GSL_CP_INT_MASK); - kgsl_yamato_regwrite(rb->device, REG_CP_INT_CNTL, GSL_CP_INT_MASK); - if (status == 0) - rb->flags |= KGSL_FLAGS_STARTED; - - KGSL_CMD_VDBG("return %d\n", status); - - return status; -} - -static int kgsl_ringbuffer_stop(struct kgsl_ringbuffer *rb) -{ - KGSL_CMD_VDBG("enter (rb=%p)\n", rb); - - if (rb->flags & KGSL_FLAGS_STARTED) { - KGSL_CMD_DBG("disabling CP interrupts: mask %08x\n", 0); - kgsl_yamato_regwrite(rb->device, REG_CP_INT_CNTL, 0); - - /* ME_HALT */ - kgsl_yamato_regwrite(rb->device, REG_CP_ME_CNTL, 0x10000000); - - rb->flags &= ~KGSL_FLAGS_STARTED; - kgsl_ringbuffer_dump(rb); - } - - KGSL_CMD_VDBG("return %d\n", 0); - - return 0; -} - -int kgsl_ringbuffer_init(struct kgsl_device *device) -{ - int status; - uint32_t flags; - struct kgsl_ringbuffer *rb = &device->ringbuffer; - - KGSL_CMD_VDBG("enter (device=%p)\n", device); - - rb->device = device; - rb->sizedwords = (2 << kgsl_cfg_rb_sizelog2quadwords); - rb->blksizequadwords = kgsl_cfg_rb_blksizequadwords; - - /* allocate memory for ringbuffer, needs to be double octword aligned - * align on page from contiguous physical memory - */ - flags = - (KGSL_MEMFLAGS_ALIGNPAGE | KGSL_MEMFLAGS_CONPHYS | - KGSL_MEMFLAGS_STRICTREQUEST); - - status = kgsl_sharedmem_alloc(flags, (rb->sizedwords << 2), - &rb->buffer_desc); - - if (status != 0) { - kgsl_ringbuffer_close(rb); - KGSL_CMD_VDBG("return %d\n", status); - return status; - } - - /* allocate memory for polling and timestamps */ - /* This really can be at 4 byte alignment boundry but for using MMU - * we need to make it at page boundary */ - flags = (KGSL_MEMFLAGS_ALIGNPAGE | KGSL_MEMFLAGS_CONPHYS); - - status = kgsl_sharedmem_alloc(flags, sizeof(struct kgsl_rbmemptrs), - &rb->memptrs_desc); - - if (status != 0) { - kgsl_ringbuffer_close(rb); - KGSL_CMD_VDBG("return %d\n", status); - return status; - } - - /* last allocation of init process is made here so map all - * allocations to MMU */ - status = kgsl_yamato_setup_pt(device, device->mmu.defaultpagetable); - if (status != 0) { - kgsl_ringbuffer_close(rb); - KGSL_CMD_VDBG("return %d\n", status); - return status; - } - - /* overlay structure on memptrs memory */ - rb->memptrs = (struct kgsl_rbmemptrs *) rb->memptrs_desc.hostptr; - - rb->flags |= KGSL_FLAGS_INITIALIZED; - - status = kgsl_ringbuffer_start(rb); - if (status != 0) { - kgsl_ringbuffer_close(rb); - KGSL_CMD_VDBG("return %d\n", status); - return status; - } - - KGSL_CMD_VDBG("return %d\n", 0); - return 0; -} - -int kgsl_ringbuffer_close(struct kgsl_ringbuffer *rb) -{ - KGSL_CMD_VDBG("enter (rb=%p)\n", rb); - - kgsl_cmdstream_memqueue_drain(rb->device); - - kgsl_ringbuffer_stop(rb); - - /* this must happen before first sharedmem_free */ - kgsl_yamato_cleanup_pt(rb->device, rb->device->mmu.defaultpagetable); - - if (rb->buffer_desc.hostptr) - kgsl_sharedmem_free(&rb->buffer_desc); - - if (rb->memptrs_desc.hostptr) - kgsl_sharedmem_free(&rb->memptrs_desc); - - rb->flags &= ~KGSL_FLAGS_INITIALIZED; - - memset(rb, 0, sizeof(struct kgsl_ringbuffer)); - - KGSL_CMD_VDBG("return %d\n", 0); - return 0; -} - -static uint32_t -kgsl_ringbuffer_addcmds(struct kgsl_ringbuffer *rb, - int flags, unsigned int *cmds, - int sizedwords) -{ - unsigned int *ringcmds; - unsigned int timestamp; - unsigned int total_sizedwords = sizedwords + 6; - - /* reserve space to temporarily turn off protected mode - * error checking if needed - */ - total_sizedwords += flags & KGSL_CMD_FLAGS_PMODE ? 4 : 0; - total_sizedwords += !(flags & KGSL_CMD_FLAGS_NO_TS_CMP) ? 9 : 0; - - ringcmds = kgsl_ringbuffer_allocspace(rb, total_sizedwords); - - if (flags & KGSL_CMD_FLAGS_PMODE) { - /* disable protected mode error checking */ - *ringcmds++ = pm4_type3_packet(PM4_SET_PROTECTED_MODE, 1); - *ringcmds++ = 0; - } - - memcpy(ringcmds, cmds, (sizedwords << 2)); - - ringcmds += sizedwords; - - if (flags & KGSL_CMD_FLAGS_PMODE) { - /* re-enable protected mode error checking */ - *ringcmds++ = pm4_type3_packet(PM4_SET_PROTECTED_MODE, 1); - *ringcmds++ = 1; - } - - rb->timestamp++; - timestamp = rb->timestamp; - - /* start-of-pipeline and end-of-pipeline timestamps */ - *ringcmds++ = pm4_type0_packet(REG_CP_TIMESTAMP, 1); - *ringcmds++ = rb->timestamp; - *ringcmds++ = pm4_type3_packet(PM4_EVENT_WRITE, 3); - *ringcmds++ = CACHE_FLUSH_TS; - *ringcmds++ = - (rb->device->memstore.gpuaddr + - KGSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp)); - *ringcmds++ = rb->timestamp; - - if (!(flags & KGSL_CMD_FLAGS_NO_TS_CMP)) { - /* Add idle packet so avoid RBBM errors */ - *ringcmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *ringcmds++ = 0x00000000; - /* Conditional execution based on memory values */ - *ringcmds++ = pm4_type3_packet(PM4_COND_EXEC, 4); - *ringcmds++ = (rb->device->memstore.gpuaddr + - KGSL_DEVICE_MEMSTORE_OFFSET(ts_cmp_enable)) >> 2; - *ringcmds++ = (rb->device->memstore.gpuaddr + - KGSL_DEVICE_MEMSTORE_OFFSET(ref_wait_ts)) >> 2; - *ringcmds++ = rb->timestamp; - /* # of conditional command DWORDs */ - *ringcmds++ = 2; - *ringcmds++ = pm4_type3_packet(PM4_INTERRUPT, 1); - *ringcmds++ = CP_INT_CNTL__RB_INT_MASK; - } - - kgsl_ringbuffer_submit(rb); - - GSL_RB_STATS(rb->stats.words_total += sizedwords); - GSL_RB_STATS(rb->stats.issues++); - - KGSL_CMD_VDBG("return %d\n", timestamp); - - /* return timestamp of issued coREG_ands */ - return timestamp; -} - -uint32_t -kgsl_ringbuffer_issuecmds(struct kgsl_device *device, - int flags, - unsigned int *cmds, - int sizedwords) -{ - unsigned int timestamp; - struct kgsl_ringbuffer *rb = &device->ringbuffer; - - KGSL_CMD_VDBG("enter (device->id=%d, flags=%d, cmds=%p, " - "sizedwords=%d)\n", device->id, flags, cmds, sizedwords); - - timestamp = kgsl_ringbuffer_addcmds(rb, flags, cmds, sizedwords); - - KGSL_CMD_VDBG("return %d\n)", timestamp); - return timestamp; -} - -int -kgsl_ringbuffer_issueibcmds(struct kgsl_device *device, - int drawctxt_index, - uint32_t ibaddr, - int sizedwords, - uint32_t *timestamp, - unsigned int flags) -{ - unsigned int link[3]; - - KGSL_CMD_VDBG("enter (device_id=%d, drawctxt_index=%d, ibaddr=0x%08x," - " sizedwords=%d, timestamp=%p)\n", - device->id, drawctxt_index, ibaddr, - sizedwords, timestamp); - - if (!(device->ringbuffer.flags & KGSL_FLAGS_STARTED)) { - KGSL_CMD_VDBG("return %d\n", -EINVAL); - return -EINVAL; - } - - BUG_ON(ibaddr == 0); - BUG_ON(sizedwords == 0); - - link[0] = PM4_HDR_INDIRECT_BUFFER_PFD; - link[1] = ibaddr; - link[2] = sizedwords; - - kgsl_drawctxt_switch(device, &device->drawctxt[drawctxt_index], flags); - - *timestamp = kgsl_ringbuffer_addcmds(&device->ringbuffer, - 0, &link[0], 3); - - - KGSL_CMD_INFO("ctxt %d g %08x sd %d ts %d\n", - drawctxt_index, ibaddr, sizedwords, *timestamp); - - KGSL_CMD_VDBG("return %d\n", 0); - - return 0; -} - - -#ifdef DEBUG -void kgsl_ringbuffer_debug(struct kgsl_ringbuffer *rb, - struct kgsl_rb_debug *rb_debug) -{ - memset(rb_debug, 0, sizeof(struct kgsl_rb_debug)); - - rb_debug->mem_rptr = rb->memptrs->rptr; - rb_debug->mem_wptr_poll = rb->memptrs->wptr_poll; - kgsl_yamato_regread(rb->device, REG_CP_RB_BASE, - (unsigned int *)&rb_debug->cp_rb_base); - kgsl_yamato_regread(rb->device, REG_CP_RB_CNTL, - (unsigned int *)&rb_debug->cp_rb_cntl); - kgsl_yamato_regread(rb->device, REG_CP_RB_RPTR_ADDR, - (unsigned int *)&rb_debug->cp_rb_rptr_addr); - kgsl_yamato_regread(rb->device, REG_CP_RB_RPTR, - (unsigned int *)&rb_debug->cp_rb_rptr); - kgsl_yamato_regread(rb->device, REG_CP_RB_RPTR_WR, - (unsigned int *)&rb_debug->cp_rb_rptr_wr); - kgsl_yamato_regread(rb->device, REG_CP_RB_WPTR, - (unsigned int *)&rb_debug->cp_rb_wptr); - kgsl_yamato_regread(rb->device, REG_CP_RB_WPTR_DELAY, - (unsigned int *)&rb_debug->cp_rb_wptr_delay); - kgsl_yamato_regread(rb->device, REG_CP_RB_WPTR_BASE, - (unsigned int *)&rb_debug->cp_rb_wptr_base); - kgsl_yamato_regread(rb->device, REG_CP_IB1_BASE, - (unsigned int *)&rb_debug->cp_ib1_base); - kgsl_yamato_regread(rb->device, REG_CP_IB1_BUFSZ, - (unsigned int *)&rb_debug->cp_ib1_bufsz); - kgsl_yamato_regread(rb->device, REG_CP_IB2_BASE, - (unsigned int *)&rb_debug->cp_ib2_base); - kgsl_yamato_regread(rb->device, REG_CP_IB2_BUFSZ, - (unsigned int *)&rb_debug->cp_ib2_bufsz); - kgsl_yamato_regread(rb->device, REG_CP_ST_BASE, - (unsigned int *)&rb_debug->cp_st_base); - kgsl_yamato_regread(rb->device, REG_CP_ST_BUFSZ, - (unsigned int *)&rb_debug->cp_st_bufsz); - kgsl_yamato_regread(rb->device, REG_CP_CSQ_RB_STAT, - (unsigned int *)&rb_debug->cp_csq_rb_stat); - kgsl_yamato_regread(rb->device, REG_CP_CSQ_IB1_STAT, - (unsigned int *)&rb_debug->cp_csq_ib1_stat); - kgsl_yamato_regread(rb->device, REG_CP_CSQ_IB2_STAT, - (unsigned int *)&rb_debug->cp_csq_ib2_stat); - kgsl_yamato_regread(rb->device, REG_SCRATCH_UMSK, - (unsigned int *)&rb_debug->scratch_umsk); - kgsl_yamato_regread(rb->device, REG_SCRATCH_ADDR, - (unsigned int *)&rb_debug->scratch_addr); - kgsl_yamato_regread(rb->device, REG_CP_ME_CNTL, - (unsigned int *)&rb_debug->cp_me_cntl); - kgsl_yamato_regread(rb->device, REG_CP_ME_STATUS, - (unsigned int *)&rb_debug->cp_me_status); - kgsl_yamato_regread(rb->device, REG_CP_DEBUG, - (unsigned int *)&rb_debug->cp_debug); - kgsl_yamato_regread(rb->device, REG_CP_STAT, - (unsigned int *)&rb_debug->cp_stat); - kgsl_yamato_regread(rb->device, REG_CP_INT_STATUS, - (unsigned int *)&rb_debug->cp_int_status); - kgsl_yamato_regread(rb->device, REG_CP_INT_CNTL, - (unsigned int *)&rb_debug->cp_int_cntl); - kgsl_yamato_regread(rb->device, REG_RBBM_STATUS, - (unsigned int *)&rb_debug->rbbm_status); - kgsl_yamato_regread(rb->device, REG_RBBM_INT_STATUS, - (unsigned int *)&rb_debug->rbbm_int_status); - GSL_RB_GET_SOP_TIMESTAMP(rb, (unsigned int *)&rb_debug->sop_timestamp); - GSL_RB_GET_EOP_TIMESTAMP(rb, (unsigned int *)&rb_debug->eop_timestamp); - -} -#endif /*DEBUG*/ - -#ifdef DEBUG -void kgsl_ringbuffer_dump(struct kgsl_ringbuffer *rb) -{ - struct kgsl_rb_debug rb_debug; - kgsl_ringbuffer_debug(rb, &rb_debug); - - KGSL_CMD_DBG("rbbm_status %08x rbbm_int_status %08x" - " mem_rptr %08x mem_wptr_poll %08x\n", - rb_debug.rbbm_status, - rb_debug.rbbm_int_status, - rb_debug.mem_rptr, rb_debug.mem_wptr_poll); - - KGSL_CMD_DBG("rb_base %08x rb_cntl %08x rb_rptr_addr %08x rb_rptr %08x" - " rb_rptr_wr %08x\n", - rb_debug.cp_rb_base, rb_debug.cp_rb_cntl, - rb_debug.cp_rb_rptr_addr, rb_debug.cp_rb_rptr, - rb_debug.cp_rb_rptr_wr); - - KGSL_CMD_DBG("rb_wptr %08x rb_wptr_delay %08x rb_wptr_base %08x" - " ib1_base %08x ib1_bufsz %08x\n", - rb_debug.cp_rb_wptr, rb_debug.cp_rb_wptr_delay, - rb_debug.cp_rb_wptr_base, rb_debug.cp_ib1_base, - rb_debug.cp_ib1_bufsz); - - KGSL_CMD_DBG("ib2_base %08x ib2_bufsz %08x st_base %08x st_bufsz %08x" - " cp_me_cntl %08x cp_me_status %08x\n", - rb_debug.cp_ib2_base, rb_debug.cp_ib2_bufsz, - rb_debug.cp_st_base, rb_debug.cp_st_bufsz, - rb_debug.cp_me_cntl, rb_debug.cp_me_status); - - KGSL_CMD_DBG("cp_debug %08x cp_stat %08x cp_int_status %08x" - " cp_int_cntl %08x\n", - rb_debug.cp_debug, rb_debug.cp_stat, - rb_debug.cp_int_status, rb_debug.cp_int_cntl); - - KGSL_CMD_DBG("sop_timestamp: %d eop_timestamp: %d\n", - rb_debug.sop_timestamp, rb_debug.eop_timestamp); - -} -#endif /* DEBUG */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_ringbuffer.h b/drivers/video/msm/gpu/kgsl/kgsl_ringbuffer.h deleted file mode 100644 index 0d060209..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_ringbuffer.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#ifndef __GSL_RINGBUFFER_H -#define __GSL_RINGBUFFER_H - -#include -#include -#include -#include "kgsl_log.h" -#include "kgsl_sharedmem.h" -#include "yamato_reg.h" - -#define GSL_STATS_RINGBUFFER - -#define GSL_RB_USE_MEM_RPTR -#define GSL_RB_USE_MEM_TIMESTAMP -#define GSL_DEVICE_SHADOW_MEMSTORE_TO_USER - -/* ringbuffer sizes log2quadword */ -#define GSL_RB_SIZE_8 0 -#define GSL_RB_SIZE_16 1 -#define GSL_RB_SIZE_32 2 -#define GSL_RB_SIZE_64 3 -#define GSL_RB_SIZE_128 4 -#define GSL_RB_SIZE_256 5 -#define GSL_RB_SIZE_512 6 -#define GSL_RB_SIZE_1K 7 -#define GSL_RB_SIZE_2K 8 -#define GSL_RB_SIZE_4K 9 -#define GSL_RB_SIZE_8K 10 -#define GSL_RB_SIZE_16K 11 -#define GSL_RB_SIZE_32K 12 -#define GSL_RB_SIZE_64K 13 -#define GSL_RB_SIZE_128K 14 -#define GSL_RB_SIZE_256K 15 -#define GSL_RB_SIZE_512K 16 -#define GSL_RB_SIZE_1M 17 -#define GSL_RB_SIZE_2M 18 -#define GSL_RB_SIZE_4M 19 - -/* Yamato ringbuffer config*/ -static const unsigned int kgsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K; -static const unsigned int kgsl_cfg_rb_blksizequadwords = GSL_RB_SIZE_16; - -/* CP timestamp register */ -#define REG_CP_TIMESTAMP REG_SCRATCH_REG0 - - -struct kgsl_device; -struct kgsl_drawctxt; -struct kgsl_ringbuffer; - -struct kgsl_rb_debug { - unsigned int pm4_ucode_rel; - unsigned int pfp_ucode_rel; - unsigned int mem_wptr_poll; - unsigned int mem_rptr; - unsigned int cp_rb_base; - unsigned int cp_rb_cntl; - unsigned int cp_rb_rptr_addr; - unsigned int cp_rb_rptr; - unsigned int cp_rb_rptr_wr; - unsigned int cp_rb_wptr; - unsigned int cp_rb_wptr_delay; - unsigned int cp_rb_wptr_base; - unsigned int cp_ib1_base; - unsigned int cp_ib1_bufsz; - unsigned int cp_ib2_base; - unsigned int cp_ib2_bufsz; - unsigned int cp_st_base; - unsigned int cp_st_bufsz; - unsigned int cp_csq_rb_stat; - unsigned int cp_csq_ib1_stat; - unsigned int cp_csq_ib2_stat; - unsigned int scratch_umsk; - unsigned int scratch_addr; - unsigned int cp_me_cntl; - unsigned int cp_me_status; - unsigned int cp_debug; - unsigned int cp_stat; - unsigned int cp_int_status; - unsigned int cp_int_cntl; - unsigned int rbbm_status; - unsigned int rbbm_int_status; - unsigned int sop_timestamp; - unsigned int eop_timestamp; -}; -#ifdef DEBUG -void kgsl_ringbuffer_debug(struct kgsl_ringbuffer *rb, - struct kgsl_rb_debug *rb_debug); - -void kgsl_ringbuffer_dump(struct kgsl_ringbuffer *rb); -#else -static inline void kgsl_ringbuffer_debug(struct kgsl_ringbuffer *rb, - struct kgsl_rb_debug *rb_debug) -{ -} - -static inline void kgsl_ringbuffer_dump(struct kgsl_ringbuffer *rb) -{ -} -#endif - -struct kgsl_rbwatchdog { - uint32_t flags; - unsigned int rptr_sample; -}; - -#define GSL_RB_MEMPTRS_SCRATCH_COUNT 8 -struct kgsl_rbmemptrs { - volatile int rptr; - volatile int wptr_poll; -} __attribute__ ((packed)); - -#define GSL_RB_MEMPTRS_RPTR_OFFSET \ - (offsetof(struct kgsl_rbmemptrs, rptr)) - -#define GSL_RB_MEMPTRS_WPTRPOLL_OFFSET \ - (offsetof(struct kgsl_rbmemptrs, wptr_poll)) - -struct kgsl_rbstats { - int64_t issues; - int64_t words_total; -}; - - -struct kgsl_ringbuffer { - struct kgsl_device *device; - uint32_t flags; - - struct kgsl_memdesc buffer_desc; - - struct kgsl_memdesc memptrs_desc; - struct kgsl_rbmemptrs *memptrs; - - /*ringbuffer size */ - unsigned int sizedwords; - unsigned int blksizequadwords; - - unsigned int wptr; /* write pointer offset in dwords from baseaddr */ - unsigned int rptr; /* read pointer offset in dwords from baseaddr */ - uint32_t timestamp; - - /* queue of memfrees pending timestamp elapse */ - struct list_head memqueue; - - struct kgsl_rbwatchdog watchdog; - -#ifdef GSL_STATS_RINGBUFFER - struct kgsl_rbstats stats; -#endif /* GSL_STATS_RINGBUFFER */ - -}; - -/* dword base address of the GFX decode space */ -#define GSL_HAL_SUBBLOCK_OFFSET(reg) ((unsigned int)((reg) - (0x2000))) - -#define GSL_RB_WRITE(ring, data) \ - do { \ - mb(); \ - writel(data, ring); \ - ring++; \ - } while (0) - -/* timestamp */ -#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER -#define GSL_RB_USE_MEM_TIMESTAMP -#endif /* GSL_DEVICE_SHADOW_MEMSTORE_TO_USER */ - -#ifdef GSL_RB_USE_MEM_TIMESTAMP -/* enable timestamp (...scratch0) memory shadowing */ -#define GSL_RB_MEMPTRS_SCRATCH_MASK 0x1 -#define GSL_RB_INIT_TIMESTAMP(rb) - -#else -#define GSL_RB_MEMPTRS_SCRATCH_MASK 0x0 -#define GSL_RB_INIT_TIMESTAMP(rb) \ - kgsl_yamato_regwrite((rb)->device->id, REG_CP_TIMESTAMP, 0) - -#endif /* GSL_RB_USE_MEMTIMESTAMP */ - -/* mem rptr */ -#ifdef GSL_RB_USE_MEM_RPTR -#define GSL_RB_CNTL_NO_UPDATE 0x0 /* enable */ -#define GSL_RB_GET_READPTR(rb, data) \ - do { \ - *(data) = (rb)->memptrs->rptr; \ - } while (0) -#else -#define GSL_RB_CNTL_NO_UPDATE 0x1 /* disable */ -#define GSL_RB_GET_READPTR(rb, data) \ - do { \ - kgsl_yamato_regread((rb)->device->id, REG_CP_RB_RPTR, (data)); \ - } while (0) -#endif /* GSL_RB_USE_MEMRPTR */ - -/* wptr polling */ -#ifdef GSL_RB_USE_WPTR_POLLING -#define GSL_RB_CNTL_POLL_EN 0x1 /* enable */ -#define GSL_RB_UPDATE_WPTR_POLLING(rb) \ - do { (rb)->memptrs->wptr_poll = (rb)->wptr; } while (0) -#else -#define GSL_RB_CNTL_POLL_EN 0x0 /* disable */ -#define GSL_RB_UPDATE_WPTR_POLLING(rb) -#endif /* GSL_RB_USE_WPTR_POLLING */ - -/* stats */ -#ifdef GSL_STATS_RINGBUFFER -#define GSL_RB_STATS(x) x -#else -#define GSL_RB_STATS(x) -#endif /* GSL_STATS_RINGBUFFER */ - -struct kgsl_pmem_entry; - -int kgsl_ringbuffer_issueibcmds(struct kgsl_device *, int drawctxt_index, - uint32_t ibaddr, int sizedwords, - uint32_t *timestamp, - unsigned int flags); - -int kgsl_ringbuffer_init(struct kgsl_device *device); - -int kgsl_ringbuffer_close(struct kgsl_ringbuffer *rb); - -uint32_t kgsl_ringbuffer_issuecmds(struct kgsl_device *device, - int pmodeoff, - unsigned int *cmdaddr, - int sizedwords); - -int kgsl_ringbuffer_gettimestampshadow(struct kgsl_device *device, - unsigned int *sopaddr, - unsigned int *eopaddr); - -void kgsl_ringbuffer_watchdog(void); - -void kgsl_cp_intrcallback(struct kgsl_device *device); - -#endif /* __GSL_RINGBUFFER_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_sharedmem.c b/drivers/video/msm/gpu/kgsl/kgsl_sharedmem.c deleted file mode 100644 index 4a1b4212..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_sharedmem.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#include -#include -#include - -#include "kgsl_sharedmem.h" -#include "kgsl_device.h" -#include "kgsl.h" -#include "kgsl_log.h" - -/* block alignment shift count */ -static inline unsigned int -kgsl_memarena_get_order(uint32_t flags) -{ - unsigned int alignshift; - alignshift = ((flags & KGSL_MEMFLAGS_ALIGN_MASK) - >> KGSL_MEMFLAGS_ALIGN_SHIFT); - return alignshift; -} - -/* block alignment shift count */ -static inline unsigned int -kgsl_memarena_align(unsigned int address, unsigned int shift) -{ - unsigned int alignedbaseaddr = ((address) >> shift) << shift; - if (alignedbaseaddr < address) - alignedbaseaddr += (1 << shift); - - return alignedbaseaddr; -} - -int -kgsl_sharedmem_init(struct kgsl_sharedmem *shmem) -{ - int result = -EINVAL; - - if (!request_mem_region(shmem->physbase, shmem->size, DRIVER_NAME)) { - KGSL_MEM_ERR("request_mem_region failed\n"); - goto error; - } - - shmem->baseptr = ioremap(shmem->physbase, shmem->size); - KGSL_MEM_INFO("ioremap(shm) = %p\n", shmem->baseptr); - - if (shmem->baseptr == NULL) { - KGSL_MEM_ERR("ioremap failed for address %08x size %d\n", - shmem->physbase, shmem->size); - result = -ENODEV; - goto error_release_mem; - } - - shmem->pool = gen_pool_create(KGSL_PAGESIZE_SHIFT, -1); - if (shmem->pool == NULL) { - KGSL_MEM_ERR("gen_pool_create failed\n"); - result = -ENOMEM; - goto error_iounmap; - } - - if (gen_pool_add(shmem->pool, shmem->physbase, shmem->size, -1)) { - KGSL_MEM_ERR("gen_pool_create failed\n"); - result = -ENOMEM; - goto error_pool_destroy; - } - result = 0; - KGSL_MEM_INFO("physbase 0x%08x size 0x%08x baseptr 0x%p\n", - shmem->physbase, shmem->size, shmem->baseptr); - return 0; - -error_pool_destroy: - gen_pool_destroy(shmem->pool); -error_iounmap: - iounmap(shmem->baseptr); - shmem->baseptr = NULL; -error_release_mem: - release_mem_region(shmem->physbase, shmem->size); -error: - return result; -} - -int -kgsl_sharedmem_close(struct kgsl_sharedmem *shmem) -{ - if (shmem->pool) { - gen_pool_destroy(shmem->pool); - shmem->pool = NULL; - } - - if (shmem->baseptr != NULL) { - KGSL_MEM_INFO("iounmap(shm) = %p\n", shmem->baseptr); - iounmap(shmem->baseptr); - shmem->baseptr = NULL; - release_mem_region(shmem->physbase, shmem->size); - } - - return 0; -} -/* -* get the host mapped address for a hardware device address -*/ -static void *kgsl_memarena_gethostptr(struct kgsl_sharedmem *shmem, - uint32_t physaddr) -{ - void *result; - - KGSL_MEM_VDBG("enter (memarena=%p, physaddr=0x%08x)\n", - shmem, physaddr); - - BUG_ON(shmem == NULL); - - /* check address range */ - if (physaddr < shmem->physbase) - return NULL; - - if (physaddr >= shmem->physbase + shmem->size) - return NULL; - - if (shmem->baseptr == NULL) { - KGSL_MEM_VDBG("return: %p\n", NULL); - return NULL; - } - - result = ((physaddr - shmem->physbase) + shmem->baseptr); - - KGSL_MEM_VDBG("return: %p\n", result); - - return result; -} - - -int -kgsl_sharedmem_alloc(uint32_t flags, int size, - struct kgsl_memdesc *memdesc) -{ - struct kgsl_sharedmem *shmem; - int result = -ENOMEM; - unsigned int blksize; - unsigned int baseaddr; - unsigned int alignshift; - unsigned int alignedbaseaddr; - - KGSL_MEM_VDBG("enter (flags=0x%08x, size=%d, memdesc=%p)\n", - flags, size, memdesc); - - shmem = &kgsl_driver.shmem; - BUG_ON(memdesc == NULL); - BUG_ON(size <= 0); - - alignshift = kgsl_memarena_get_order(flags); - - size = ALIGN(size, KGSL_PAGESIZE); - blksize = size; - if (alignshift > KGSL_PAGESIZE_SHIFT) - blksize += (1 << alignshift) - KGSL_PAGESIZE; - - baseaddr = gen_pool_alloc(shmem->pool, blksize); - if (baseaddr == 0) { - KGSL_MEM_ERR("gen_pool_alloc failed\n"); - result = -ENOMEM; - goto done; - } - result = 0; - - if (alignshift > KGSL_PAGESIZE_SHIFT) { - alignedbaseaddr = ALIGN(baseaddr, (1 << alignshift)); - - KGSL_MEM_VDBG("ba %x al %x as %d m->as %d bs %x s %x\n", - baseaddr, alignedbaseaddr, alignshift, - KGSL_PAGESIZE_SHIFT, blksize, size); - if (alignedbaseaddr > baseaddr) { - KGSL_MEM_VDBG("physaddr %x free before %x size %x\n", - alignedbaseaddr, - baseaddr, alignedbaseaddr - baseaddr); - gen_pool_free(shmem->pool, baseaddr, - alignedbaseaddr - baseaddr); - blksize -= alignedbaseaddr - baseaddr; - } - if (blksize > size) { - KGSL_MEM_VDBG("physaddr %x free after %x size %x\n", - alignedbaseaddr, - alignedbaseaddr + size, - blksize - size); - gen_pool_free(shmem->pool, - alignedbaseaddr + size, - blksize - size); - } - } else { - alignedbaseaddr = baseaddr; - } - - memdesc->physaddr = alignedbaseaddr; - memdesc->hostptr = kgsl_memarena_gethostptr(shmem, memdesc->physaddr); - memdesc->size = size; - - KGSL_MEM_VDBG("ashift %d m->ashift %d blksize %d base %x abase %x\n", - alignshift, KGSL_PAGESIZE_SHIFT, blksize, baseaddr, - alignedbaseaddr); - -done: - if (result) - memset(memdesc, 0, sizeof(*memdesc)); - - - KGSL_MEM_VDBG("return: %d\n", result); - return result; -} - -void -kgsl_sharedmem_free(struct kgsl_memdesc *memdesc) -{ - struct kgsl_sharedmem *shmem = &kgsl_driver.shmem; - - KGSL_MEM_VDBG("enter (shmem=%p, memdesc=%p, physaddr=%08x, size=%d)\n", - shmem, memdesc, memdesc->physaddr, memdesc->size); - - BUG_ON(memdesc == NULL); - BUG_ON(memdesc->size <= 0); - BUG_ON(shmem->physbase > memdesc->physaddr); - BUG_ON((shmem->physbase + shmem->size) - < (memdesc->physaddr + memdesc->size)); - - gen_pool_free(shmem->pool, memdesc->physaddr, memdesc->size); - - memset(memdesc, 0, sizeof(struct kgsl_memdesc)); - KGSL_MEM_VDBG("return\n"); -} - -int -kgsl_sharedmem_read(const struct kgsl_memdesc *memdesc, void *dst, - unsigned int offsetbytes, unsigned int sizebytes) -{ - if (memdesc == NULL || memdesc->hostptr == NULL || dst == NULL) { - KGSL_MEM_ERR("bad ptr memdesc %p hostptr %p dst %p\n", - memdesc, - (memdesc ? memdesc->hostptr : NULL), - dst); - return -EINVAL; - } - if (offsetbytes + sizebytes > memdesc->size) { - KGSL_MEM_ERR("bad range: offset %d size %d memdesc %d\n", - offsetbytes, sizebytes, memdesc->size); - return -ERANGE; - } - memcpy(dst, memdesc->hostptr + offsetbytes, sizebytes); - return 0; -} - -int -kgsl_sharedmem_write(const struct kgsl_memdesc *memdesc, - unsigned int offsetbytes, - void *value, unsigned int sizebytes) -{ - if (memdesc == NULL || memdesc->hostptr == NULL) { - KGSL_MEM_ERR("bad ptr memdesc %p hostptr %p\n", memdesc, - (memdesc ? memdesc->hostptr : NULL)); - return -EINVAL; - } - if (offsetbytes + sizebytes > memdesc->size) { - KGSL_MEM_ERR("bad range: offset %d size %d memdesc %d\n", - offsetbytes, sizebytes, memdesc->size); - return -ERANGE; - } - memcpy(memdesc->hostptr + offsetbytes, value, sizebytes); - return 0; -} - -int -kgsl_sharedmem_set(const struct kgsl_memdesc *memdesc, unsigned int offsetbytes, - unsigned int value, unsigned int sizebytes) -{ - if (memdesc == NULL || memdesc->hostptr == NULL) { - KGSL_MEM_ERR("bad ptr memdesc %p hostptr %p\n", memdesc, - (memdesc ? memdesc->hostptr : NULL)); - return -EINVAL; - } - if (offsetbytes + sizebytes > memdesc->size) { - KGSL_MEM_ERR("bad range: offset %d size %d memdesc %d\n", - offsetbytes, sizebytes, memdesc->size); - return -ERANGE; - } - memset(memdesc->hostptr + offsetbytes, value, sizebytes); - return 0; -} - diff --git a/drivers/video/msm/gpu/kgsl/kgsl_sharedmem.h b/drivers/video/msm/gpu/kgsl/kgsl_sharedmem.h deleted file mode 100644 index eaf84063..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_sharedmem.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#ifndef __GSL_SHAREDMEM_H -#define __GSL_SHAREDMEM_H - -#include -#include - -#define KGSL_PAGESIZE 0x1000 -#define KGSL_PAGESIZE_SHIFT 12 -#define KGSL_PAGEMASK (~(KGSL_PAGESIZE - 1)) - -struct kgsl_pagetable; - -struct platform_device; -struct gen_pool; - -/* memory allocation flags */ -#define KGSL_MEMFLAGS_ANY 0x00000000 /*dont care*/ - -#define KGSL_MEMFLAGS_APERTUREANY 0x00000000 -#define KGSL_MEMFLAGS_EMEM 0x00000000 -#define KGSL_MEMFLAGS_CONPHYS 0x00001000 - -#define KGSL_MEMFLAGS_ALIGNANY 0x00000000 -#define KGSL_MEMFLAGS_ALIGN32 0x00000000 -#define KGSL_MEMFLAGS_ALIGN64 0x00060000 -#define KGSL_MEMFLAGS_ALIGN128 0x00070000 -#define KGSL_MEMFLAGS_ALIGN256 0x00080000 -#define KGSL_MEMFLAGS_ALIGN512 0x00090000 -#define KGSL_MEMFLAGS_ALIGN1K 0x000A0000 -#define KGSL_MEMFLAGS_ALIGN2K 0x000B0000 -#define KGSL_MEMFLAGS_ALIGN4K 0x000C0000 -#define KGSL_MEMFLAGS_ALIGN8K 0x000D0000 -#define KGSL_MEMFLAGS_ALIGN16K 0x000E0000 -#define KGSL_MEMFLAGS_ALIGN32K 0x000F0000 -#define KGSL_MEMFLAGS_ALIGN64K 0x00100000 -#define KGSL_MEMFLAGS_ALIGNPAGE KGSL_MEMFLAGS_ALIGN4K - -/* fail the alloc if the flags cannot be honored */ -#define KGSL_MEMFLAGS_STRICTREQUEST 0x80000000 - -#define KGSL_MEMFLAGS_APERTURE_MASK 0x0000F000 -#define KGSL_MEMFLAGS_ALIGN_MASK 0x00FF0000 - -#define KGSL_MEMFLAGS_APERTURE_SHIFT 12 -#define KGSL_MEMFLAGS_ALIGN_SHIFT 16 - - -/* shared memory allocation */ -struct kgsl_memdesc { - struct kgsl_pagetable *pagetable; - void *hostptr; - unsigned int gpuaddr; - unsigned int physaddr; - unsigned int size; - unsigned int priv; -}; - -struct kgsl_sharedmem { - void *baseptr; - unsigned int physbase; - unsigned int size; - struct gen_pool *pool; -}; - -int kgsl_sharedmem_alloc(uint32_t flags, int size, - struct kgsl_memdesc *memdesc); - -/*TODO: add protection flags */ -int kgsl_sharedmem_import(struct kgsl_pagetable *, - uint32_t phys_addr, - uint32_t size, - struct kgsl_memdesc *memdesc); - - -void kgsl_sharedmem_free(struct kgsl_memdesc *memdesc); - - -int kgsl_sharedmem_read(const struct kgsl_memdesc *memdesc, void *dst, - unsigned int offsetbytes, unsigned int sizebytes); - -int kgsl_sharedmem_write(const struct kgsl_memdesc *memdesc, - unsigned int offsetbytes, void *value, - unsigned int sizebytes); - -int kgsl_sharedmem_set(const struct kgsl_memdesc *memdesc, - unsigned int offsetbytes, unsigned int value, - unsigned int sizebytes); - -int kgsl_sharedmem_init(struct kgsl_sharedmem *shmem); - -int kgsl_sharedmem_close(struct kgsl_sharedmem *shmem); - -#endif /* __GSL_SHAREDMEM_H */ diff --git a/drivers/video/msm/gpu/kgsl/kgsl_yamato.c b/drivers/video/msm/gpu/kgsl/kgsl_yamato.c deleted file mode 100644 index b0d6eeec..00000000 --- a/drivers/video/msm/gpu/kgsl/kgsl_yamato.c +++ /dev/null @@ -1,1004 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#include -#include -#include -#include -#include -#include - -#include "kgsl.h" -#include "kgsl_log.h" -#include "kgsl_pm4types.h" -#include "kgsl_cmdstream.h" - -#include "yamato_reg.h" - -#define GSL_RBBM_INT_MASK \ - (RBBM_INT_CNTL__RDERR_INT_MASK | \ - RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK) - -#define GSL_SQ_INT_MASK \ - (SQ_INT_CNTL__PS_WATCHDOG_MASK | \ - SQ_INT_CNTL__VS_WATCHDOG_MASK) - -/* Yamato MH arbiter config*/ -#define KGSL_CFG_YAMATO_MHARB \ - (0x10 \ - | (0 << MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT) \ - | (0 << MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT) \ - | (0 << MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT) \ - | (0x8 << MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT) \ - | (1 << MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT)) - -void kgsl_register_dump(struct kgsl_device *device) -{ - unsigned int regValue; - - kgsl_yamato_regread(device, REG_RBBM_STATUS, ®Value); - KGSL_CMD_ERR("RBBM_STATUS = %8.8X\n", regValue); - kgsl_yamato_regread(device, REG_CP_RB_BASE, ®Value); - KGSL_CMD_ERR("CP_RB_BASE = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_RB_CNTL, ®Value); - KGSL_CMD_ERR("CP_RB_CNTL = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_RB_RPTR_ADDR, ®Value); - KGSL_CMD_ERR("CP_RB_RPTR_ADDR = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_RB_RPTR, ®Value); - KGSL_CMD_ERR("CP_RB_RPTR = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_RB_WPTR, ®Value); - KGSL_CMD_ERR("CP_RB_WPTR = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_RB_RPTR_WR, ®Value); - KGSL_CMD_ERR("CP_RB_RPTR_WR = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_INT_CNTL, ®Value); - KGSL_CMD_ERR("CP_INT_CNTL = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_INT_STATUS, ®Value); - KGSL_CMD_ERR("CP_INT_STATUS = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_ME_CNTL, ®Value); - KGSL_CMD_ERR("CP_ME_CNTL = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_ME_STATUS, ®Value); - KGSL_CMD_ERR("CP_ME_STATUS = %08x\n", regValue); - kgsl_yamato_regread(device, REG_RBBM_PM_OVERRIDE1, ®Value); - KGSL_CMD_ERR("RBBM_PM_OVERRIDE1 = %08x\n", regValue); - kgsl_yamato_regread(device, REG_RBBM_PM_OVERRIDE2, ®Value); - KGSL_CMD_ERR("RBBM_PM_OVERRIDE2 = %08x\n", regValue); - kgsl_yamato_regread(device, REG_RBBM_INT_CNTL, ®Value); - KGSL_CMD_ERR("RBBM_INT_CNTL = %08x\n", regValue); - kgsl_yamato_regread(device, REG_RBBM_INT_STATUS, ®Value); - KGSL_CMD_ERR("RBBM_INT_STATUS = %08x\n", regValue); - kgsl_yamato_regread(device, REG_MASTER_INT_SIGNAL, ®Value); - KGSL_CMD_ERR("MASTER_INT_SIGNAL = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_IB1_BASE, ®Value); - KGSL_CMD_ERR("CP_IB1_BASE = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_IB1_BUFSZ, ®Value); - KGSL_CMD_ERR("CP_IB1_BUFSZ = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_IB2_BASE, ®Value); - KGSL_CMD_ERR("CP_IB2_BASE = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_IB2_BUFSZ, ®Value); - KGSL_CMD_ERR("CP_IB2_BUFSZ = %08x\n", regValue); - kgsl_yamato_regread(device, REG_CP_STAT, ®Value); - KGSL_CMD_ERR("CP_STAT = %08x\n", regValue); - kgsl_yamato_regread(device, REG_SCRATCH_REG0, ®Value); - KGSL_CMD_ERR("SCRATCH_REG0 = %08x\n", regValue); - kgsl_yamato_regread(device, REG_COHER_SIZE_PM4, ®Value); - KGSL_CMD_ERR("COHER_SIZE_PM4 = %08x\n", regValue); - kgsl_yamato_regread(device, REG_COHER_BASE_PM4, ®Value); - KGSL_CMD_ERR("COHER_BASE_PM4 = %08x\n", regValue); - kgsl_yamato_regread(device, REG_COHER_STATUS_PM4, ®Value); - KGSL_CMD_ERR("COHER_STATUS_PM4 = %08x\n", regValue); - kgsl_yamato_regread(device, REG_RBBM_READ_ERROR, ®Value); - KGSL_CMD_ERR("RBBM_READ_ERROR = %08x\n", regValue); - kgsl_yamato_regread(device, REG_MH_AXI_ERROR, ®Value); - KGSL_CMD_ERR("MH_AXI_ERROR = %08x\n", regValue); -} - -static int kgsl_yamato_gmeminit(struct kgsl_device *device) -{ - union reg_rb_edram_info rb_edram_info; - unsigned int gmem_size; - unsigned int edram_value = 0; - - /* make sure edram range is aligned to size */ - BUG_ON(device->gmemspace.gpu_base & (device->gmemspace.sizebytes - 1)); - - /* get edram_size value equivalent */ - gmem_size = (device->gmemspace.sizebytes >> 14); - while (gmem_size >>= 1) - edram_value++; - - rb_edram_info.val = 0; - - rb_edram_info.f.edram_size = edram_value; - rb_edram_info.f.edram_mapping_mode = 0; /* EDRAM_MAP_UPPER */ - /* must be aligned to size */ - rb_edram_info.f.edram_range = (device->gmemspace.gpu_base >> 14); - - kgsl_yamato_regwrite(device, REG_RB_EDRAM_INFO, rb_edram_info.val); - - return 0; -} - -static int kgsl_yamato_gmemclose(struct kgsl_device *device) -{ - kgsl_yamato_regwrite(device, REG_RB_EDRAM_INFO, 0x00000000); - - return 0; -} - -void kgsl_yamato_rbbm_intrcallback(struct kgsl_device *device) -{ - unsigned int status = 0; - unsigned int rderr = 0; - - KGSL_DRV_VDBG("enter (device=%p)\n", device); - - kgsl_yamato_regread(device, REG_RBBM_INT_STATUS, &status); - - if (status & RBBM_INT_CNTL__RDERR_INT_MASK) { - kgsl_yamato_regread(device, REG_RBBM_READ_ERROR, &rderr); - KGSL_DRV_FATAL("rbbm read error interrupt: %08x\n", rderr); - } else if (status & RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK) { - KGSL_DRV_DBG("rbbm display update interrupt\n"); - } else if (status & RBBM_INT_CNTL__GUI_IDLE_INT_MASK) { - KGSL_DRV_DBG("rbbm gui idle interrupt\n"); - } else { - KGSL_CMD_DBG("bad bits in REG_CP_INT_STATUS %08x\n", status); - } - - status &= GSL_RBBM_INT_MASK; - kgsl_yamato_regwrite(device, REG_RBBM_INT_ACK, status); - - KGSL_DRV_VDBG("return\n"); -} - -void kgsl_yamato_sq_intrcallback(struct kgsl_device *device) -{ - unsigned int status = 0; - - KGSL_DRV_VDBG("enter (device=%p)\n", device); - - kgsl_yamato_regread(device, REG_SQ_INT_STATUS, &status); - - if (status & SQ_INT_CNTL__PS_WATCHDOG_MASK) - KGSL_DRV_DBG("sq ps watchdog interrupt\n"); - else if (status & SQ_INT_CNTL__VS_WATCHDOG_MASK) - KGSL_DRV_DBG("sq vs watchdog interrupt\n"); - else - KGSL_DRV_DBG("bad bits in REG_SQ_INT_STATUS %08x\n", status); - - - status &= GSL_SQ_INT_MASK; - kgsl_yamato_regwrite(device, REG_SQ_INT_ACK, status); - - KGSL_DRV_VDBG("return\n"); -} - -irqreturn_t kgsl_yamato_isr(int irq, void *data) -{ - irqreturn_t result = IRQ_NONE; - - struct kgsl_device *device = &kgsl_driver.yamato_device; - unsigned int status; - - kgsl_yamato_regread(device, REG_MASTER_INT_SIGNAL, &status); - - if (status & MASTER_INT_SIGNAL__MH_INT_STAT) { - kgsl_mh_intrcallback(device); - result = IRQ_HANDLED; - } - - if (status & MASTER_INT_SIGNAL__CP_INT_STAT) { - kgsl_cp_intrcallback(device); - result = IRQ_HANDLED; - } - - if (status & MASTER_INT_SIGNAL__RBBM_INT_STAT) { - kgsl_yamato_rbbm_intrcallback(device); - result = IRQ_HANDLED; - } - - if (status & MASTER_INT_SIGNAL__SQ_INT_STAT) { - kgsl_yamato_sq_intrcallback(device); - result = IRQ_HANDLED; - } - - - return result; -} - -int kgsl_yamato_cleanup_pt(struct kgsl_device *device, - struct kgsl_pagetable *pagetable) -{ - kgsl_mmu_unmap(pagetable, device->ringbuffer.buffer_desc.gpuaddr, - device->ringbuffer.buffer_desc.size); - - kgsl_mmu_unmap(pagetable, device->ringbuffer.memptrs_desc.gpuaddr, - device->ringbuffer.memptrs_desc.size); - - kgsl_mmu_unmap(pagetable, device->memstore.gpuaddr, - device->memstore.size); - - kgsl_mmu_unmap(pagetable, device->mmu.dummyspace.gpuaddr, - device->mmu.dummyspace.size); - - return 0; -} - -int kgsl_yamato_setup_pt(struct kgsl_device *device, - struct kgsl_pagetable *pagetable) -{ - int result = 0; - unsigned int gpuaddr; - - BUG_ON(device->ringbuffer.buffer_desc.physaddr == 0); - BUG_ON(device->ringbuffer.memptrs_desc.physaddr == 0); - BUG_ON(device->memstore.physaddr == 0); - BUG_ON(device->mmu.dummyspace.physaddr == 0); - - result = kgsl_mmu_map(pagetable, - device->ringbuffer.buffer_desc.physaddr, - device->ringbuffer.buffer_desc.size, - GSL_PT_PAGE_RV, &gpuaddr, - KGSL_MEMFLAGS_CONPHYS | KGSL_MEMFLAGS_ALIGN4K); - - if (result) - goto error; - - if (device->ringbuffer.buffer_desc.gpuaddr == 0) - device->ringbuffer.buffer_desc.gpuaddr = gpuaddr; - BUG_ON(device->ringbuffer.buffer_desc.gpuaddr != gpuaddr); - - result = kgsl_mmu_map(pagetable, - device->ringbuffer.memptrs_desc.physaddr, - device->ringbuffer.memptrs_desc.size, - GSL_PT_PAGE_RV | GSL_PT_PAGE_WV, &gpuaddr, - KGSL_MEMFLAGS_CONPHYS | KGSL_MEMFLAGS_ALIGN4K); - if (result) - goto unmap_buffer_desc; - - if (device->ringbuffer.memptrs_desc.gpuaddr == 0) - device->ringbuffer.memptrs_desc.gpuaddr = gpuaddr; - BUG_ON(device->ringbuffer.memptrs_desc.gpuaddr != gpuaddr); - - result = kgsl_mmu_map(pagetable, device->memstore.physaddr, - device->memstore.size, - GSL_PT_PAGE_RV | GSL_PT_PAGE_WV, &gpuaddr, - KGSL_MEMFLAGS_CONPHYS | KGSL_MEMFLAGS_ALIGN4K); - if (result) - goto unmap_memptrs_desc; - - if (device->memstore.gpuaddr == 0) - device->memstore.gpuaddr = gpuaddr; - BUG_ON(device->memstore.gpuaddr != gpuaddr); - - result = kgsl_mmu_map(pagetable, - device->mmu.dummyspace.physaddr, - device->mmu.dummyspace.size, - GSL_PT_PAGE_RV | GSL_PT_PAGE_WV, &gpuaddr, - KGSL_MEMFLAGS_CONPHYS | KGSL_MEMFLAGS_ALIGN4K); - - if (result) - goto unmap_memstore_desc; - - if (device->mmu.dummyspace.gpuaddr == 0) - device->mmu.dummyspace.gpuaddr = gpuaddr; - BUG_ON(device->mmu.dummyspace.gpuaddr != gpuaddr); - - return result; - -unmap_memstore_desc: - kgsl_mmu_unmap(pagetable, device->memstore.gpuaddr, - device->memstore.size); - -unmap_memptrs_desc: - kgsl_mmu_unmap(pagetable, device->ringbuffer.memptrs_desc.gpuaddr, - device->ringbuffer.memptrs_desc.size); -unmap_buffer_desc: - kgsl_mmu_unmap(pagetable, device->ringbuffer.buffer_desc.gpuaddr, - device->ringbuffer.buffer_desc.size); -error: - return result; - -} - -#ifdef CONFIG_GPU_MSM_KGSL_MMU -int kgsl_yamato_setstate(struct kgsl_device *device, uint32_t flags) -{ - unsigned int link[32]; - unsigned int *cmds = &link[0]; - int sizedwords = 0; - unsigned int mh_mmu_invalidate = 0x00000003; /*invalidate all and tc */ - - KGSL_MEM_DBG("device %p ctxt %p pt %p\n", - device, - device->drawctxt_active, - device->mmu.hwpagetable); - /* if possible, set via command stream, - * otherwise set via direct register writes - */ - if (device->drawctxt_active) { - KGSL_MEM_DBG("cmds\n"); - if (flags & KGSL_MMUFLAGS_PTUPDATE) { - /* wait for graphics pipe to be idle */ - *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmds++ = 0x00000000; - - /* set page table base */ - *cmds++ = pm4_type0_packet(REG_MH_MMU_PT_BASE, 1); - *cmds++ = device->mmu.hwpagetable->base.gpuaddr; - sizedwords += 4; - } - - if (flags & KGSL_MMUFLAGS_TLBFLUSH) { - *cmds++ = pm4_type0_packet(REG_MH_MMU_INVALIDATE, 1); - *cmds++ = mh_mmu_invalidate; - sizedwords += 2; - } - - if (flags & KGSL_MMUFLAGS_PTUPDATE) { - /* HW workaround: to resolve MMU page fault interrupts - * caused by the VGT.It prevents the CP PFP from filling - * the VGT DMA request fifo too early,thereby ensuring - * that the VGT will not fetch vertex/bin data until - * after the page table base register has been updated. - * - * Two null DRAW_INDX_BIN packets are inserted right - * after the page table base update, followed by a - * wait for idle. The null packets will fill up the - * VGT DMA request fifo and prevent any further - * vertex/bin updates from occurring until the wait - * has finished. */ - *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); - *cmds++ = (0x4 << 16) | - (REG_PA_SU_SC_MODE_CNTL - 0x2000); - *cmds++ = 0; /* disable faceness generation */ - *cmds++ = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1); - *cmds++ = device->mmu.dummyspace.gpuaddr; - *cmds++ = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6); - *cmds++ = 0; /* viz query info */ - *cmds++ = 0x0003C004; /* draw indicator */ - *cmds++ = 0; /* bin base */ - *cmds++ = 3; /* bin size */ - *cmds++ = device->mmu.dummyspace.gpuaddr; /* dma base */ - *cmds++ = 6; /* dma size */ - *cmds++ = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6); - *cmds++ = 0; /* viz query info */ - *cmds++ = 0x0003C004; /* draw indicator */ - *cmds++ = 0; /* bin base */ - *cmds++ = 3; /* bin size */ - /* dma base */ - *cmds++ = device->mmu.dummyspace.gpuaddr; - *cmds++ = 6; /* dma size */ - *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); - *cmds++ = 0x00000000; - sizedwords += 21; - } - - if (flags & (KGSL_MMUFLAGS_PTUPDATE | KGSL_MMUFLAGS_TLBFLUSH)) { - *cmds++ = pm4_type3_packet(PM4_INVALIDATE_STATE, 1); - *cmds++ = 0x7fff; /* invalidate all base pointers */ - sizedwords += 2; - } - - kgsl_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_PMODE, - &link[0], sizedwords); - } else { - KGSL_MEM_DBG("regs\n"); - - if (flags & KGSL_MMUFLAGS_PTUPDATE) { - kgsl_yamato_idle(device, KGSL_TIMEOUT_DEFAULT); - kgsl_yamato_regwrite(device, REG_MH_MMU_PT_BASE, - device->mmu.hwpagetable->base.gpuaddr); - } - - if (flags & KGSL_MMUFLAGS_TLBFLUSH) { - kgsl_yamato_regwrite(device, REG_MH_MMU_INVALIDATE, - mh_mmu_invalidate); - } - } - - return 0; -} -#endif - -static unsigned int -kgsl_yamato_getchipid(struct kgsl_device *device) -{ - unsigned int chipid; - unsigned int coreid, majorid, minorid, patchid, revid; - - /* YDX */ - kgsl_yamato_regread(device, REG_RBBM_PERIPHID1, &coreid); - coreid &= 0xF; - - kgsl_yamato_regread(device, REG_RBBM_PERIPHID2, &majorid); - majorid = (majorid >> 4) & 0xF; - - kgsl_yamato_regread(device, REG_RBBM_PATCH_RELEASE, &revid); - /* this is a 16bit field, but extremely unlikely it would ever get - * this high - */ - minorid = ((revid >> 0) & 0xFF); - - - patchid = ((revid >> 16) & 0xFF); - - chipid = ((coreid << 24) | (majorid << 16) | - (minorid << 8) | (patchid << 0)); - - /* Hardware revision 211 (8650) returns the wrong chip ID */ - if (chipid == KGSL_CHIPID_YAMATODX_REV21) - chipid = KGSL_CHIPID_YAMATODX_REV211; - - return chipid; -} - -int kgsl_yamato_init(struct kgsl_device *device, struct kgsl_devconfig *config) -{ - int status = -EINVAL; - int init_reftimestamp = 0x7fffffff; - struct kgsl_memregion *regspace = &device->regspace; - unsigned int memflags = KGSL_MEMFLAGS_ALIGNPAGE | KGSL_MEMFLAGS_CONPHYS; - - KGSL_DRV_VDBG("enter (device=%p, config=%p)\n", device, config); - - if (device->flags & KGSL_FLAGS_INITIALIZED) { - KGSL_DRV_VDBG("return %d\n", 0); - return 0; - } - memset(device, 0, sizeof(*device)); - - init_waitqueue_head(&device->ib1_wq); - - memcpy(regspace, &config->regspace, sizeof(device->regspace)); - if (regspace->mmio_phys_base == 0 || regspace->sizebytes == 0) { - KGSL_DRV_ERR("dev %d invalid regspace\n", device->id); - goto error; - } - if (!request_mem_region(regspace->mmio_phys_base, - regspace->sizebytes, DRIVER_NAME)) { - KGSL_DRV_ERR("request_mem_region failed for register memory\n"); - status = -ENODEV; - goto error; - } - - regspace->mmio_virt_base = ioremap(regspace->mmio_phys_base, - regspace->sizebytes); - KGSL_MEM_INFO("ioremap(regs) = %p\n", regspace->mmio_virt_base); - if (regspace->mmio_virt_base == NULL) { - KGSL_DRV_ERR("ioremap failed for register memory\n"); - status = -ENODEV; - goto error_release_mem; - } - - KGSL_DRV_INFO("dev %d regs phys 0x%08x size 0x%08x virt %p\n", - device->id, regspace->mmio_phys_base, - regspace->sizebytes, regspace->mmio_virt_base); - - memcpy(&device->gmemspace, &config->gmemspace, - sizeof(device->gmemspace)); - - device->id = KGSL_DEVICE_YAMATO; - - if (config->mmu_config) { - device->mmu.config = config->mmu_config; - device->mmu.mpu_base = config->mpu_base; - device->mmu.mpu_range = config->mpu_range; - device->mmu.va_base = config->va_base; - device->mmu.va_range = config->va_range; - } - - device->chip_id = kgsl_yamato_getchipid(device); - - /*We need to make sure all blocks are powered up and clocked before - *issuing a soft reset. The overrides will be turned off (set to 0) - *later in kgsl_yamato_start. - */ - kgsl_yamato_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0xfffffffe); - kgsl_yamato_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0xffffffff); - - kgsl_yamato_regwrite(device, REG_RBBM_SOFT_RESET, 0xFFFFFFFF); - msleep(50); - kgsl_yamato_regwrite(device, REG_RBBM_SOFT_RESET, 0x00000000); - - kgsl_yamato_regwrite(device, REG_RBBM_CNTL, 0x00004442); - - kgsl_yamato_regwrite(device, REG_MH_ARBITER_CONFIG, - KGSL_CFG_YAMATO_MHARB); - - kgsl_yamato_regwrite(device, REG_SQ_VS_PROGRAM, 0x00000000); - kgsl_yamato_regwrite(device, REG_SQ_PS_PROGRAM, 0x00000000); - - - status = kgsl_mmu_init(device); - if (status != 0) { - status = -ENODEV; - goto error_iounmap; - } - - status = kgsl_cmdstream_init(device); - if (status != 0) { - status = -ENODEV; - goto error_close_mmu; - } - - status = kgsl_sharedmem_alloc(memflags, sizeof(device->memstore), - &device->memstore); - if (status != 0) { - status = -ENODEV; - goto error_close_cmdstream; - } - kgsl_sharedmem_set(&device->memstore, 0, 0, device->memstore.size); - - kgsl_sharedmem_write(&device->memstore, - KGSL_DEVICE_MEMSTORE_OFFSET(ref_wait_ts), - &init_reftimestamp, 4); - - kgsl_yamato_regwrite(device, REG_RBBM_DEBUG, 0x00080000); - pr_info("msm_kgsl: initilized dev=%d mmu=%s\n", device->id, - kgsl_mmu_isenabled(&device->mmu) ? "on" : "off"); - - device->flags |= KGSL_FLAGS_INITIALIZED; - return 0; - -error_close_cmdstream: - kgsl_cmdstream_close(device); -error_close_mmu: - kgsl_mmu_close(device); -error_iounmap: - iounmap(regspace->mmio_virt_base); - regspace->mmio_virt_base = NULL; -error_release_mem: - release_mem_region(regspace->mmio_phys_base, regspace->sizebytes); -error: - return status; -} - -int kgsl_yamato_close(struct kgsl_device *device) -{ - struct kgsl_memregion *regspace = &device->regspace; - - if (device->memstore.hostptr) - kgsl_sharedmem_free(&device->memstore); - - kgsl_mmu_close(device); - - kgsl_cmdstream_close(device); - - if (regspace->mmio_virt_base != NULL) { - KGSL_MEM_INFO("iounmap(regs) = %p\n", regspace->mmio_virt_base); - iounmap(regspace->mmio_virt_base); - regspace->mmio_virt_base = NULL; - release_mem_region(regspace->mmio_phys_base, - regspace->sizebytes); - } - - KGSL_DRV_VDBG("return %d\n", 0); - device->flags &= ~KGSL_FLAGS_INITIALIZED; - return 0; -} - -int kgsl_yamato_start(struct kgsl_device *device, uint32_t flags) -{ - int status = -EINVAL; - - KGSL_DRV_VDBG("enter (device=%p)\n", device); - - if (!(device->flags & KGSL_FLAGS_INITIALIZED)) { - KGSL_DRV_ERR("Trying to start uninitialized device.\n"); - return -EINVAL; - } - - device->refcnt++; - - if (device->flags & KGSL_FLAGS_STARTED) { - KGSL_DRV_VDBG("already started"); - return 0; - } - - kgsl_yamato_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0); - kgsl_yamato_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0); - - KGSL_DRV_DBG("enabling RBBM interrupts mask 0x%08lx\n", - GSL_RBBM_INT_MASK); - kgsl_yamato_regwrite(device, REG_RBBM_INT_CNTL, GSL_RBBM_INT_MASK); - - /* make sure SQ interrupts are disabled */ - kgsl_yamato_regwrite(device, REG_SQ_INT_CNTL, 0); - - kgsl_yamato_gmeminit(device); - - status = kgsl_ringbuffer_init(device); - if (status != 0) { - kgsl_yamato_stop(device); - return status; - } - - status = kgsl_drawctxt_init(device); - if (status != 0) { - kgsl_yamato_stop(device); - return status; - } - - device->flags |= KGSL_FLAGS_STARTED; - - KGSL_DRV_VDBG("return %d\n", status); - return status; -} - -int kgsl_yamato_stop(struct kgsl_device *device) -{ - if (device->flags & KGSL_FLAGS_STARTED) { - - kgsl_yamato_regwrite(device, REG_RBBM_INT_CNTL, 0); - - kgsl_yamato_regwrite(device, REG_SQ_INT_CNTL, 0); - - kgsl_drawctxt_close(device); - - kgsl_ringbuffer_close(&device->ringbuffer); - - kgsl_yamato_gmemclose(device); - - device->flags &= ~KGSL_FLAGS_STARTED; - } - - return 0; -} - -int kgsl_yamato_getproperty(struct kgsl_device *device, - enum kgsl_property_type type, - void *value, - unsigned int sizebytes) -{ - int status = -EINVAL; - - switch (type) { - case KGSL_PROP_DEVICE_INFO: - { - struct kgsl_devinfo devinfo; - - if (sizebytes != sizeof(devinfo)) { - status = -EINVAL; - break; - } - - memset(&devinfo, 0, sizeof(devinfo)); - devinfo.device_id = device->id; - devinfo.chip_id = device->chip_id; - devinfo.mmu_enabled = kgsl_mmu_isenabled(&device->mmu); - devinfo.gmem_hostbaseaddr = - (unsigned int)device->gmemspace.mmio_virt_base; - devinfo.gmem_gpubaseaddr = device->gmemspace.gpu_base; - devinfo.gmem_sizebytes = device->gmemspace.sizebytes; - - if (copy_to_user(value, &devinfo, sizeof(devinfo)) != - 0) { - status = -EFAULT; - break; - } - status = 0; - } - break; - case KGSL_PROP_DEVICE_SHADOW: - { - struct kgsl_shadowprop shadowprop; - - if (sizebytes != sizeof(shadowprop)) { - status = -EINVAL; - break; - } - memset(&shadowprop, 0, sizeof(shadowprop)); - if (device->memstore.hostptr) { - /*NOTE: with mmu enabled, gpuaddr doesn't mean - * anything to mmap(). - */ - shadowprop.gpuaddr = device->memstore.physaddr; - shadowprop.size = device->memstore.size; - shadowprop.flags = KGSL_FLAGS_INITIALIZED; - } - if (copy_to_user(value, &shadowprop, - sizeof(shadowprop))) { - status = -EFAULT; - break; - } - status = 0; - } - break; - case KGSL_PROP_MMU_ENABLE: - { -#ifdef CONFIG_GPU_MSM_KGSL_MMU - int mmuProp = 1; -#else - int mmuProp = 0; -#endif - if (sizebytes != sizeof(int)) { - status = -EINVAL; - break; - } - if (copy_to_user(value, &mmuProp, sizeof(mmuProp))) { - status = -EFAULT; - break; - } - status = 0; - } - break; - case KGSL_PROP_INTERRUPT_WAITS: - { - int int_waits = 1; - if (sizebytes != sizeof(int)) { - status = -EINVAL; - break; - } - if (copy_to_user(value, &int_waits, sizeof(int))) { - status = -EFAULT; - break; - } - status = 0; - } - break; - default: - status = -EINVAL; - } - - return status; -} - -/* Note: This is either called from the standby timer, or while holding the - * driver mutex. - * - * The reader may obseve that this function may be called without holding the - * driver mutex (in the timer), which can cause the ringbuffer write pointer - * to change, when a user submits a command. However, the user must be holding - * the driver mutex when doing so, and then must - * have canceled the timer. If the timer was executing at the time of - * cancellation, the active flag would have been cleared, which the user - * ioctl checks for after cancelling the timer. - */ -bool kgsl_yamato_is_idle(struct kgsl_device *device) -{ - struct kgsl_ringbuffer *rb = &device->ringbuffer; - unsigned int rbbm_status; - - BUG_ON(!(rb->flags & KGSL_FLAGS_STARTED)); - - GSL_RB_GET_READPTR(rb, &rb->rptr); - if (rb->rptr == rb->wptr) { - kgsl_yamato_regread(device, REG_RBBM_STATUS, &rbbm_status); - if (rbbm_status == 0x110) - return true; - } - return false; -} - -int kgsl_yamato_idle(struct kgsl_device *device, unsigned int timeout) -{ - int status = -EINVAL; - struct kgsl_ringbuffer *rb = &device->ringbuffer; - struct kgsl_mmu_debug mmu_dbg; - unsigned int rbbm_status; - int idle_count = 0; -#define IDLE_COUNT_MAX 1000000 - - KGSL_DRV_VDBG("enter (device=%p, timeout=%d)\n", device, timeout); - - (void)timeout; - - /* first, wait until the CP has consumed all the commands in - * the ring buffer - */ - if (rb->flags & KGSL_FLAGS_STARTED) { - do { - idle_count++; - GSL_RB_GET_READPTR(rb, &rb->rptr); - - } while (rb->rptr != rb->wptr && idle_count < IDLE_COUNT_MAX); - if (idle_count == IDLE_COUNT_MAX) - goto err; - } - /* now, wait for the GPU to finish its operations */ - for (idle_count = 0; idle_count < IDLE_COUNT_MAX; idle_count++) { - kgsl_yamato_regread(device, REG_RBBM_STATUS, &rbbm_status); - - if (rbbm_status == 0x110) { - status = 0; - goto done; - } - } - -err: - KGSL_DRV_ERR("spun too long waiting for RB to idle\n"); - kgsl_register_dump(device); - kgsl_ringbuffer_dump(rb); - kgsl_mmu_debug(&device->mmu, &mmu_dbg); - BUG(); - -done: - KGSL_DRV_VDBG("return %d\n", status); - - return status; -} - -int kgsl_yamato_regread(struct kgsl_device *device, unsigned int offsetwords, - unsigned int *value) -{ - unsigned int *reg; - - if (offsetwords*sizeof(uint32_t) >= device->regspace.sizebytes) { - KGSL_DRV_ERR("invalid offset %d\n", offsetwords); - return -ERANGE; - } - - reg = (unsigned int *)(device->regspace.mmio_virt_base - + (offsetwords << 2)); - *value = readl(reg); - - return 0; -} - -int kgsl_yamato_regwrite(struct kgsl_device *device, unsigned int offsetwords, - unsigned int value) -{ - unsigned int *reg; - - if (offsetwords*sizeof(uint32_t) >= device->regspace.sizebytes) { - KGSL_DRV_ERR("invalid offset %d\n", offsetwords); - return -ERANGE; - } - - reg = (unsigned int *)(device->regspace.mmio_virt_base - + (offsetwords << 2)); - writel(value, reg); - - return 0; -} - -static inline int _wait_timestamp(struct kgsl_device *device, - unsigned int timestamp, - unsigned int msecs) -{ - long status; - - status = wait_event_interruptible_timeout(device->ib1_wq, - kgsl_cmdstream_check_timestamp(device, timestamp), - msecs_to_jiffies(msecs)); - - if (status > 0) - status = 0; - else if (status == 0) { - if (!kgsl_cmdstream_check_timestamp(device, timestamp)) { - status = -ETIMEDOUT; - kgsl_register_dump(device); - } - } - - return (int)status; -} - -/* MUST be called with the kgsl_driver.mutex held */ -int kgsl_yamato_waittimestamp(struct kgsl_device *device, - unsigned int timestamp, - unsigned int msecs) -{ - long status = 0; - uint32_t ref_ts; - int enableflag = 1; - unsigned int cmd[2]; - - KGSL_DRV_INFO("enter (device=%p,timestamp=%d,timeout=0x%08x)\n", - device, timestamp, msecs); - - if (!kgsl_cmdstream_check_timestamp(device, timestamp)) { - kgsl_sharedmem_read(&device->memstore, &ref_ts, - KGSL_DEVICE_MEMSTORE_OFFSET(ref_wait_ts), 4); - if (timestamp_cmp(ref_ts, timestamp)) { - kgsl_sharedmem_write(&device->memstore, - KGSL_DEVICE_MEMSTORE_OFFSET(ref_wait_ts), - ×tamp, 4); - } - - cmd[0] = pm4_type3_packet(PM4_INTERRUPT, 1); - cmd[1] = CP_INT_CNTL__IB1_INT_MASK; - kgsl_ringbuffer_issuecmds(device, KGSL_CMD_FLAGS_NO_TS_CMP, - cmd, 2); - kgsl_sharedmem_write(&device->memstore, - KGSL_DEVICE_MEMSTORE_OFFSET(ts_cmp_enable), - &enableflag, 4); - - mutex_unlock(&kgsl_driver.mutex); - status = _wait_timestamp(device, timestamp, msecs); - mutex_lock(&kgsl_driver.mutex); - } - - KGSL_DRV_INFO("return %ld\n", status); - return (int)status; -} - -int kgsl_yamato_runpending(struct kgsl_device *device) -{ - if (device->flags & KGSL_FLAGS_INITIALIZED) - kgsl_cmdstream_memqueue_drain(device); - return 0; -} - -int __init kgsl_yamato_config(struct kgsl_devconfig *devconfig, - struct platform_device *pdev) -{ - int result = 0; - struct resource *res = NULL; - - memset(devconfig, 0, sizeof(*devconfig)); - - /*find memory regions */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "kgsl_reg_memory"); - if (res == NULL) { - KGSL_DRV_ERR("platform_get_resource_byname failed\n"); - result = -EINVAL; - goto done; - } - KGSL_DRV_DBG("registers at %08x to %08x\n", res->start, res->end); - devconfig->regspace.mmio_phys_base = res->start; - devconfig->regspace.sizebytes = resource_size(res); - - devconfig->gmemspace.gpu_base = 0; - devconfig->gmemspace.sizebytes = SZ_256K; - - /*note: for all of these behavior masks: - * 0 = do not translate - * 1 = translate within va_range, otherwise use physical - * 2 = translate within va_range, otherwise fault - */ - devconfig->mmu_config = 1 /* mmu enable */ - | (2 << MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT) - | (2 << MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT); - - /*TODO: these should probably be configurable from platform device - * stuff */ - devconfig->va_base = 0x66000000; - devconfig->va_range = SZ_128M; - - /* turn off memory protection unit by setting acceptable physical - * address range to include all pages. Apparrently MPU causing - * problems. - */ - devconfig->mpu_base = 0x00000000; - devconfig->mpu_range = 0xFFFFF000; - - result = 0; -done: - return result; -} diff --git a/drivers/video/msm/gpu/kgsl/yamato_reg.h b/drivers/video/msm/gpu/kgsl/yamato_reg.h deleted file mode 100644 index 828b95aa..00000000 --- a/drivers/video/msm/gpu/kgsl/yamato_reg.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * (C) Copyright Advanced Micro Devices, Inc. 2002, 2007 - * Copyright (c) 2008-2009 QUALCOMM USA, INC. - * - * All source code in this file is licensed under the following license - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ -#ifndef _YAMATO_REG_H -#define _YAMATO_REG_H - -enum VGT_EVENT_TYPE { - VS_DEALLOC = 0, - PS_DEALLOC = 1, - VS_DONE_TS = 2, - PS_DONE_TS = 3, - CACHE_FLUSH_TS = 4, - CONTEXT_DONE = 5, - CACHE_FLUSH = 6, - VIZQUERY_START = 7, - VIZQUERY_END = 8, - SC_WAIT_WC = 9, - RST_PIX_CNT = 13, - RST_VTX_CNT = 14, - TILE_FLUSH = 15, - CACHE_FLUSH_AND_INV_TS_EVENT = 20, - ZPASS_DONE = 21, - CACHE_FLUSH_AND_INV_EVENT = 22, - PERFCOUNTER_START = 23, - PERFCOUNTER_STOP = 24, - VS_FETCH_DONE = 27, - FACENESS_FLUSH = 28, -}; - -enum COLORFORMATX { - COLORX_4_4_4_4 = 0, - COLORX_1_5_5_5 = 1, - COLORX_5_6_5 = 2, - COLORX_8 = 3, - COLORX_8_8 = 4, - COLORX_8_8_8_8 = 5, - COLORX_S8_8_8_8 = 6, - COLORX_16_FLOAT = 7, - COLORX_16_16_FLOAT = 8, - COLORX_16_16_16_16_FLOAT = 9, - COLORX_32_FLOAT = 10, - COLORX_32_32_FLOAT = 11, - COLORX_32_32_32_32_FLOAT = 12, - COLORX_2_3_3 = 13, - COLORX_8_8_8 = 14, -}; - -enum SURFACEFORMAT { - FMT_1_REVERSE = 0, - FMT_1 = 1, - FMT_8 = 2, - FMT_1_5_5_5 = 3, - FMT_5_6_5 = 4, - FMT_6_5_5 = 5, - FMT_8_8_8_8 = 6, - FMT_2_10_10_10 = 7, - FMT_8_A = 8, - FMT_8_B = 9, - FMT_8_8 = 10, - FMT_Cr_Y1_Cb_Y0 = 11, - FMT_Y1_Cr_Y0_Cb = 12, - FMT_5_5_5_1 = 13, - FMT_8_8_8_8_A = 14, - FMT_4_4_4_4 = 15, - FMT_10_11_11 = 16, - FMT_11_11_10 = 17, - FMT_DXT1 = 18, - FMT_DXT2_3 = 19, - FMT_DXT4_5 = 20, - FMT_24_8 = 22, - FMT_24_8_FLOAT = 23, - FMT_16 = 24, - FMT_16_16 = 25, - FMT_16_16_16_16 = 26, - FMT_16_EXPAND = 27, - FMT_16_16_EXPAND = 28, - FMT_16_16_16_16_EXPAND = 29, - FMT_16_FLOAT = 30, - FMT_16_16_FLOAT = 31, - FMT_16_16_16_16_FLOAT = 32, - FMT_32 = 33, - FMT_32_32 = 34, - FMT_32_32_32_32 = 35, - FMT_32_FLOAT = 36, - FMT_32_32_FLOAT = 37, - FMT_32_32_32_32_FLOAT = 38, - FMT_32_AS_8 = 39, - FMT_32_AS_8_8 = 40, - FMT_16_MPEG = 41, - FMT_16_16_MPEG = 42, - FMT_8_INTERLACED = 43, - FMT_32_AS_8_INTERLACED = 44, - FMT_32_AS_8_8_INTERLACED = 45, - FMT_16_INTERLACED = 46, - FMT_16_MPEG_INTERLACED = 47, - FMT_16_16_MPEG_INTERLACED = 48, - FMT_DXN = 49, - FMT_8_8_8_8_AS_16_16_16_16 = 50, - FMT_DXT1_AS_16_16_16_16 = 51, - FMT_DXT2_3_AS_16_16_16_16 = 52, - FMT_DXT4_5_AS_16_16_16_16 = 53, - FMT_2_10_10_10_AS_16_16_16_16 = 54, - FMT_10_11_11_AS_16_16_16_16 = 55, - FMT_11_11_10_AS_16_16_16_16 = 56, - FMT_32_32_32_FLOAT = 57, - FMT_DXT3A = 58, - FMT_DXT5A = 59, - FMT_CTX1 = 60, - FMT_DXT3A_AS_1_1_1_1 = 61 -}; - -#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 -#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 -#define RB_EDRAM_INFO_UNUSED0_SIZE 8 -#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 - -struct rb_edram_info_t { - unsigned int edram_size:RB_EDRAM_INFO_EDRAM_SIZE_SIZE; - unsigned int edram_mapping_mode:RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; - unsigned int unused0:RB_EDRAM_INFO_UNUSED0_SIZE; - unsigned int edram_range:RB_EDRAM_INFO_EDRAM_RANGE_SIZE; -}; - -union reg_rb_edram_info { - unsigned int val:32; - struct rb_edram_info_t f; -}; - -#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 -#define CP_RB_CNTL_UNUSED0_SIZE 2 -#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 -#define CP_RB_CNTL_UNUSED1_SIZE 2 -#define CP_RB_CNTL_BUF_SWAP_SIZE 2 -#define CP_RB_CNTL_UNUSED2_SIZE 2 -#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 -#define CP_RB_CNTL_UNUSED3_SIZE 6 -#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 -#define CP_RB_CNTL_UNUSED4_SIZE 3 -#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 - -struct cp_rb_cntl_t { - unsigned int rb_bufsz:CP_RB_CNTL_RB_BUFSZ_SIZE; - unsigned int unused0:CP_RB_CNTL_UNUSED0_SIZE; - unsigned int rb_blksz:CP_RB_CNTL_RB_BLKSZ_SIZE; - unsigned int unused1:CP_RB_CNTL_UNUSED1_SIZE; - unsigned int buf_swap:CP_RB_CNTL_BUF_SWAP_SIZE; - unsigned int unused2:CP_RB_CNTL_UNUSED2_SIZE; - unsigned int rb_poll_en:CP_RB_CNTL_RB_POLL_EN_SIZE; - unsigned int unused3:CP_RB_CNTL_UNUSED3_SIZE; - unsigned int rb_no_update:CP_RB_CNTL_RB_NO_UPDATE_SIZE; - unsigned int unused4:CP_RB_CNTL_UNUSED4_SIZE; - unsigned int rb_rptr_wr_ena:CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; -}; - -union reg_cp_rb_cntl { - unsigned int val:32; - struct cp_rb_cntl_t f; -}; - -#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL -#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 - - -#define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L -#define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L - -#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L -#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L -#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L - -#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L -#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L -#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L - -#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL -#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L -#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L -#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L -#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L -#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L -#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L -#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L -#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L -#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L -#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L -#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L -#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L -#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L -#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L -#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L -#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L -#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L -#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L -#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L - -#define CP_INT_CNTL__SW_INT_MASK 0x00080000L -#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L -#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L -#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L -#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L -#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L -#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L -#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L -#define CP_INT_CNTL__RB_INT_MASK 0x80000000L - -#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L -#define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L -#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L -#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L - -#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL -#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L - -#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 -#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 -#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 -#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 -#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a -#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d -#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e -#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f -#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 -#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 -#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 -#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 -#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 -#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a - -#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 -#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 -#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 -#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a -#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c -#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e -#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 -#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 -#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 -#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 -#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018 - -#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 -#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 -#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 -#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b - -#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 -#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 -#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e - -#define REG_CP_CSQ_IB1_STAT 0x01FE -#define REG_CP_CSQ_IB2_STAT 0x01FF -#define REG_CP_CSQ_RB_STAT 0x01FD -#define REG_CP_DEBUG 0x01FC -#define REG_CP_IB1_BASE 0x0458 -#define REG_CP_IB1_BUFSZ 0x0459 -#define REG_CP_IB2_BASE 0x045A -#define REG_CP_IB2_BUFSZ 0x045B -#define REG_CP_INT_ACK 0x01F4 -#define REG_CP_INT_CNTL 0x01F2 -#define REG_CP_INT_STATUS 0x01F3 -#define REG_CP_ME_CNTL 0x01F6 -#define REG_CP_ME_RAM_DATA 0x01FA -#define REG_CP_ME_RAM_WADDR 0x01F8 -#define REG_CP_ME_STATUS 0x01F7 -#define REG_CP_PFP_UCODE_ADDR 0x00C0 -#define REG_CP_PFP_UCODE_DATA 0x00C1 -#define REG_CP_QUEUE_THRESHOLDS 0x01D5 -#define REG_CP_RB_BASE 0x01C0 -#define REG_CP_RB_CNTL 0x01C1 -#define REG_CP_RB_RPTR 0x01C4 -#define REG_CP_RB_RPTR_ADDR 0x01C3 -#define REG_CP_RB_RPTR_WR 0x01C7 -#define REG_CP_RB_WPTR 0x01C5 -#define REG_CP_RB_WPTR_BASE 0x01C8 -#define REG_CP_RB_WPTR_DELAY 0x01C6 -#define REG_CP_STAT 0x047F -#define REG_CP_STATE_DEBUG_DATA 0x01ED -#define REG_CP_STATE_DEBUG_INDEX 0x01EC -#define REG_CP_ST_BASE 0x044D -#define REG_CP_ST_BUFSZ 0x044E - -#define REG_MASTER_INT_SIGNAL 0x03B7 - -#define REG_MH_ARBITER_CONFIG 0x0A40 -#define REG_MH_INTERRUPT_CLEAR 0x0A44 -#define REG_MH_INTERRUPT_MASK 0x0A42 -#define REG_MH_INTERRUPT_STATUS 0x0A43 -#define REG_MH_MMU_CONFIG 0x0040 -#define REG_MH_MMU_INVALIDATE 0x0045 -#define REG_MH_MMU_MPU_BASE 0x0046 -#define REG_MH_MMU_MPU_END 0x0047 -#define REG_MH_MMU_PAGE_FAULT 0x0043 -#define REG_MH_MMU_PT_BASE 0x0042 -#define REG_MH_MMU_TRAN_ERROR 0x0044 -#define REG_MH_MMU_VA_RANGE 0x0041 - -#define REG_PA_CL_VPORT_XSCALE 0x210F -#define REG_PA_CL_VPORT_ZOFFSET 0x2114 -#define REG_PA_CL_VPORT_ZSCALE 0x2113 -#define REG_PA_CL_VTE_CNTL 0x2206 -#define REG_PA_SC_AA_MASK 0x2312 -#define REG_PA_SC_LINE_CNTL 0x2300 -#define REG_PA_SC_SCREEN_SCISSOR_BR 0x200F -#define REG_PA_SC_SCREEN_SCISSOR_TL 0x200E -#define REG_PA_SC_VIZ_QUERY 0x2293 -#define REG_PA_SC_VIZ_QUERY_STATUS 0x0C44 -#define REG_PA_SC_WINDOW_OFFSET 0x2080 -#define REG_PA_SC_WINDOW_SCISSOR_BR 0x2082 -#define REG_PA_SC_WINDOW_SCISSOR_TL 0x2081 -#define REG_PA_SU_FACE_DATA 0x0C86 -#define REG_PA_SU_POINT_SIZE 0x2280 -#define REG_PA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 -#define REG_PA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 -#define REG_PA_SU_SC_MODE_CNTL 0x2205 - -#define REG_RBBM_CNTL 0x003B -#define REG_RBBM_INT_ACK 0x03B6 -#define REG_RBBM_INT_CNTL 0x03B4 -#define REG_RBBM_INT_STATUS 0x03B5 -#define REG_RBBM_PATCH_RELEASE 0x0001 -#define REG_RBBM_PERIPHID1 0x03F9 -#define REG_RBBM_PERIPHID2 0x03FA -#define REG_RBBM_DEBUG 0x039B -#define REG_RBBM_PM_OVERRIDE1 0x039C -#define REG_RBBM_PM_OVERRIDE2 0x039D -#define REG_RBBM_READ_ERROR 0x03B3 -#define REG_RBBM_SOFT_RESET 0x003C -#define REG_RBBM_STATUS 0x05D0 - -#define REG_RB_COLORCONTROL 0x2202 -#define REG_RB_COLOR_DEST_MASK 0x2326 -#define REG_RB_COLOR_MASK 0x2104 -#define REG_RB_COPY_CONTROL 0x2318 -#define REG_RB_DEPTHCONTROL 0x2200 -#define REG_RB_EDRAM_INFO 0x0F02 -#define REG_RB_MODECONTROL 0x2208 -#define REG_RB_SURFACE_INFO 0x2000 - -#define REG_SCRATCH_ADDR 0x01DD -#define REG_SCRATCH_REG0 0x0578 -#define REG_SCRATCH_REG2 0x057A -#define REG_SCRATCH_UMSK 0x01DC - -#define REG_SQ_CF_BOOLEANS 0x4900 -#define REG_SQ_CF_LOOP 0x4908 -#define REG_SQ_GPR_MANAGEMENT 0x0D00 -#define REG_SQ_INST_STORE_MANAGMENT 0x0D02 -#define REG_SQ_INT_ACK 0x0D36 -#define REG_SQ_INT_CNTL 0x0D34 -#define REG_SQ_INT_STATUS 0x0D35 -#define REG_SQ_PROGRAM_CNTL 0x2180 -#define REG_SQ_PS_PROGRAM 0x21F6 -#define REG_SQ_VS_PROGRAM 0x21F7 -#define REG_SQ_WRAPPING_0 0x2183 -#define REG_SQ_WRAPPING_1 0x2184 - -#define REG_VGT_ENHANCE 0x2294 -#define REG_VGT_INDX_OFFSET 0x2102 -#define REG_VGT_MAX_VTX_INDX 0x2100 -#define REG_VGT_MIN_VTX_INDX 0x2101 - -#define REG_TP0_CHICKEN 0x0E1E -#define REG_TC_CNTL_STATUS 0x0E00 -#define REG_PA_SC_AA_CONFIG 0x2301 -#define REG_VGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 -#define REG_SQ_INTERPOLATOR_CNTL 0x2182 -#define REG_RB_DEPTH_INFO 0x2002 -#define REG_COHER_DEST_BASE_0 0x2006 -#define REG_PA_SC_SCREEN_SCISSOR_BR 0x200F -#define REG_RB_FOG_COLOR 0x2109 -#define REG_RB_STENCILREFMASK_BF 0x210C -#define REG_PA_SC_LINE_STIPPLE 0x2283 -#define REG_SQ_PS_CONST 0x2308 -#define REG_VGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 -#define REG_RB_DEPTH_CLEAR 0x231D -#define REG_RB_SAMPLE_COUNT_CTL 0x2324 -#define REG_SQ_CONSTANT_0 0x4000 -#define REG_SQ_FETCH_0 0x4800 - -#define REG_MH_AXI_ERROR 0xA45 -#define REG_COHER_BASE_PM4 0xA2A -#define REG_COHER_STATUS_PM4 0xA2B -#define REG_COHER_SIZE_PM4 0xA29 - -#endif /* _YAMATO_REG_H */