msm: kgsl: handle larger instruction store for adreno225
This GPU has a larger instruction store, so more memory needs to be reserved for saving shader state when context switching. The initial vertex and pixel partitioning of the instruction store also needs to be different.
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SecureCRT
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@ -137,21 +137,28 @@ static const struct {
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const char *pm4fw;
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const char *pfpfw;
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struct adreno_gpudev *gpudev;
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unsigned int istore_size;
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unsigned int pix_shader_start;
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} adreno_gpulist[] = {
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{ ADRENO_REV_A200, 0, 2, ANY_ID, ANY_ID,
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"yamato_pm4.fw", "yamato_pfp.fw", &adreno_a2xx_gpudev },
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"yamato_pm4.fw", "yamato_pfp.fw", &adreno_a2xx_gpudev,
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512, 384},
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{ ADRENO_REV_A205, 0, 1, 0, ANY_ID,
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"yamato_pm4.fw", "yamato_pfp.fw", &adreno_a2xx_gpudev },
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"yamato_pm4.fw", "yamato_pfp.fw", &adreno_a2xx_gpudev,
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512, 384},
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{ ADRENO_REV_A220, 2, 1, ANY_ID, ANY_ID,
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"leia_pm4_470.fw", "leia_pfp_470.fw", &adreno_a2xx_gpudev },
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"leia_pm4_470.fw", "leia_pfp_470.fw", &adreno_a2xx_gpudev,
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512, 384},
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/*
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* patchlevel 5 (8960v2) needs special pm4 firmware to work around
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* a hardware problem.
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*/
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{ ADRENO_REV_A225, 2, 2, 0, 5,
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"a225p5_pm4.fw", "a225_pfp.fw", &adreno_a2xx_gpudev },
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"a225p5_pm4.fw", "a225_pfp.fw", &adreno_a2xx_gpudev,
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1536, 768 },
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{ ADRENO_REV_A225, 2, 2, ANY_ID, ANY_ID,
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"a225_pm4.fw", "a225_pfp.fw", &adreno_a2xx_gpudev },
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"a225_pm4.fw", "a225_pfp.fw", &adreno_a2xx_gpudev,
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1536, 768 },
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};
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static void adreno_gmeminit(struct adreno_device *adreno_dev)
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@ -424,6 +431,8 @@ adreno_identify_gpu(struct adreno_device *adreno_dev)
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adreno_dev->gpudev = adreno_gpulist[i].gpudev;
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adreno_dev->pfp_fwfile = adreno_gpulist[i].pfpfw;
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adreno_dev->pm4_fwfile = adreno_gpulist[i].pm4fw;
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adreno_dev->istore_size = adreno_gpulist[i].istore_size;
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adreno_dev->pix_shader_start = adreno_gpulist[i].pix_shader_start;
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}
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static int __devinit
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@ -39,6 +39,12 @@
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#define ADRENO_DEFAULT_PWRSCALE_POLICY NULL
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#endif
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/*
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* constants for the size of shader instructions
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*/
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#define ADRENO_ISTORE_BYTES 12
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#define ADRENO_ISTORE_WORDS 3
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enum adreno_gpurev {
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ADRENO_REV_UNKNOWN = 0,
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ADRENO_REV_A200 = 200,
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@ -65,6 +71,8 @@ struct adreno_device {
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unsigned int mharb;
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struct adreno_gpudev *gpudev;
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unsigned int wait_timeout;
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unsigned int istore_size;
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unsigned int pix_shader_start;
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};
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struct adreno_gpudev {
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@ -128,5 +136,28 @@ static inline int adreno_is_a2xx(struct adreno_device *adreno_dev)
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return (adreno_dev->gpurev <= ADRENO_REV_A225);
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}
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/**
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* adreno_encode_istore_size - encode istore size in CP format
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* @adreno_dev - The 3D device.
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*
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* Encode the istore size into the format expected that the
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* CP_SET_SHADER_BASES and CP_ME_INIT commands:
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* bits 31:29 - istore size as encoded by this function
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* bits 27:16 - vertex shader start offset in instructions
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* bits 11:0 - pixel shader start offset in instructions.
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*/
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static inline int adreno_encode_istore_size(struct adreno_device *adreno_dev)
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{
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unsigned int size;
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/* in a225 the CP microcode multiplies the encoded
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* value by 3 while decoding.
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*/
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if (adreno_is_a225(adreno_dev))
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size = adreno_dev->istore_size/3;
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else
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size = adreno_dev->istore_size;
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return (ilog2(size) - 5) << 29;
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}
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#endif /*__ADRENO_H */
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@ -72,10 +72,6 @@
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#define TEX_CONSTANTS (32*6) /* DWORDS */
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#define BOOL_CONSTANTS 8 /* DWORDS */
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#define LOOP_CONSTANTS 56 /* DWORDS */
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#define SHADER_INSTRUCT_LOG2 9U /* 2^n == SHADER_INSTRUCTIONS */
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/* 96-bit instructions */
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#define SHADER_INSTRUCT (1<<SHADER_INSTRUCT_LOG2)
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/* LOAD_CONSTANT_CONTEXT shadow size */
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#define LCC_SHADOW_SIZE 0x2000 /* 8KB */
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@ -88,14 +84,21 @@
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#define CMD_BUFFER_SIZE 0x3000 /* 12KB */
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#endif
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#define TEX_SHADOW_SIZE (TEX_CONSTANTS*4) /* 768 bytes */
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#define SHADER_SHADOW_SIZE (SHADER_INSTRUCT*12) /* 6KB */
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#define REG_OFFSET LCC_SHADOW_SIZE
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#define CMD_OFFSET (REG_OFFSET + REG_SHADOW_SIZE)
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#define TEX_OFFSET (CMD_OFFSET + CMD_BUFFER_SIZE)
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#define SHADER_OFFSET ((TEX_OFFSET + TEX_SHADOW_SIZE + 32) & ~31)
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#define CONTEXT_SIZE (SHADER_OFFSET + 3 * SHADER_SHADOW_SIZE)
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static inline int _shader_shadow_size(struct adreno_device *adreno_dev)
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{
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return adreno_dev->istore_size*ADRENO_ISTORE_BYTES;
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}
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static inline int _context_size(struct adreno_device *adreno_dev)
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{
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return SHADER_OFFSET + 3*_shader_shadow_size(adreno_dev);
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}
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/* A scratchpad used to build commands during context create */
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@ -603,7 +606,8 @@ static unsigned int *build_gmem2sys_cmds(struct adreno_device *adreno_dev,
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*cmds++ = 0x00003F00;
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*cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
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*cmds++ = (0x80000000) | 0x180;
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*cmds++ = adreno_encode_istore_size(adreno_dev)
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| adreno_dev->pix_shader_start;
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/* load the patched vertex shader stream */
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cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN);
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@ -806,7 +810,8 @@ static unsigned int *build_sys2gmem_cmds(struct adreno_device *adreno_dev,
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*cmds++ = 0x00000300; /* 0x100 = Vertex, 0x200 = Pixel */
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*cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
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*cmds++ = (0x80000000) | 0x180;
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*cmds++ = adreno_encode_istore_size(adreno_dev)
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| adreno_dev->pix_shader_start;
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/* Load the patched fragment shader stream */
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cmds =
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@ -1104,8 +1109,10 @@ build_shader_save_restore_cmds(struct adreno_device *adreno_dev,
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/* compute vertex, pixel and shared instruction shadow GPU addresses */
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tmp_ctx.shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET;
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tmp_ctx.shader_pixel = tmp_ctx.shader_vertex + SHADER_SHADOW_SIZE;
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tmp_ctx.shader_shared = tmp_ctx.shader_pixel + SHADER_SHADOW_SIZE;
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tmp_ctx.shader_pixel = tmp_ctx.shader_vertex
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+ _shader_shadow_size(adreno_dev);
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tmp_ctx.shader_shared = tmp_ctx.shader_pixel
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+ _shader_shadow_size(adreno_dev);
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/* restore shader partitioning and instructions */
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@ -1161,8 +1168,8 @@ build_shader_save_restore_cmds(struct adreno_device *adreno_dev,
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*cmd++ = REG_SCRATCH_REG2;
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/* AND off invalid bits. */
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*cmd++ = 0x0FFF0FFF;
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/* OR in instruction memory size */
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*cmd++ = (unsigned int)((SHADER_INSTRUCT_LOG2 - 5U) << 29);
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/* OR in instruction memory size. */
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*cmd++ = adreno_encode_istore_size(adreno_dev);
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/* write the computed value to the SET_SHADER_BASES data field */
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*cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2);
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@ -1305,13 +1312,13 @@ static int a2xx_drawctxt_create(struct adreno_device *adreno_dev,
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*/
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ret = kgsl_allocate(&drawctxt->gpustate,
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drawctxt->pagetable, CONTEXT_SIZE);
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drawctxt->pagetable, _context_size(adreno_dev));
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if (ret)
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return ret;
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kgsl_sharedmem_set(&drawctxt->gpustate, 0, 0,
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CONTEXT_SIZE);
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_context_size(adreno_dev));
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tmp_ctx.cmd = tmp_ctx.start
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= (unsigned int *)((char *)drawctxt->gpustate.hostptr + CMD_OFFSET);
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11
drivers/gpu/msm/adreno_debugfs.c
Normal file → Executable file
11
drivers/gpu/msm/adreno_debugfs.c
Normal file → Executable file
@ -223,21 +223,23 @@ static int kgsl_regread_nolock(struct kgsl_device *device,
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return 0;
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}
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#define KGSL_ISTORE_START 0x5000
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#define KGSL_ISTORE_LENGTH 0x600
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#define ADRENO_ISTORE_START 0x5000
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static ssize_t kgsl_istore_read(
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struct file *file,
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char __user *buff,
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size_t buff_count,
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loff_t *ppos)
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{
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int i, count = KGSL_ISTORE_LENGTH, remaining, pos = 0, tot = 0;
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int i, count, remaining, pos = 0, tot = 0;
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struct kgsl_device *device = file->private_data;
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const int rowc = 8;
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struct adreno_device *adreno_dev;
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if (!ppos || !device)
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return 0;
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adreno_dev = ADRENO_DEVICE(device);
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count = adreno_dev->istore_size * ADRENO_ISTORE_WORDS;
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remaining = count;
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for (i = 0; i < count; i += rowc) {
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unsigned int vals[rowc];
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@ -248,7 +250,8 @@ static ssize_t kgsl_istore_read(
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if (pos >= *ppos) {
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for (j = 0; j < linec; ++j)
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kgsl_regread_nolock(device,
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KGSL_ISTORE_START+i+j, vals+j);
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ADRENO_ISTORE_START + i + j,
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vals + j);
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} else
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memset(vals, 0, sizeof(vals));
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@ -1,4 +1,4 @@
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/* Copyright (c) 2002,2007-2012, Code Aurora Forum. All rights reserved.
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/* Copyright (c) 2002,2007-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -246,6 +246,7 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram)
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union reg_cp_rb_cntl cp_rb_cntl;
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unsigned int *cmds, rb_cntl;
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struct kgsl_device *device = rb->device;
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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uint cmds_gpu;
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if (rb->flags & KGSL_FLAGS_STARTED)
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@ -362,9 +363,10 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram)
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GSL_RB_WRITE(cmds, cmds_gpu,
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SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE));
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/* Vertex and Pixel Shader Start Addresses in instructions
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* (3 DWORDS per instruction) */
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GSL_RB_WRITE(cmds, cmds_gpu, 0x80000180);
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/* Instruction memory size: */
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GSL_RB_WRITE(cmds, cmds_gpu,
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(adreno_encode_istore_size(adreno_dev)
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| adreno_dev->pix_shader_start));
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/* Maximum Contexts */
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GSL_RB_WRITE(cmds, cmds_gpu, 0x00000001);
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/* Write Confirm Interval and The CP will wait the
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