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net: add newest bsm wlan drivers Check for new firmware too!

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This commit is contained in:
Markinus
2010-09-12 13:40:29 +02:00
parent 34974f2ad3
commit 8c7de5cc0e
93 changed files with 53110 additions and 2 deletions
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2
drivers/net/wireless/Kconfig
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@ -488,6 +488,6 @@ source "drivers/net/wireless/rt2x00/Kconfig"
source "drivers/net/wireless/orinoco/Kconfig"
source "drivers/net/wireless/wl12xx/Kconfig"
source "drivers/net/wireless/iwmc3200wifi/Kconfig"
source "drivers/net/wireless/bcm4329_204/Kconfig"
source "drivers/net/wireless/bcm4329_245/Kconfig"
endif # WLAN

2
drivers/net/wireless/Makefile
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@ -63,4 +63,4 @@ obj-$(CONFIG_WL12XX) += wl12xx/
obj-$(CONFIG_IWM) += iwmc3200wifi/
obj-$(CONFIG_BCM4329) += bcm4329_204/
obj-$(CONFIG_BCM4329) += bcm4329_245/

32
drivers/net/wireless/bcm4329_245/Kconfig Normal file
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@ -0,0 +1,32 @@
config BCM4329
tristate "Broadcom 4329 wireless cards support"
depends on WIRELESS_EXT && MMC
---help---
This module adds support for wireless adapters based on
Broadcom 4329 chipset.
This driver uses the kernel's wireless extensions subsystem.
If you choose to build a module, it'll be called dhd. Say M if
unsure.
config BCM4329_SOFTAP
depends on BCM4329
bool "Broadcom 4329 Soft AP function"
---help---
BCM4329 soft AP function
config BCM4329_FW_PATH
depends on BCM4329
string "Firmware path"
default "/system/etc/firmware/fw_bcm4329.bin"
---help---
Path to the firmware file.
config BCM4329_NVRAM_PATH
depends on BCM4329
string "NVRAM path"
default "/proc/calibration"
---help---
Path to the calibration file.

20
drivers/net/wireless/bcm4329_245/Makefile Normal file
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@ -0,0 +1,20 @@
# bcm4329
DHDCFLAGS = -DLINUX -DBCMDRIVER -DBCMDONGLEHOST -DDHDTHREAD -DBCMWPA2 \
-DUNRELEASEDCHIP -Dlinux -DDHD_SDALIGN=64 -DMAX_HDR_READ=64 \
-DDHD_FIRSTREAD=64 -DDHD_GPL -DDHD_SCHED -DBDC -DTOE -DDHD_BCMEVENTS \
-DSHOW_EVENTS -DBCMSDIO -DDHD_GPL -DBCMLXSDMMC -DBCMPLATFORM_BUS \
-Wall -Wstrict-prototypes -Werror -DOOB_INTR_ONLY -DCUSTOMER_HW2 \
-DDHD_USE_STATIC_BUF -DMMC_SDIO_ABORT -DWLAN_PFN -DWLAN_PROTECT \
-DEMBEDDED_PLATFORM -DARP_OFFLOAD_SUPPORT -DPKT_FILTER_SUPPORT \
-DSET_RANDOM_MAC_SOFTAP \
-Idrivers/net/wireless/bcm4329_245 -Idrivers/net/wireless/bcm4329_245/include
DHDOFILES = dhd_linux.o linux_osl.o bcmutils.o dhd_common.o dhd_custom_gpio.o \
wl_iw.o siutils.o sbutils.o aiutils.o hndpmu.o bcmwifi.o dhd_sdio.o \
dhd_linux_sched.o dhd_cdc.o bcmsdh_sdmmc.o bcmsdh.o bcmsdh_linux.o \
bcmsdh_sdmmc_linux.o wl_cfg80211.o
obj-$(CONFIG_BCM4329) += bcm4329.o
bcm4329-objs += $(DHDOFILES)
EXTRA_CFLAGS = $(DHDCFLAGS)
EXTRA_LDFLAGS += --strip-debug

686
drivers/net/wireless/bcm4329_245/aiutils.c Normal file
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@ -0,0 +1,686 @@
/*
* Misc utility routines for accessing chip-specific features
* of the SiliconBackplane-based Broadcom chips.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: aiutils.c,v 1.6.4.7.4.6 2010/04/21 20:43:47 Exp $
*/
#include <typedefs.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <siutils.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include "siutils_priv.h"
STATIC uint32
get_asd(si_t *sih, uint32 *eromptr, uint sp, uint ad, uint st,
uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh);
/* EROM parsing */
static uint32
get_erom_ent(si_t *sih, uint32 *eromptr, uint32 mask, uint32 match)
{
uint32 ent;
uint inv = 0, nom = 0;
while (TRUE) {
ent = R_REG(si_osh(sih), (uint32 *)(uintptr)(*eromptr));
*eromptr += sizeof(uint32);
if (mask == 0)
break;
if ((ent & ER_VALID) == 0) {
inv++;
continue;
}
if (ent == (ER_END | ER_VALID))
break;
if ((ent & mask) == match)
break;
nom++;
}
SI_MSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent));
if (inv + nom)
SI_MSG((" after %d invalid and %d non-matching entries\n", inv, nom));
return ent;
}
STATIC uint32
get_asd(si_t *sih, uint32 *eromptr, uint sp, uint ad, uint st,
uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh)
{
uint32 asd, sz, szd;
asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
if (((asd & ER_TAG1) != ER_ADD) ||
(((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
((asd & AD_ST_MASK) != st)) {
/* This is not what we want, "push" it back */
*eromptr -= sizeof(uint32);
return 0;
}
*addrl = asd & AD_ADDR_MASK;
if (asd & AD_AG32)
*addrh = get_erom_ent(sih, eromptr, 0, 0);
else
*addrh = 0;
*sizeh = 0;
sz = asd & AD_SZ_MASK;
if (sz == AD_SZ_SZD) {
szd = get_erom_ent(sih, eromptr, 0, 0);
*sizel = szd & SD_SZ_MASK;
if (szd & SD_SG32)
*sizeh = get_erom_ent(sih, eromptr, 0, 0);
} else
*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
SI_MSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
return asd;
}
/* parse the enumeration rom to identify all cores */
void
ai_scan(si_t *sih, void *regs, uint devid)
{
si_info_t *sii = SI_INFO(sih);
chipcregs_t *cc = (chipcregs_t *)regs;
uint32 erombase, eromptr, eromlim;
erombase = R_REG(sii->osh, &cc->eromptr);
switch (BUSTYPE(sih->bustype)) {
case SI_BUS:
eromptr = (uintptr)REG_MAP(erombase, SI_CORE_SIZE);
break;
case PCI_BUS:
/* Set wrappers address */
sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
/* Now point the window at the erom */
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
eromptr = (uint32)(uintptr)regs;
break;
case SPI_BUS:
case SDIO_BUS:
eromptr = erombase;
break;
case PCMCIA_BUS:
default:
SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n", sih->bustype));
ASSERT(0);
return;
}
eromlim = eromptr + ER_REMAPCONTROL;
SI_MSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%08x, eromlim = 0x%08x\n",
regs, erombase, eromptr, eromlim));
while (eromptr < eromlim) {
uint32 cia, cib, base, cid, mfg, crev, nmw, nsw, nmp, nsp;
uint32 mpd, asd, addrl, addrh, sizel, sizeh;
uint i, j, idx;
bool br;
br = FALSE;
/* Grok a component */
cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
if (cia == (ER_END | ER_VALID)) {
SI_MSG(("Found END of erom after %d cores\n", sii->numcores));
return;
}
base = eromptr - sizeof(uint32);
cib = get_erom_ent(sih, &eromptr, 0, 0);
if ((cib & ER_TAG) != ER_CI) {
SI_ERROR(("CIA not followed by CIB\n"));
goto error;
}
cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
SI_MSG(("Found component 0x%04x/0x%4x rev %d at erom addr 0x%08x, with nmw = %d, "
"nsw = %d, nmp = %d & nsp = %d\n",
mfg, cid, crev, base, nmw, nsw, nmp, nsp));
if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
continue;
if ((nmw + nsw == 0)) {
/* A component which is not a core */
if (cid == OOB_ROUTER_CORE_ID) {
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
&addrl, &addrh, &sizel, &sizeh);
if (asd != 0) {
sii->common_info->oob_router = addrl;
}
}
continue;
}
idx = sii->numcores;
/* sii->eromptr[idx] = base; */
sii->common_info->cia[idx] = cia;
sii->common_info->cib[idx] = cib;
sii->common_info->coreid[idx] = cid;
for (i = 0; i < nmp; i++) {
mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
if ((mpd & ER_TAG) != ER_MP) {
SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
goto error;
}
SI_MSG((" Master port %d, mp: %d id: %d\n", i,
(mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
(mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
}
/* First Slave Address Descriptor should be port 0:
* the main register space for the core
*/
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
if (asd == 0) {
/* Try again to see if it is a bridge */
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
&sizel, &sizeh);
if (asd != 0)
br = TRUE;
else
if ((addrh != 0) || (sizeh != 0) || (sizel != SI_CORE_SIZE)) {
SI_ERROR(("First Slave ASD for core 0x%04x malformed "
"(0x%08x)\n", cid, asd));
goto error;
}
}
sii->common_info->coresba[idx] = addrl;
sii->common_info->coresba_size[idx] = sizel;
/* Get any more ASDs in port 0 */
j = 1;
do {
asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE))
sii->common_info->coresba2[idx] = addrl;
sii->common_info->coresba2_size[idx] = sizel;
j++;
} while (asd != 0);
/* Go through the ASDs for other slave ports */
for (i = 1; i < nsp; i++) {
j = 0;
do {
asd = get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
} while (asd != 0);
if (j == 0) {
SI_ERROR((" SP %d has no address descriptors\n", i));
goto error;
}
}
/* Now get master wrappers */
for (i = 0; i < nmw; i++) {
asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
&sizel, &sizeh);
if (asd == 0) {
SI_ERROR(("Missing descriptor for MW %d\n", i));
goto error;
}
if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
SI_ERROR(("Master wrapper %d is not 4KB\n", i));
goto error;
}
if (i == 0)
sii->common_info->wrapba[idx] = addrl;
}
/* And finally slave wrappers */
for (i = 0; i < nsw; i++) {
uint fwp = (nsp == 1) ? 0 : 1;
asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
&sizel, &sizeh);
if (asd == 0) {
SI_ERROR(("Missing descriptor for SW %d\n", i));
goto error;
}
if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
goto error;
}
if ((nmw == 0) && (i == 0))
sii->common_info->wrapba[idx] = addrl;
}
/* Don't record bridges */
if (br)
continue;
/* Done with core */
sii->numcores++;
}
SI_ERROR(("Reached end of erom without finding END"));
error:
sii->numcores = 0;
return;
}
/* This function changes the logical "focus" to the indicated core.
* Return the current core's virtual address.
*/
void *
ai_setcoreidx(si_t *sih, uint coreidx)
{
si_info_t *sii = SI_INFO(sih);
uint32 addr = sii->common_info->coresba[coreidx];
uint32 wrap = sii->common_info->wrapba[coreidx];
void *regs;
if (coreidx >= sii->numcores)
return (NULL);
/*
* If the user has provided an interrupt mask enabled function,
* then assert interrupts are disabled before switching the core.
*/
ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
switch (BUSTYPE(sih->bustype)) {
case SI_BUS:
/* map new one */
if (!sii->common_info->regs[coreidx]) {
sii->common_info->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
ASSERT(GOODREGS(sii->common_info->regs[coreidx]));
}
sii->curmap = regs = sii->common_info->regs[coreidx];
if (!sii->common_info->wrappers[coreidx]) {
sii->common_info->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
ASSERT(GOODREGS(sii->common_info->wrappers[coreidx]));
}
sii->curwrap = sii->common_info->wrappers[coreidx];
break;
case SPI_BUS:
case SDIO_BUS:
sii->curmap = regs = (void *)((uintptr)addr);
sii->curwrap = (void *)((uintptr)wrap);
break;
case PCMCIA_BUS:
default:
ASSERT(0);
regs = NULL;
break;
}
sii->curmap = regs;
sii->curidx = coreidx;
return regs;
}
/* Return the number of address spaces in current core */
int
ai_numaddrspaces(si_t *sih)
{
return 2;
}
/* Return the address of the nth address space in the current core */
uint32
ai_addrspace(si_t *sih, uint asidx)
{
si_info_t *sii;
uint cidx;
sii = SI_INFO(sih);
cidx = sii->curidx;
if (asidx == 0)
return sii->common_info->coresba[cidx];
else if (asidx == 1)
return sii->common_info->coresba2[cidx];
else {
SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
__FUNCTION__, asidx));
return 0;
}
}
/* Return the size of the nth address space in the current core */
uint32
ai_addrspacesize(si_t *sih, uint asidx)
{
si_info_t *sii;
uint cidx;
sii = SI_INFO(sih);
cidx = sii->curidx;
if (asidx == 0)
return sii->common_info->coresba_size[cidx];
else if (asidx == 1)
return sii->common_info->coresba2_size[cidx];
else {
SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
__FUNCTION__, asidx));
return 0;
}
}
uint
ai_flag(si_t *sih)
{
si_info_t *sii;
aidmp_t *ai;
sii = SI_INFO(sih);
ai = sii->curwrap;
return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
}
void
ai_setint(si_t *sih, int siflag)
{
}
void
ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val)
{
si_info_t *sii = SI_INFO(sih);
aidmp_t *ai = sii->curwrap;
W_REG(sii->osh, (uint32 *)((uint8 *)ai+offset), val);
return;
}
uint
ai_corevendor(si_t *sih)
{
si_info_t *sii;
uint32 cia;
sii = SI_INFO(sih);
cia = sii->common_info->cia[sii->curidx];
return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
}
uint
ai_corerev(si_t *sih)
{
si_info_t *sii;
uint32 cib;
sii = SI_INFO(sih);
cib = sii->common_info->cib[sii->curidx];
return ((cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
}
bool
ai_iscoreup(si_t *sih)
{
si_info_t *sii;
aidmp_t *ai;
sii = SI_INFO(sih);
ai = sii->curwrap;
return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
}
/*
* Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
* switch back to the original core, and return the new value.
*
* When using the silicon backplane, no fidleing with interrupts or core switches are needed.
*
* Also, when using pci/pcie, we can optimize away the core switching for pci registers
* and (on newer pci cores) chipcommon registers.
*/
uint
ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
uint origidx = 0;
uint32 *r = NULL;
uint w;
uint intr_val = 0;
bool fast = FALSE;
si_info_t *sii;
sii = SI_INFO(sih);
ASSERT(GOODIDX(coreidx));
ASSERT(regoff < SI_CORE_SIZE);
ASSERT((val & ~mask) == 0);
if (coreidx >= SI_MAXCORES)
return 0;
if (BUSTYPE(sih->bustype) == SI_BUS) {
/* If internal bus, we can always get at everything */
fast = TRUE;
/* map if does not exist */
if (!sii->common_info->wrappers[coreidx]) {
sii->common_info->regs[coreidx] =
REG_MAP(sii->common_info->coresba[coreidx], SI_CORE_SIZE);
ASSERT(GOODREGS(sii->common_info->regs[coreidx]));
}
r = (uint32 *)((uchar *)sii->common_info->regs[coreidx] + regoff);
} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
if ((sii->common_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
/* Chipc registers are mapped at 12KB */
fast = TRUE;
r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
} else if (sii->pub.buscoreidx == coreidx) {
/* pci registers are at either in the last 2KB of an 8KB window
* or, in pcie and pci rev 13 at 8KB
*/
fast = TRUE;
if (SI_FAST(sii))
r = (uint32 *)((char *)sii->curmap +
PCI_16KB0_PCIREGS_OFFSET + regoff);
else
r = (uint32 *)((char *)sii->curmap +
((regoff >= SBCONFIGOFF) ?
PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
regoff);
}
}
if (!fast) {
INTR_OFF(sii, intr_val);
/* save current core index */
origidx = si_coreidx(&sii->pub);
/* switch core */
r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
}
ASSERT(r != NULL);
/* mask and set */
if (mask || val) {
w = (R_REG(sii->osh, r) & ~mask) | val;
W_REG(sii->osh, r, w);
}
/* readback */
w = R_REG(sii->osh, r);
if (!fast) {
/* restore core index */
if (origidx != coreidx)
ai_setcoreidx(&sii->pub, origidx);
INTR_RESTORE(sii, intr_val);
}
return (w);
}
void
ai_core_disable(si_t *sih, uint32 bits)
{
si_info_t *sii;
volatile uint32 dummy;
aidmp_t *ai;
sii = SI_INFO(sih);
ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
/* if core is already in reset, just return */
if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
return;
W_REG(sii->osh, &ai->ioctrl, bits);
dummy = R_REG(sii->osh, &ai->ioctrl);
OSL_DELAY(10);
W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
OSL_DELAY(1);
}
/* reset and re-enable a core
* inputs:
* bits - core specific bits that are set during and after reset sequence
* resetbits - core specific bits that are set only during reset sequence
*/
void
ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
{
si_info_t *sii;
aidmp_t *ai;
volatile uint32 dummy;
sii = SI_INFO(sih);
ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
/*
* Must do the disable sequence first to work for arbitrary current core state.
*/
ai_core_disable(sih, (bits | resetbits));
/*
* Now do the initialization sequence.
*/
W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
dummy = R_REG(sii->osh, &ai->ioctrl);
W_REG(sii->osh, &ai->resetctrl, 0);
OSL_DELAY(1);
W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
dummy = R_REG(sii->osh, &ai->ioctrl);
OSL_DELAY(1);
}
void
ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
aidmp_t *ai;
uint32 w;
sii = SI_INFO(sih);
ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
ASSERT((val & ~mask) == 0);
if (mask || val) {
w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
W_REG(sii->osh, &ai->ioctrl, w);
}
}
uint32
ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
aidmp_t *ai;
uint32 w;
sii = SI_INFO(sih);
ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
ASSERT((val & ~mask) == 0);
if (mask || val) {
w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
W_REG(sii->osh, &ai->ioctrl, w);
}
return R_REG(sii->osh, &ai->ioctrl);
}
uint32
ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
aidmp_t *ai;
uint32 w;
sii = SI_INFO(sih);
ASSERT(GOODREGS(sii->curwrap));
ai = sii->curwrap;
ASSERT((val & ~mask) == 0);
ASSERT((mask & ~SISF_CORE_BITS) == 0);
if (mask || val) {
w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
W_REG(sii->osh, &ai->iostatus, w);
}
return R_REG(sii->osh, &ai->iostatus);
}

625
drivers/net/wireless/bcm4329_245/bcmpcispi.c Normal file
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@ -0,0 +1,625 @@
/*
* Broadcom SPI over PCI-SPI Host Controller, low-level hardware driver
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmpcispi.c,v 1.22.2.4.4.5 2008/07/09 21:23:30 Exp $
*/
#include <typedefs.h>
#include <bcmutils.h>
#include <sdio.h> /* SDIO Specs */
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* to get msglevel bit values */
#include <pcicfg.h>
#include <bcmsdspi.h>
#include <bcmspi.h>
#include <bcmpcispi.h> /* BRCM PCI-SPI Host Controller Register definitions */
/* ndis_osl.h needs to do a runtime check of the osh to map
* R_REG/W_REG to bus specific access similar to linux_osl.h.
* Until then...
*/
/* linux */
#define SPIPCI_RREG R_REG
#define SPIPCI_WREG W_REG
#define SPIPCI_ANDREG(osh, r, v) SPIPCI_WREG(osh, (r), (SPIPCI_RREG(osh, r) & (v)))
#define SPIPCI_ORREG(osh, r, v) SPIPCI_WREG(osh, (r), (SPIPCI_RREG(osh, r) | (v)))
int bcmpcispi_dump = 0; /* Set to dump complete trace of all SPI bus transactions */
typedef struct spih_info_ {
uint bar0; /* BAR0 of PCI Card */
uint bar1; /* BAR1 of PCI Card */
osl_t *osh; /* osh handle */
spih_pciregs_t *pciregs; /* PCI Core Registers */
spih_regs_t *regs; /* SPI Controller Registers */
uint8 rev; /* PCI Card Revision ID */
} spih_info_t;
/* Attach to PCI-SPI Host Controller Hardware */
bool
spi_hw_attach(sdioh_info_t *sd)
{
osl_t *osh;
spih_info_t *si;
sd_trace(("%s: enter\n", __FUNCTION__));
osh = sd->osh;
if ((si = (spih_info_t *)MALLOC(osh, sizeof(spih_info_t))) == NULL) {
sd_err(("%s: out of memory, malloced %d bytes\n", __FUNCTION__, MALLOCED(osh)));
return FALSE;
}
bzero(si, sizeof(spih_info_t));
sd->controller = si;
si->osh = sd->osh;
si->rev = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_REV, 4) & 0xFF;
if (si->rev < 3) {
sd_err(("Host controller %d not supported, please upgrade to rev >= 3\n", si->rev));
MFREE(osh, si, sizeof(spih_info_t));
return (FALSE);
}
sd_err(("Attaching to Generic PCI SPI Host Controller Rev %d\n", si->rev));
/* FPGA Revision < 3 not supported by driver anymore. */
ASSERT(si->rev >= 3);
si->bar0 = sd->bar0;
/* Rev < 10 PciSpiHost has 2 BARs:
* BAR0 = PCI Core Registers
* BAR1 = PciSpiHost Registers (all other cores on backplane)
*
* Rev 10 and up use a different PCI core which only has a single
* BAR0 which contains the PciSpiHost Registers.
*/
if (si->rev < 10) {
si->pciregs = (spih_pciregs_t *)spi_reg_map(osh,
(uintptr)si->bar0,
sizeof(spih_pciregs_t));
sd_err(("Mapped PCI Core regs to BAR0 at %p\n", si->pciregs));
si->bar1 = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR1, 4);
si->regs = (spih_regs_t *)spi_reg_map(osh,
(uintptr)si->bar1,
sizeof(spih_regs_t));
sd_err(("Mapped SPI Controller regs to BAR1 at %p\n", si->regs));
} else {
si->regs = (spih_regs_t *)spi_reg_map(osh,
(uintptr)si->bar0,
sizeof(spih_regs_t));
sd_err(("Mapped SPI Controller regs to BAR0 at %p\n", si->regs));
si->pciregs = NULL;
}
/* Enable SPI Controller, 16.67MHz SPI Clock */
SPIPCI_WREG(osh, &si->regs->spih_ctrl, 0x000000d1);
/* Set extended feature register to defaults */
SPIPCI_WREG(osh, &si->regs->spih_ext, 0x00000000);
/* Set GPIO CS# High (de-asserted) */
SPIPCI_WREG(osh, &si->regs->spih_gpio_data, SPIH_CS);
/* set GPIO[0] to output for CS# */
/* set GPIO[1] to output for power control */
/* set GPIO[2] to input for card detect */
SPIPCI_WREG(osh, &si->regs->spih_gpio_ctrl, (SPIH_CS | SPIH_SLOT_POWER));
/* Clear out the Read FIFO in case there is any stuff left in there from a previous run. */
while ((SPIPCI_RREG(osh, &si->regs->spih_stat) & SPIH_RFEMPTY) == 0) {
SPIPCI_RREG(osh, &si->regs->spih_data);
}
/* Wait for power to stabilize to the SDIO Card (100msec was insufficient) */
OSL_DELAY(250000);
/* Check card detect on FPGA Revision >= 4 */
if (si->rev >= 4) {
if (SPIPCI_RREG(osh, &si->regs->spih_gpio_data) & SPIH_CARD_DETECT) {
sd_err(("%s: no card detected in SD slot\n", __FUNCTION__));
spi_reg_unmap(osh, (uintptr)si->regs, sizeof(spih_regs_t));
if (si->pciregs) {
spi_reg_unmap(osh, (uintptr)si->pciregs, sizeof(spih_pciregs_t));
}
MFREE(osh, si, sizeof(spih_info_t));
return FALSE;
}
}
/* Interrupts are level sensitive */
SPIPCI_WREG(osh, &si->regs->spih_int_edge, 0x80000000);
/* Interrupts are active low. */
SPIPCI_WREG(osh, &si->regs->spih_int_pol, 0x40000004);
/* Enable interrupts through PCI Core. */
if (si->pciregs) {
SPIPCI_WREG(osh, &si->pciregs->ICR, PCI_INT_PROP_EN);
}
sd_trace(("%s: exit\n", __FUNCTION__));
return TRUE;
}
/* Detach and return PCI-SPI Hardware to unconfigured state */
bool
spi_hw_detach(sdioh_info_t *sd)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
spih_pciregs_t *pciregs = si->pciregs;
sd_trace(("%s: enter\n", __FUNCTION__));
SPIPCI_WREG(osh, &regs->spih_ctrl, 0x00000010);
SPIPCI_WREG(osh, &regs->spih_gpio_ctrl, 0x00000000); /* Disable GPIO for CS# */
SPIPCI_WREG(osh, &regs->spih_int_mask, 0x00000000); /* Clear Intmask */
SPIPCI_WREG(osh, &regs->spih_hex_disp, 0x0000DEAF);
SPIPCI_WREG(osh, &regs->spih_int_edge, 0x00000000);
SPIPCI_WREG(osh, &regs->spih_int_pol, 0x00000000);
SPIPCI_WREG(osh, &regs->spih_hex_disp, 0x0000DEAD);
/* Disable interrupts through PCI Core. */
if (si->pciregs) {
SPIPCI_WREG(osh, &pciregs->ICR, 0x00000000);
spi_reg_unmap(osh, (uintptr)pciregs, sizeof(spih_pciregs_t));
}
spi_reg_unmap(osh, (uintptr)regs, sizeof(spih_regs_t));
MFREE(osh, si, sizeof(spih_info_t));
sd->controller = NULL;
sd_trace(("%s: exit\n", __FUNCTION__));
return TRUE;
}
/* Switch between internal (PCI) and external clock oscillator */
static bool
sdspi_switch_clock(sdioh_info_t *sd, bool ext_clk)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
/* Switch to desired clock, and reset the PLL. */
SPIPCI_WREG(osh, &regs->spih_pll_ctrl, ext_clk ? SPIH_EXT_CLK : 0);
SPINWAIT(((SPIPCI_RREG(osh, &regs->spih_pll_status) & SPIH_PLL_LOCKED)
!= SPIH_PLL_LOCKED), 1000);
if ((SPIPCI_RREG(osh, &regs->spih_pll_status) & SPIH_PLL_LOCKED) != SPIH_PLL_LOCKED) {
sd_err(("%s: timeout waiting for PLL to lock\n", __FUNCTION__));
return (FALSE);
}
return (TRUE);
}
/* Configure PCI-SPI Host Controller's SPI Clock rate as a divisor into the
* base clock rate. The base clock is either the PCI Clock (33MHz) or the
* external clock oscillator at U17 on the PciSpiHost.
*/
bool
spi_start_clock(sdioh_info_t *sd, uint16 div)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
uint32 t, espr, disp;
uint32 disp_xtal_freq;
bool ext_clock = FALSE;
char disp_string[5];
if (div > 2048) {
sd_err(("%s: divisor %d too large; using max of 2048\n", __FUNCTION__, div));
div = 2048;
} else if (div & (div - 1)) { /* Not a power of 2? */
/* Round up to a power of 2 */
while ((div + 1) & div)
div |= div >> 1;
div++;
}
/* For FPGA Rev >= 5, the use of an external clock oscillator is supported.
* If the oscillator is populated, use it to provide the SPI base clock,
* otherwise, default to the PCI clock as the SPI base clock.
*/
if (si->rev >= 5) {
uint32 clk_tick;
/* Enable the External Clock Oscillator as PLL clock source. */
if (!sdspi_switch_clock(sd, TRUE)) {
sd_err(("%s: error switching to external clock\n", __FUNCTION__));
}
/* Check to make sure the external clock is running. If not, then it
* is not populated on the card, so we will default to the PCI clock.
*/
clk_tick = SPIPCI_RREG(osh, &regs->spih_clk_count);
if (clk_tick == SPIPCI_RREG(osh, &regs->spih_clk_count)) {
/* Switch back to the PCI clock as the clock source. */
if (!sdspi_switch_clock(sd, FALSE)) {
sd_err(("%s: error switching to external clock\n", __FUNCTION__));
}
} else {
ext_clock = TRUE;
}
}
/* Hack to allow hot-swapping oscillators:
* 1. Force PCI clock as clock source, using sd_divisor of 0.
* 2. Swap oscillator
* 3. Set desired sd_divisor (will switch to external oscillator as clock source.
*/
if (div == 0) {
ext_clock = FALSE;
div = 2;
/* Select PCI clock as the clock source. */
if (!sdspi_switch_clock(sd, FALSE)) {
sd_err(("%s: error switching to external clock\n", __FUNCTION__));
}
sd_err(("%s: Ok to hot-swap oscillators.\n", __FUNCTION__));
}
/* If using the external oscillator, read the clock frequency from the controller
* The value read is in units of 10000Hz, and it's not a nice round number because
* it is calculated by the FPGA. So to make up for that, we round it off.
*/
if (ext_clock == TRUE) {
uint32 xtal_freq;
OSL_DELAY(1000);
xtal_freq = SPIPCI_RREG(osh, &regs->spih_xtal_freq) * 10000;
sd_info(("%s: Oscillator is %dHz\n", __FUNCTION__, xtal_freq));
disp_xtal_freq = xtal_freq / 10000;
/* Round it off to a nice number. */
if ((disp_xtal_freq % 100) > 50) {
disp_xtal_freq += 100;
}
disp_xtal_freq = (disp_xtal_freq / 100) * 100;
} else {
sd_err(("%s: no external oscillator installed, using PCI clock.\n", __FUNCTION__));
disp_xtal_freq = 3333;
}
/* Convert the SPI Clock frequency to BCD format. */
sprintf(disp_string, "%04d", disp_xtal_freq / div);
disp = (disp_string[0] - '0') << 12;
disp |= (disp_string[1] - '0') << 8;
disp |= (disp_string[2] - '0') << 4;
disp |= (disp_string[3] - '0');
/* Select the correct ESPR register value based on the divisor. */
switch (div) {
case 1: espr = 0x0; break;
case 2: espr = 0x1; break;
case 4: espr = 0x2; break;
case 8: espr = 0x5; break;
case 16: espr = 0x3; break;
case 32: espr = 0x4; break;
case 64: espr = 0x6; break;
case 128: espr = 0x7; break;
case 256: espr = 0x8; break;
case 512: espr = 0x9; break;
case 1024: espr = 0xa; break;
case 2048: espr = 0xb; break;
default: espr = 0x0; ASSERT(0); break;
}
t = SPIPCI_RREG(osh, &regs->spih_ctrl);
t &= ~3;
t |= espr & 3;
SPIPCI_WREG(osh, &regs->spih_ctrl, t);
t = SPIPCI_RREG(osh, &regs->spih_ext);
t &= ~3;
t |= (espr >> 2) & 3;
SPIPCI_WREG(osh, &regs->spih_ext, t);
SPIPCI_WREG(osh, &regs->spih_hex_disp, disp);
/* For Rev 8, writing to the PLL_CTRL register resets
* the PLL, and it can re-acquire in 200uS. For
* Rev 7 and older, we use a software delay to allow
* the PLL to re-acquire, which takes more than 2mS.
*/
if (si->rev < 8) {
/* Wait for clock to settle. */
OSL_DELAY(5000);
}
sd_info(("%s: SPI_CTRL=0x%08x SPI_EXT=0x%08x\n",
__FUNCTION__,
SPIPCI_RREG(osh, &regs->spih_ctrl),
SPIPCI_RREG(osh, &regs->spih_ext)));
return TRUE;
}
/* Configure PCI-SPI Host Controller High-Speed Clocking mode setting */
bool
spi_controller_highspeed_mode(sdioh_info_t *sd, bool hsmode)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
if (si->rev >= 10) {
if (hsmode) {
SPIPCI_ORREG(osh, &regs->spih_ext, 0x10);
} else {
SPIPCI_ANDREG(osh, &regs->spih_ext, ~0x10);
}
}
return TRUE;
}
/* Disable device interrupt */
void
spi_devintr_off(sdioh_info_t *sd)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints));
if (sd->use_client_ints) {
sd->intmask &= ~SPIH_DEV_INTR;
SPIPCI_WREG(osh, &regs->spih_int_mask, sd->intmask); /* Clear Intmask */
}
}
/* Enable device interrupt */
void
spi_devintr_on(sdioh_info_t *sd)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
ASSERT(sd->lockcount == 0);
sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints));
if (sd->use_client_ints) {
if (SPIPCI_RREG(osh, &regs->spih_ctrl) & 0x02) {
/* Ack in case one was pending but is no longer... */
SPIPCI_WREG(osh, &regs->spih_int_status, SPIH_DEV_INTR);
}
sd->intmask |= SPIH_DEV_INTR;
/* Set device intr in Intmask */
SPIPCI_WREG(osh, &regs->spih_int_mask, sd->intmask);
}
}
/* Check to see if an interrupt belongs to the PCI-SPI Host or a SPI Device */
bool
spi_check_client_intr(sdioh_info_t *sd, int *is_dev_intr)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
bool ours = FALSE;
uint32 raw_int, cur_int;
ASSERT(sd);
if (is_dev_intr)
*is_dev_intr = FALSE;
raw_int = SPIPCI_RREG(osh, &regs->spih_int_status);
cur_int = raw_int & sd->intmask;
if (cur_int & SPIH_DEV_INTR) {
if (sd->client_intr_enabled && sd->use_client_ints) {
sd->intrcount++;
ASSERT(sd->intr_handler);
ASSERT(sd->intr_handler_arg);
(sd->intr_handler)(sd->intr_handler_arg);
if (is_dev_intr)
*is_dev_intr = TRUE;
} else {
sd_trace(("%s: Not ready for intr: enabled %d, handler 0x%p\n",
__FUNCTION__, sd->client_intr_enabled, sd->intr_handler));
}
SPIPCI_WREG(osh, &regs->spih_int_status, SPIH_DEV_INTR);
SPIPCI_RREG(osh, &regs->spih_int_status);
ours = TRUE;
} else if (cur_int & SPIH_CTLR_INTR) {
/* Interrupt is from SPI FIFO... just clear and ack it... */
sd_trace(("%s: SPI CTLR interrupt: raw_int 0x%08x cur_int 0x%08x\n",
__FUNCTION__, raw_int, cur_int));
/* Clear the interrupt in the SPI_STAT register */
SPIPCI_WREG(osh, &regs->spih_stat, 0x00000080);
/* Ack the interrupt in the interrupt controller */
SPIPCI_WREG(osh, &regs->spih_int_status, SPIH_CTLR_INTR);
SPIPCI_RREG(osh, &regs->spih_int_status);
ours = TRUE;
} else if (cur_int & SPIH_WFIFO_INTR) {
sd_trace(("%s: SPI WR FIFO Empty interrupt: raw_int 0x%08x cur_int 0x%08x\n",
__FUNCTION__, raw_int, cur_int));
/* Disable the FIFO Empty Interrupt */
sd->intmask &= ~SPIH_WFIFO_INTR;
SPIPCI_WREG(osh, &regs->spih_int_mask, sd->intmask);
sd->local_intrcount++;
sd->got_hcint = TRUE;
ours = TRUE;
} else {
/* Not an error: can share interrupts... */
sd_trace(("%s: Not my interrupt: raw_int 0x%08x cur_int 0x%08x\n",
__FUNCTION__, raw_int, cur_int));
ours = FALSE;
}
return ours;
}
static void
hexdump(char *pfx, unsigned char *msg, int msglen)
{
int i, col;
char buf[80];
ASSERT(strlen(pfx) + 49 <= sizeof(buf));
col = 0;
for (i = 0; i < msglen; i++, col++) {
if (col % 16 == 0)
strcpy(buf, pfx);
sprintf(buf + strlen(buf), "%02x", msg[i]);
if ((col + 1) % 16 == 0)
printf("%s\n", buf);
else
sprintf(buf + strlen(buf), " ");
}
if (col % 16 != 0)
printf("%s\n", buf);
}
/* Send/Receive an SPI Packet */
void
spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
uint32 count;
uint32 spi_data_out;
uint32 spi_data_in;
bool yield;
sd_trace(("%s: enter\n", __FUNCTION__));
if (bcmpcispi_dump) {
printf("SENDRECV(len=%d)\n", msglen);
hexdump(" OUT: ", msg_out, msglen);
}
#ifdef BCMSDYIELD
/* Only yield the CPU and wait for interrupt on Rev 8 and newer FPGA images. */
yield = ((msglen > 500) && (si->rev >= 8));
#else
yield = FALSE;
#endif /* BCMSDYIELD */
ASSERT(msglen % 4 == 0);
SPIPCI_ANDREG(osh, &regs->spih_gpio_data, ~SPIH_CS); /* Set GPIO CS# Low (asserted) */
for (count = 0; count < (uint32)msglen/4; count++) {
spi_data_out = ((uint32)((uint32 *)msg_out)[count]);
SPIPCI_WREG(osh, &regs->spih_data, spi_data_out);
}
#ifdef BCMSDYIELD
if (yield) {
/* Ack the interrupt in the interrupt controller */
SPIPCI_WREG(osh, &regs->spih_int_status, SPIH_WFIFO_INTR);
SPIPCI_RREG(osh, &regs->spih_int_status);
/* Enable the FIFO Empty Interrupt */
sd->intmask |= SPIH_WFIFO_INTR;
sd->got_hcint = FALSE;
SPIPCI_WREG(osh, &regs->spih_int_mask, sd->intmask);
}
#endif /* BCMSDYIELD */
/* Wait for write fifo to empty... */
SPIPCI_ANDREG(osh, &regs->spih_gpio_data, ~0x00000020); /* Set GPIO 5 Low */
if (yield) {
ASSERT((SPIPCI_RREG(sd->osh, &regs->spih_stat) & SPIH_WFEMPTY) == 0);
}
spi_waitbits(sd, yield);
SPIPCI_ORREG(osh, &regs->spih_gpio_data, 0x00000020); /* Set GPIO 5 High (de-asserted) */
for (count = 0; count < (uint32)msglen/4; count++) {
spi_data_in = SPIPCI_RREG(osh, &regs->spih_data);
((uint32 *)msg_in)[count] = spi_data_in;
}
/* Set GPIO CS# High (de-asserted) */
SPIPCI_ORREG(osh, &regs->spih_gpio_data, SPIH_CS);
if (bcmpcispi_dump) {
hexdump(" IN : ", msg_in, msglen);
}
}
void
spi_spinbits(sdioh_info_t *sd)
{
spih_info_t *si = (spih_info_t *)sd->controller;
osl_t *osh = si->osh;
spih_regs_t *regs = si->regs;
uint spin_count; /* Spin loop bound check */
spin_count = 0;
while ((SPIPCI_RREG(sd->osh, &regs->spih_stat) & SPIH_WFEMPTY) == 0) {
if (spin_count > SPI_SPIN_BOUND) {
ASSERT(FALSE); /* Spin bound exceeded */
}
spin_count++;
}
spin_count = 0;
/* Wait for SPI Transfer state machine to return to IDLE state.
* The state bits are only implemented in Rev >= 5 FPGA. These
* bits are hardwired to 00 for Rev < 5, so this check doesn't cause
* any problems.
*/
while ((SPIPCI_RREG(osh, &regs->spih_stat) & SPIH_STATE_MASK) != 0) {
if (spin_count > SPI_SPIN_BOUND) {
ASSERT(FALSE);
}
spin_count++;
}
}

652
drivers/net/wireless/bcm4329_245/bcmsdh.c Normal file
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@ -0,0 +1,652 @@
/*
* BCMSDH interface glue
* implement bcmsdh API for SDIOH driver
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdh.c,v 1.35.2.1.4.8.6.13 2010/04/06 03:26:57 Exp $
*/
/* ****************** BCMSDH Interface Functions *************************** */
#include <typedefs.h>
#include <bcmdevs.h>
#include <bcmendian.h>
#include <bcmutils.h>
#include <hndsoc.h>
#include <siutils.h>
#include <osl.h>
#include <bcmsdh.h> /* BRCM API for SDIO clients (such as wl, dhd) */
#include <bcmsdbus.h> /* common SDIO/controller interface */
#include <sbsdio.h> /* BRCM sdio device core */
#include <sdio.h> /* sdio spec */
#define SDIOH_API_ACCESS_RETRY_LIMIT 2
const uint bcmsdh_msglevel = BCMSDH_ERROR_VAL;
struct bcmsdh_info
{
bool init_success; /* underlying driver successfully attached */
void *sdioh; /* handler for sdioh */
uint32 vendevid; /* Target Vendor and Device ID on SD bus */
osl_t *osh;
bool regfail; /* Save status of last reg_read/reg_write call */
uint32 sbwad; /* Save backplane window address */
};
/* local copy of bcm sd handler */
bcmsdh_info_t * l_bcmsdh = NULL;
#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
extern int
sdioh_enable_hw_oob_intr(void *sdioh, bool enable);
void
bcmsdh_enable_hw_oob_intr(bcmsdh_info_t *sdh, bool enable)
{
sdioh_enable_hw_oob_intr(sdh->sdioh, enable);
}
#endif
bcmsdh_info_t *
bcmsdh_attach(osl_t *osh, void *cfghdl, void **regsva, uint irq)
{
bcmsdh_info_t *bcmsdh;
if ((bcmsdh = (bcmsdh_info_t *)MALLOC(osh, sizeof(bcmsdh_info_t))) == NULL) {
BCMSDH_ERROR(("bcmsdh_attach: out of memory, malloced %d bytes\n", MALLOCED(osh)));
return NULL;
}
bzero((char *)bcmsdh, sizeof(bcmsdh_info_t));
/* save the handler locally */
l_bcmsdh = bcmsdh;
if (!(bcmsdh->sdioh = sdioh_attach(osh, cfghdl, irq))) {
bcmsdh_detach(osh, bcmsdh);
return NULL;
}
bcmsdh->osh = osh;
bcmsdh->init_success = TRUE;
*regsva = (uint32 *)SI_ENUM_BASE;
/* Report the BAR, to fix if needed */
bcmsdh->sbwad = SI_ENUM_BASE;
return bcmsdh;
}
int
bcmsdh_detach(osl_t *osh, void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
if (bcmsdh != NULL) {
if (bcmsdh->sdioh) {
sdioh_detach(osh, bcmsdh->sdioh);
bcmsdh->sdioh = NULL;
}
MFREE(osh, bcmsdh, sizeof(bcmsdh_info_t));
}
l_bcmsdh = NULL;
return 0;
}
int
bcmsdh_iovar_op(void *sdh, const char *name,
void *params, int plen, void *arg, int len, bool set)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
return sdioh_iovar_op(bcmsdh->sdioh, name, params, plen, arg, len, set);
}
bool
bcmsdh_intr_query(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
bool on;
ASSERT(bcmsdh);
status = sdioh_interrupt_query(bcmsdh->sdioh, &on);
if (SDIOH_API_SUCCESS(status))
return FALSE;
else
return on;
}
int
bcmsdh_intr_enable(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
ASSERT(bcmsdh);
status = sdioh_interrupt_set(bcmsdh->sdioh, TRUE);
return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
}
int
bcmsdh_intr_disable(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
ASSERT(bcmsdh);
status = sdioh_interrupt_set(bcmsdh->sdioh, FALSE);
return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
}
int
bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
ASSERT(bcmsdh);
status = sdioh_interrupt_register(bcmsdh->sdioh, fn, argh);
return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
}
int
bcmsdh_intr_dereg(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
ASSERT(bcmsdh);
status = sdioh_interrupt_deregister(bcmsdh->sdioh);
return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
}
#if defined(DHD_DEBUG)
bool
bcmsdh_intr_pending(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
ASSERT(sdh);
return sdioh_interrupt_pending(bcmsdh->sdioh);
}
#endif
int
bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
{
ASSERT(sdh);
/* don't support yet */
return BCME_UNSUPPORTED;
}
uint8
bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
int32 retry = 0;
#endif
uint8 data = 0;
if (!bcmsdh)
bcmsdh = l_bcmsdh;
ASSERT(bcmsdh->init_success);
#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
do {
if (retry) /* wait for 1 ms till bus get settled down */
OSL_DELAY(1000);
#endif
status = sdioh_cfg_read(bcmsdh->sdioh, fnc_num, addr, (uint8 *)&data);
#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
} while (!SDIOH_API_SUCCESS(status) && (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
#endif
if (err)
*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint8data = 0x%x\n", __FUNCTION__,
fnc_num, addr, data));
return data;
}
void
bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, uint8 data, int *err)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
int32 retry = 0;
#endif
if (!bcmsdh)
bcmsdh = l_bcmsdh;
ASSERT(bcmsdh->init_success);
#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
do {
if (retry) /* wait for 1 ms till bus get settled down */
OSL_DELAY(1000);
#endif
status = sdioh_cfg_write(bcmsdh->sdioh, fnc_num, addr, (uint8 *)&data);
#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
} while (!SDIOH_API_SUCCESS(status) && (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
#endif
if (err)
*err = SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR;
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint8data = 0x%x\n", __FUNCTION__,
fnc_num, addr, data));
}
uint32
bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
uint32 data = 0;
if (!bcmsdh)
bcmsdh = l_bcmsdh;
ASSERT(bcmsdh->init_success);
status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_READ, fnc_num,
addr, &data, 4);
if (err)
*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", __FUNCTION__,
fnc_num, addr, data));
return data;
}
void
bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
if (!bcmsdh)
bcmsdh = l_bcmsdh;
ASSERT(bcmsdh->init_success);
status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_WRITE, fnc_num,
addr, &data, 4);
if (err)
*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", __FUNCTION__, fnc_num,
addr, data));
}
int
bcmsdh_cis_read(void *sdh, uint func, uint8 *cis, uint length)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
uint8 *tmp_buf, *tmp_ptr;
uint8 *ptr;
bool ascii = func & ~0xf;
func &= 0x7;
if (!bcmsdh)
bcmsdh = l_bcmsdh;
ASSERT(bcmsdh->init_success);
ASSERT(cis);
ASSERT(length <= SBSDIO_CIS_SIZE_LIMIT);
status = sdioh_cis_read(bcmsdh->sdioh, func, cis, length);
if (ascii) {
/* Move binary bits to tmp and format them into the provided buffer. */
if ((tmp_buf = (uint8 *)MALLOC(bcmsdh->osh, length)) == NULL) {
BCMSDH_ERROR(("%s: out of memory\n", __FUNCTION__));
return BCME_NOMEM;
}
bcopy(cis, tmp_buf, length);
for (tmp_ptr = tmp_buf, ptr = cis; ptr < (cis + length - 4); tmp_ptr++) {
ptr += sprintf((char*)ptr, "%.2x ", *tmp_ptr & 0xff);
if ((((tmp_ptr - tmp_buf) + 1) & 0xf) == 0)
ptr += sprintf((char *)ptr, "\n");
}
MFREE(bcmsdh->osh, tmp_buf, length);
}
return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
}
static int
bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address)
{
int err = 0;
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
(address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
if (!err)
bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
(address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
if (!err)
bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
(address >> 24) & SBSDIO_SBADDRHIGH_MASK, &err);
return err;
}
uint32
bcmsdh_reg_read(void *sdh, uint32 addr, uint size)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
uint32 word = 0;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, ", __FUNCTION__, addr));
if (!bcmsdh)
bcmsdh = l_bcmsdh;
ASSERT(bcmsdh->init_success);
if (bar0 != bcmsdh->sbwad) {
if (bcmsdhsdio_set_sbaddr_window(bcmsdh, bar0))
return 0xFFFFFFFF;
bcmsdh->sbwad = bar0;
}
addr &= SBSDIO_SB_OFT_ADDR_MASK;
if (size == 4)
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL,
SDIOH_READ, SDIO_FUNC_1, addr, &word, size);
bcmsdh->regfail = !(SDIOH_API_SUCCESS(status));
BCMSDH_INFO(("uint32data = 0x%x\n", word));
/* if ok, return appropriately masked word */
if (SDIOH_API_SUCCESS(status)) {
switch (size) {
case sizeof(uint8):
return (word & 0xff);
case sizeof(uint16):
return (word & 0xffff);
case sizeof(uint32):
return word;
default:
bcmsdh->regfail = TRUE;
}
}
/* otherwise, bad sdio access or invalid size */
BCMSDH_ERROR(("%s: error reading addr 0x%04x size %d\n", __FUNCTION__, addr, size));
return 0xFFFFFFFF;
}
uint32
bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
int err = 0;
BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, uint%ddata = 0x%x\n",
__FUNCTION__, addr, size*8, data));
if (!bcmsdh)
bcmsdh = l_bcmsdh;
ASSERT(bcmsdh->init_success);
if (bar0 != bcmsdh->sbwad) {
if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, bar0)))
return err;
bcmsdh->sbwad = bar0;
}
addr &= SBSDIO_SB_OFT_ADDR_MASK;
if (size == 4)
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_WRITE, SDIO_FUNC_1,
addr, &data, size);
bcmsdh->regfail = !(SDIOH_API_SUCCESS(status));
if (SDIOH_API_SUCCESS(status))
return 0;
BCMSDH_ERROR(("%s: error writing 0x%08x to addr 0x%04x size %d\n",
__FUNCTION__, data, addr, size));
return 0xFFFFFFFF;
}
bool
bcmsdh_regfail(void *sdh)
{
return ((bcmsdh_info_t *)sdh)->regfail;
}
int
bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
uint incr_fix;
uint width;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
int err = 0;
ASSERT(bcmsdh);
ASSERT(bcmsdh->init_success);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, size = %d\n",
__FUNCTION__, fn, addr, nbytes));
/* Async not implemented yet */
ASSERT(!(flags & SDIO_REQ_ASYNC));
if (flags & SDIO_REQ_ASYNC)
return BCME_UNSUPPORTED;
if (bar0 != bcmsdh->sbwad) {
if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, bar0)))
return err;
bcmsdh->sbwad = bar0;
}
addr &= SBSDIO_SB_OFT_ADDR_MASK;
incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
if (width == 4)
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, incr_fix,
SDIOH_READ, fn, addr, width, nbytes, buf, pkt);
return (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
}
int
bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
uint incr_fix;
uint width;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
int err = 0;
ASSERT(bcmsdh);
ASSERT(bcmsdh->init_success);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, size = %d\n",
__FUNCTION__, fn, addr, nbytes));
/* Async not implemented yet */
ASSERT(!(flags & SDIO_REQ_ASYNC));
if (flags & SDIO_REQ_ASYNC)
return BCME_UNSUPPORTED;
if (bar0 != bcmsdh->sbwad) {
if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, bar0)))
return err;
bcmsdh->sbwad = bar0;
}
addr &= SBSDIO_SB_OFT_ADDR_MASK;
incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
if (width == 4)
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, incr_fix,
SDIOH_WRITE, fn, addr, width, nbytes, buf, pkt);
return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
}
int
bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
SDIOH_API_RC status;
ASSERT(bcmsdh);
ASSERT(bcmsdh->init_success);
ASSERT((addr & SBSDIO_SBWINDOW_MASK) == 0);
addr &= SBSDIO_SB_OFT_ADDR_MASK;
addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, SDIOH_DATA_INC,
(rw ? SDIOH_WRITE : SDIOH_READ), SDIO_FUNC_1,
addr, 4, nbytes, buf, NULL);
return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
}
int
bcmsdh_abort(void *sdh, uint fn)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
return sdioh_abort(bcmsdh->sdioh, fn);
}
int
bcmsdh_start(void *sdh, int stage)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
return sdioh_start(bcmsdh->sdioh, stage);
}
int
bcmsdh_stop(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
return sdioh_stop(bcmsdh->sdioh);
}
int
bcmsdh_query_device(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
bcmsdh->vendevid = (VENDOR_BROADCOM << 16) | 0;
return (bcmsdh->vendevid);
}
uint
bcmsdh_query_iofnum(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
if (!bcmsdh)
bcmsdh = l_bcmsdh;
return (sdioh_query_iofnum(bcmsdh->sdioh));
}
int
bcmsdh_reset(bcmsdh_info_t *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
return sdioh_sdio_reset(bcmsdh->sdioh);
}
void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh)
{
ASSERT(sdh);
return sdh->sdioh;
}
/* Function to pass device-status bits to DHD. */
uint32
bcmsdh_get_dstatus(void *sdh)
{
return 0;
}
uint32
bcmsdh_cur_sbwad(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
if (!bcmsdh)
bcmsdh = l_bcmsdh;
return (bcmsdh->sbwad);
}
void
bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev)
{
return;
}

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drivers/net/wireless/bcm4329_245/bcmsdh_linux.c Normal file
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@ -0,0 +1,691 @@
/*
* SDIO access interface for drivers - linux specific (pci only)
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdh_linux.c,v 1.42.10.10.2.12 2010/03/10 03:09:48 Exp $
*/
/**
* @file bcmsdh_linux.c
*/
#define __UNDEF_NO_VERSION__
#include <typedefs.h>
#include <linuxver.h>
#include <linux/pci.h>
#include <linux/completion.h>
#include <osl.h>
#include <pcicfg.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#if defined(OOB_INTR_ONLY)
#include <linux/irq.h>
extern void dhdsdio_isr(void * args);
#include <bcmutils.h>
#include <dngl_stats.h>
#include <dhd.h>
#endif /* defined(OOB_INTR_ONLY) */
#if defined(CONFIG_MACH_SANDGATE2G) || defined(CONFIG_MACH_LOGICPD_PXA270)
#if !defined(BCMPLATFORM_BUS)
#define BCMPLATFORM_BUS
#endif /* !defined(BCMPLATFORM_BUS) */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
#include <linux/platform_device.h>
#endif /* KERNEL_VERSION(2, 6, 19) */
#endif /* CONFIG_MACH_SANDGATE2G || CONFIG_MACH_LOGICPD_PXA270 */
/**
* SDIO Host Controller info
*/
typedef struct bcmsdh_hc bcmsdh_hc_t;
struct bcmsdh_hc {
bcmsdh_hc_t *next;
#ifdef BCMPLATFORM_BUS
struct device *dev; /* platform device handle */
#else
struct pci_dev *dev; /* pci device handle */
#endif /* BCMPLATFORM_BUS */
osl_t *osh;
void *regs; /* SDIO Host Controller address */
bcmsdh_info_t *sdh; /* SDIO Host Controller handle */
void *ch;
unsigned int oob_irq;
unsigned long oob_flags; /* OOB Host specifiction as edge and etc */
};
static bcmsdh_hc_t *sdhcinfo = NULL;
/* driver info, initialized when bcmsdh_register is called */
static bcmsdh_driver_t drvinfo = {NULL, NULL};
/* debugging macros */
#define SDLX_MSG(x)
/**
* Checks to see if vendor and device IDs match a supported SDIO Host Controller.
*/
bool
bcmsdh_chipmatch(uint16 vendor, uint16 device)
{
/* Add other vendors and devices as required */
#ifdef BCMSDIOH_STD
/* Check for Arasan host controller */
if (vendor == VENDOR_SI_IMAGE) {
return (TRUE);
}
/* Check for BRCM 27XX Standard host controller */
if (device == BCM27XX_SDIOH_ID && vendor == VENDOR_BROADCOM) {
return (TRUE);
}
/* Check for BRCM Standard host controller */
if (device == SDIOH_FPGA_ID && vendor == VENDOR_BROADCOM) {
return (TRUE);
}
/* Check for TI PCIxx21 Standard host controller */
if (device == PCIXX21_SDIOH_ID && vendor == VENDOR_TI) {
return (TRUE);
}
if (device == PCIXX21_SDIOH0_ID && vendor == VENDOR_TI) {
return (TRUE);
}
/* Ricoh R5C822 Standard SDIO Host */
if (device == R5C822_SDIOH_ID && vendor == VENDOR_RICOH) {
return (TRUE);
}
/* JMicron Standard SDIO Host */
if (device == JMICRON_SDIOH_ID && vendor == VENDOR_JMICRON) {
return (TRUE);
}
#endif /* BCMSDIOH_STD */
#ifdef BCMSDIOH_SPI
/* This is the PciSpiHost. */
if (device == SPIH_FPGA_ID && vendor == VENDOR_BROADCOM) {
printf("Found PCI SPI Host Controller\n");
return (TRUE);
}
#endif /* BCMSDIOH_SPI */
return (FALSE);
}
#if defined(BCMPLATFORM_BUS)
#if defined(BCMLXSDMMC)
/* forward declarations */
int bcmsdh_probe(struct device *dev);
int bcmsdh_remove(struct device *dev);
EXPORT_SYMBOL(bcmsdh_probe);
EXPORT_SYMBOL(bcmsdh_remove);
#else
/* forward declarations */
static int __devinit bcmsdh_probe(struct device *dev);
static int __devexit bcmsdh_remove(struct device *dev);
#endif /* BCMLXSDMMC */
#ifndef BCMLXSDMMC
static struct device_driver bcmsdh_driver = {
.name = "pxa2xx-mci",
.bus = &platform_bus_type,
.probe = bcmsdh_probe,
.remove = bcmsdh_remove,
.suspend = NULL,
.resume = NULL,
};
#endif /* BCMLXSDMMC */
#ifndef BCMLXSDMMC
static
#endif /* BCMLXSDMMC */
int bcmsdh_probe(struct device *dev)
{
osl_t *osh = NULL;
bcmsdh_hc_t *sdhc = NULL;
ulong regs = 0;
bcmsdh_info_t *sdh = NULL;
#if !defined(BCMLXSDMMC) && defined(BCMPLATFORM_BUS)
struct platform_device *pdev;
struct resource *r;
#endif /* BCMLXSDMMC */
int irq = 0;
uint32 vendevid;
unsigned long irq_flags = 0;
#if !defined(BCMLXSDMMC) && defined(BCMPLATFORM_BUS)
pdev = to_platform_device(dev);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
if (!r || irq == NO_IRQ)
return -ENXIO;
#endif /* BCMLXSDMMC */
#if defined(OOB_INTR_ONLY)
irq_flags = IRQF_TRIGGER_FALLING;
irq = dhd_customer_oob_irq_map(&irq_flags);
if (irq < 0) {
SDLX_MSG(("%s: Host irq is not defined\n", __FUNCTION__));
return 1;
}
#endif /* defined(OOB_INTR_ONLY) */
/* allocate SDIO Host Controller state info */
if (!(osh = osl_attach(dev, PCI_BUS, FALSE))) {
SDLX_MSG(("%s: osl_attach failed\n", __FUNCTION__));
goto err;
}
if (!(sdhc = MALLOC(osh, sizeof(bcmsdh_hc_t)))) {
SDLX_MSG(("%s: out of memory, allocated %d bytes\n",
__FUNCTION__,
MALLOCED(osh)));
goto err;
}
bzero(sdhc, sizeof(bcmsdh_hc_t));
sdhc->osh = osh;
sdhc->dev = (void *)dev;
#ifdef BCMLXSDMMC
if (!(sdh = bcmsdh_attach(osh, (void *)0,
(void **)&regs, irq))) {
SDLX_MSG(("%s: bcmsdh_attach failed\n", __FUNCTION__));
goto err;
}
#else
if (!(sdh = bcmsdh_attach(osh, (void *)r->start,
(void **)&regs, irq))) {
SDLX_MSG(("%s: bcmsdh_attach failed\n", __FUNCTION__));
goto err;
}
#endif /* BCMLXSDMMC */
sdhc->sdh = sdh;
sdhc->oob_irq = irq;
sdhc->oob_flags = irq_flags;
/* chain SDIO Host Controller info together */
sdhc->next = sdhcinfo;
sdhcinfo = sdhc;
/* Read the vendor/device ID from the CIS */
vendevid = bcmsdh_query_device(sdh);
/* try to attach to the target device */
if (!(sdhc->ch = drvinfo.attach((vendevid >> 16),
(vendevid & 0xFFFF), 0, 0, 0, 0,
(void *)regs, NULL, sdh))) {
SDLX_MSG(("%s: device attach failed\n", __FUNCTION__));
goto err;
}
return 0;
/* error handling */
err:
if (sdhc) {
if (sdhc->sdh)
bcmsdh_detach(sdhc->osh, sdhc->sdh);
MFREE(osh, sdhc, sizeof(bcmsdh_hc_t));
}
if (osh)
osl_detach(osh);
return -ENODEV;
}
#ifndef BCMLXSDMMC
static
#endif /* BCMLXSDMMC */
int bcmsdh_remove(struct device *dev)
{
bcmsdh_hc_t *sdhc, *prev;
osl_t *osh;
sdhc = sdhcinfo;
drvinfo.detach(sdhc->ch);
bcmsdh_detach(sdhc->osh, sdhc->sdh);
/* find the SDIO Host Controller state for this pdev and take it out from the list */
for (sdhc = sdhcinfo, prev = NULL; sdhc; sdhc = sdhc->next) {
if (sdhc->dev == (void *)dev) {
if (prev)
prev->next = sdhc->next;
else
sdhcinfo = NULL;
break;
}
prev = sdhc;
}
if (!sdhc) {
SDLX_MSG(("%s: failed\n", __FUNCTION__));
return 0;
}
/* release SDIO Host Controller info */
osh = sdhc->osh;
MFREE(osh, sdhc, sizeof(bcmsdh_hc_t));
osl_detach(osh);
#if !defined(BCMLXSDMMC)
dev_set_drvdata(dev, NULL);
#endif /* !defined(BCMLXSDMMC) */
return 0;
}
#else /* BCMPLATFORM_BUS */
#if !defined(BCMLXSDMMC)
/* forward declarations for PCI probe and remove functions. */
static int __devinit bcmsdh_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
static void __devexit bcmsdh_pci_remove(struct pci_dev *pdev);
/**
* pci id table
*/
static struct pci_device_id bcmsdh_pci_devid[] __devinitdata = {
{ vendor: PCI_ANY_ID,
device: PCI_ANY_ID,
subvendor: PCI_ANY_ID,
subdevice: PCI_ANY_ID,
class: 0,
class_mask: 0,
driver_data: 0,
},
{ 0, }
};
MODULE_DEVICE_TABLE(pci, bcmsdh_pci_devid);
/**
* SDIO Host Controller pci driver info
*/
static struct pci_driver bcmsdh_pci_driver = {
node: {},
name: "bcmsdh",
id_table: bcmsdh_pci_devid,
probe: bcmsdh_pci_probe,
remove: bcmsdh_pci_remove,
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
save_state: NULL,
#endif
suspend: NULL,
resume: NULL,
};
extern uint sd_pci_slot; /* Force detection to a particular PCI */
/* slot only . Allows for having multiple */
/* WL devices at once in a PC */
/* Only one instance of dhd will be */
/* useable at a time */
/* Upper word is bus number, */
/* lower word is slot number */
/* Default value of 0xFFFFffff turns this */
/* off */
module_param(sd_pci_slot, uint, 0);
/**
* Detect supported SDIO Host Controller and attach if found.
*
* Determine if the device described by pdev is a supported SDIO Host
* Controller. If so, attach to it and attach to the target device.
*/
static int __devinit
bcmsdh_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
osl_t *osh = NULL;
bcmsdh_hc_t *sdhc = NULL;
ulong regs;
bcmsdh_info_t *sdh = NULL;
int rc;
if (sd_pci_slot != 0xFFFFffff) {
if (pdev->bus->number != (sd_pci_slot>>16) ||
PCI_SLOT(pdev->devfn) != (sd_pci_slot&0xffff)) {
SDLX_MSG(("%s: %s: bus %X, slot %X, vend %X, dev %X\n",
__FUNCTION__,
bcmsdh_chipmatch(pdev->vendor, pdev->device)
?"Found compatible SDIOHC"
:"Probing unknown device",
pdev->bus->number, PCI_SLOT(pdev->devfn), pdev->vendor,
pdev->device));
return -ENODEV;
}
SDLX_MSG(("%s: %s: bus %X, slot %X, vendor %X, device %X (good PCI location)\n",
__FUNCTION__,
bcmsdh_chipmatch(pdev->vendor, pdev->device)
?"Using compatible SDIOHC"
:"WARNING, forced use of unkown device",
pdev->bus->number, PCI_SLOT(pdev->devfn), pdev->vendor, pdev->device));
}
if ((pdev->vendor == VENDOR_TI) && ((pdev->device == PCIXX21_FLASHMEDIA_ID) ||
(pdev->device == PCIXX21_FLASHMEDIA0_ID))) {
uint32 config_reg;
SDLX_MSG(("%s: Disabling TI FlashMedia Controller.\n", __FUNCTION__));
if (!(osh = osl_attach(pdev, PCI_BUS, FALSE))) {
SDLX_MSG(("%s: osl_attach failed\n", __FUNCTION__));
goto err;
}
config_reg = OSL_PCI_READ_CONFIG(osh, 0x4c, 4);
/*
* Set MMC_SD_DIS bit in FlashMedia Controller.
* Disbling the SD/MMC Controller in the FlashMedia Controller
* allows the Standard SD Host Controller to take over control
* of the SD Slot.
*/
config_reg |= 0x02;
OSL_PCI_WRITE_CONFIG(osh, 0x4c, 4, config_reg);
osl_detach(osh);
}
/* match this pci device with what we support */
/* we can't solely rely on this to believe it is our SDIO Host Controller! */
if (!bcmsdh_chipmatch(pdev->vendor, pdev->device)) {
return -ENODEV;
}
/* this is a pci device we might support */
SDLX_MSG(("%s: Found possible SDIO Host Controller: bus %d slot %d func %d irq %d\n",
__FUNCTION__,
pdev->bus->number, PCI_SLOT(pdev->devfn),
PCI_FUNC(pdev->devfn), pdev->irq));
/* use bcmsdh_query_device() to get the vendor ID of the target device so
* it will eventually appear in the Broadcom string on the console
*/
/* allocate SDIO Host Controller state info */
if (!(osh = osl_attach(pdev, PCI_BUS, FALSE))) {
SDLX_MSG(("%s: osl_attach failed\n", __FUNCTION__));
goto err;
}
if (!(sdhc = MALLOC(osh, sizeof(bcmsdh_hc_t)))) {
SDLX_MSG(("%s: out of memory, allocated %d bytes\n",
__FUNCTION__,
MALLOCED(osh)));
goto err;
}
bzero(sdhc, sizeof(bcmsdh_hc_t));
sdhc->osh = osh;
sdhc->dev = pdev;
/* map to address where host can access */
pci_set_master(pdev);
rc = pci_enable_device(pdev);
if (rc) {
SDLX_MSG(("%s: Cannot enble PCI device\n", __FUNCTION__));
goto err;
}
if (!(sdh = bcmsdh_attach(osh, (void *)(uintptr)pci_resource_start(pdev, 0),
(void **)&regs, pdev->irq))) {
SDLX_MSG(("%s: bcmsdh_attach failed\n", __FUNCTION__));
goto err;
}
sdhc->sdh = sdh;
/* try to attach to the target device */
if (!(sdhc->ch = drvinfo.attach(VENDOR_BROADCOM, /* pdev->vendor, */
bcmsdh_query_device(sdh) & 0xFFFF, 0, 0, 0, 0,
(void *)regs, NULL, sdh))) {
SDLX_MSG(("%s: device attach failed\n", __FUNCTION__));
goto err;
}
/* chain SDIO Host Controller info together */
sdhc->next = sdhcinfo;
sdhcinfo = sdhc;
return 0;
/* error handling */
err:
if (sdhc->sdh)
bcmsdh_detach(sdhc->osh, sdhc->sdh);
if (sdhc)
MFREE(osh, sdhc, sizeof(bcmsdh_hc_t));
if (osh)
osl_detach(osh);
return -ENODEV;
}
/**
* Detach from target devices and SDIO Host Controller
*/
static void __devexit
bcmsdh_pci_remove(struct pci_dev *pdev)
{
bcmsdh_hc_t *sdhc, *prev;
osl_t *osh;
/* find the SDIO Host Controller state for this pdev and take it out from the list */
for (sdhc = sdhcinfo, prev = NULL; sdhc; sdhc = sdhc->next) {
if (sdhc->dev == pdev) {
if (prev)
prev->next = sdhc->next;
else
sdhcinfo = NULL;
break;
}
prev = sdhc;
}
if (!sdhc)
return;
drvinfo.detach(sdhc->ch);
bcmsdh_detach(sdhc->osh, sdhc->sdh);
/* release SDIO Host Controller info */
osh = sdhc->osh;
MFREE(osh, sdhc, sizeof(bcmsdh_hc_t));
osl_detach(osh);
}
#endif /* BCMLXSDMMC */
#endif /* BCMPLATFORM_BUS */
extern int sdio_function_init(void);
int
bcmsdh_register(bcmsdh_driver_t *driver)
{
int error = 0;
drvinfo = *driver;
#if defined(BCMPLATFORM_BUS)
#if defined(BCMLXSDMMC)
SDLX_MSG(("Linux Kernel SDIO/MMC Driver\n"));
error = sdio_function_init();
#else
SDLX_MSG(("Intel PXA270 SDIO Driver\n"));
error = driver_register(&bcmsdh_driver);
#endif /* defined(BCMLXSDMMC) */
return error;
#endif /* defined(BCMPLATFORM_BUS) */
#if !defined(BCMPLATFORM_BUS) && !defined(BCMLXSDMMC)
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
if (!(error = pci_module_init(&bcmsdh_pci_driver)))
return 0;
#else
if (!(error = pci_register_driver(&bcmsdh_pci_driver)))
return 0;
#endif
SDLX_MSG(("%s: pci_module_init failed 0x%x\n", __FUNCTION__, error));
#endif /* BCMPLATFORM_BUS */
return error;
}
extern void sdio_function_cleanup(void);
void
bcmsdh_unregister(void)
{
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
if (bcmsdh_pci_driver.node.next)
#endif
#if defined(BCMPLATFORM_BUS) && !defined(BCMLXSDMMC)
driver_unregister(&bcmsdh_driver);
#endif
#if defined(BCMLXSDMMC)
sdio_function_cleanup();
#endif /* BCMLXSDMMC */
#if !defined(BCMPLATFORM_BUS) && !defined(BCMLXSDMMC)
pci_unregister_driver(&bcmsdh_pci_driver);
#endif /* BCMPLATFORM_BUS */
}
#if defined(OOB_INTR_ONLY)
static irqreturn_t wlan_oob_irq(int irq, void *dev_id)
{
dhd_pub_t *dhdp;
dhdp = (dhd_pub_t *)dev_get_drvdata(sdhcinfo->dev);
if (dhdp == NULL) {
disable_irq(sdhcinfo->oob_irq);
SDLX_MSG(("Out of band GPIO interrupt fired way too early\n"));
return IRQ_HANDLED;
}
WAKE_LOCK_TIMEOUT(dhdp, WAKE_LOCK_TMOUT, 25);
dhdsdio_isr((void *)dhdp->bus);
return IRQ_HANDLED;
}
int bcmsdh_register_oob_intr(void * dhdp)
{
int error = 0;
SDLX_MSG(("%s Enter\n", __FUNCTION__));
dev_set_drvdata(sdhcinfo->dev, dhdp);
/* Refer to customer Host IRQ docs about proper irqflags definition */
error = request_irq(sdhcinfo->oob_irq, wlan_oob_irq, sdhcinfo->oob_flags,
"bcmsdh_sdmmc", NULL);
if (error)
return -ENODEV;
set_irq_wake(sdhcinfo->oob_irq, 1);
return 0;
}
void bcmsdh_unregister_oob_intr(void)
{
SDLX_MSG(("%s: Enter\n", __FUNCTION__));
set_irq_wake(sdhcinfo->oob_irq, 0);
disable_irq(sdhcinfo->oob_irq); /* just in case.. */
free_irq(sdhcinfo->oob_irq, NULL);
}
void bcmsdh_oob_intr_set(bool enable)
{
if (enable)
enable_irq(sdhcinfo->oob_irq);
else
disable_irq(sdhcinfo->oob_irq);
}
#endif /* defined(OOB_INTR_ONLY) */
/* Module parameters specific to each host-controller driver */
extern uint sd_msglevel; /* Debug message level */
module_param(sd_msglevel, uint, 0);
extern uint sd_power; /* 0 = SD Power OFF, 1 = SD Power ON. */
module_param(sd_power, uint, 0);
extern uint sd_clock; /* SD Clock Control, 0 = SD Clock OFF, 1 = SD Clock ON */
module_param(sd_clock, uint, 0);
extern uint sd_divisor; /* Divisor (-1 means external clock) */
module_param(sd_divisor, uint, 0);
extern uint sd_sdmode; /* Default is SD4, 0=SPI, 1=SD1, 2=SD4 */
module_param(sd_sdmode, uint, 0);
extern uint sd_hiok; /* Ok to use hi-speed mode */
module_param(sd_hiok, uint, 0);
extern uint sd_f2_blocksize;
module_param(sd_f2_blocksize, int, 0);
#ifdef BCMSDH_MODULE
EXPORT_SYMBOL(bcmsdh_attach);
EXPORT_SYMBOL(bcmsdh_detach);
EXPORT_SYMBOL(bcmsdh_intr_query);
EXPORT_SYMBOL(bcmsdh_intr_enable);
EXPORT_SYMBOL(bcmsdh_intr_disable);
EXPORT_SYMBOL(bcmsdh_intr_reg);
EXPORT_SYMBOL(bcmsdh_intr_dereg);
#if defined(DHD_DEBUG)
EXPORT_SYMBOL(bcmsdh_intr_pending);
#endif
EXPORT_SYMBOL(bcmsdh_devremove_reg);
EXPORT_SYMBOL(bcmsdh_cfg_read);
EXPORT_SYMBOL(bcmsdh_cfg_write);
EXPORT_SYMBOL(bcmsdh_cis_read);
EXPORT_SYMBOL(bcmsdh_reg_read);
EXPORT_SYMBOL(bcmsdh_reg_write);
EXPORT_SYMBOL(bcmsdh_regfail);
EXPORT_SYMBOL(bcmsdh_send_buf);
EXPORT_SYMBOL(bcmsdh_recv_buf);
EXPORT_SYMBOL(bcmsdh_rwdata);
EXPORT_SYMBOL(bcmsdh_abort);
EXPORT_SYMBOL(bcmsdh_query_device);
EXPORT_SYMBOL(bcmsdh_query_iofnum);
EXPORT_SYMBOL(bcmsdh_iovar_op);
EXPORT_SYMBOL(bcmsdh_register);
EXPORT_SYMBOL(bcmsdh_unregister);
EXPORT_SYMBOL(bcmsdh_chipmatch);
EXPORT_SYMBOL(bcmsdh_reset);
EXPORT_SYMBOL(bcmsdh_get_dstatus);
EXPORT_SYMBOL(bcmsdh_cfg_read_word);
EXPORT_SYMBOL(bcmsdh_cfg_write_word);
EXPORT_SYMBOL(bcmsdh_cur_sbwad);
EXPORT_SYMBOL(bcmsdh_chipinfo);
#endif /* BCMSDH_MODULE */

1299
drivers/net/wireless/bcm4329_245/bcmsdh_sdmmc.c Normal file
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File diff suppressed because it is too large Load Diff

261
drivers/net/wireless/bcm4329_245/bcmsdh_sdmmc_linux.c Normal file
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@ -0,0 +1,261 @@
/*
* BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdh_sdmmc_linux.c,v 1.1.2.5.6.15 2010/04/14 21:11:46 Exp $
*/
#include <typedefs.h>
#include <bcmutils.h>
#include <sdio.h> /* SDIO Specs */
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* to get msglevel bit values */
#include <linux/sched.h> /* request_irq() */
#include <linux/mmc/core.h>
#include <linux/mmc/card.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
#if !defined(SDIO_VENDOR_ID_BROADCOM)
#define SDIO_VENDOR_ID_BROADCOM 0x02d0
#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4325) */
#if !defined(SDIO_DEVICE_ID_BROADCOM_4325)
#define SDIO_DEVICE_ID_BROADCOM_4325 0x0000
#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4325) */
#if !defined(SDIO_DEVICE_ID_BROADCOM_4329)
#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4329) */
#include <bcmsdh_sdmmc.h>
#include <dhd_dbg.h>
extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd);
extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd);
int sdio_function_init(void);
void sdio_function_cleanup(void);
#define DESCRIPTION "bcmsdh_sdmmc Driver"
#define AUTHOR "Broadcom Corporation"
/* module param defaults */
static int clockoverride = 0;
module_param(clockoverride, int, 0644);
MODULE_PARM_DESC(clockoverride, "SDIO card clock override");
PBCMSDH_SDMMC_INSTANCE gInstance;
/* Maximum number of bcmsdh_sdmmc devices supported by driver */
#define BCMSDH_SDMMC_MAX_DEVICES 1
extern int bcmsdh_probe(struct device *dev);
extern int bcmsdh_remove(struct device *dev);
struct device sdmmc_dev;
static int bcmsdh_sdmmc_probe(struct sdio_func *func,
const struct sdio_device_id *id)
{
int ret = 0;
static struct sdio_func sdio_func_0;
sd_trace(("bcmsdh_sdmmc: %s Enter\n", __FUNCTION__));
sd_trace(("sdio_bcmsdh: func->class=%x\n", func->class));
sd_trace(("sdio_vendor: 0x%04x\n", func->vendor));
sd_trace(("sdio_device: 0x%04x\n", func->device));
sd_trace(("Function#: 0x%04x\n", func->num));
if (func->num == 1) {
sdio_func_0.num = 0;
sdio_func_0.card = func->card;
gInstance->func[0] = &sdio_func_0;
if(func->device == 0x4) { /* 4318 */
gInstance->func[2] = NULL;
sd_trace(("NIC found, calling bcmsdh_probe...\n"));
ret = bcmsdh_probe(&sdmmc_dev);
}
}
gInstance->func[func->num] = func;
if (func->num == 2) {
sd_trace(("F2 found, calling bcmsdh_probe...\n"));
ret = bcmsdh_probe(&sdmmc_dev);
}
return ret;
}
static void bcmsdh_sdmmc_remove(struct sdio_func *func)
{
sd_trace(("bcmsdh_sdmmc: %s Enter\n", __FUNCTION__));
sd_info(("sdio_bcmsdh: func->class=%x\n", func->class));
sd_info(("sdio_vendor: 0x%04x\n", func->vendor));
sd_info(("sdio_device: 0x%04x\n", func->device));
sd_info(("Function#: 0x%04x\n", func->num));
if (func->num == 2) {
sd_trace(("F2 found, calling bcmsdh_probe...\n"));
bcmsdh_remove(&sdmmc_dev);
}
}
/* devices we support, null terminated */
static const struct sdio_device_id bcmsdh_sdmmc_ids[] = {
{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4325) },
{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329) },
{ /* end: all zeroes */ },
};
MODULE_DEVICE_TABLE(sdio, bcmsdh_sdmmc_ids);
static struct sdio_driver bcmsdh_sdmmc_driver = {
.probe = bcmsdh_sdmmc_probe,
.remove = bcmsdh_sdmmc_remove,
.name = "bcmsdh_sdmmc",
.id_table = bcmsdh_sdmmc_ids,
};
struct sdos_info {
sdioh_info_t *sd;
spinlock_t lock;
};
int
sdioh_sdmmc_osinit(sdioh_info_t *sd)
{
struct sdos_info *sdos;
sdos = (struct sdos_info*)MALLOC(sd->osh, sizeof(struct sdos_info));
sd->sdos_info = (void*)sdos;
if (sdos == NULL)
return BCME_NOMEM;
sdos->sd = sd;
spin_lock_init(&sdos->lock);
return BCME_OK;
}
void
sdioh_sdmmc_osfree(sdioh_info_t *sd)
{
struct sdos_info *sdos;
ASSERT(sd && sd->sdos_info);
sdos = (struct sdos_info *)sd->sdos_info;
MFREE(sd->osh, sdos, sizeof(struct sdos_info));
}
/* Interrupt enable/disable */
SDIOH_API_RC
sdioh_interrupt_set(sdioh_info_t *sd, bool enable)
{
ulong flags;
struct sdos_info *sdos;
sd_trace(("%s: %s\n", __FUNCTION__, enable ? "Enabling" : "Disabling"));
sdos = (struct sdos_info *)sd->sdos_info;
ASSERT(sdos);
#if !defined(OOB_INTR_ONLY)
if (enable && !(sd->intr_handler && sd->intr_handler_arg)) {
sd_err(("%s: no handler registered, will not enable\n", __FUNCTION__));
return SDIOH_API_RC_FAIL;
}
#endif /* !defined(OOB_INTR_ONLY) */
/* Ensure atomicity for enable/disable calls */
spin_lock_irqsave(&sdos->lock, flags);
sd->client_intr_enabled = enable;
if (enable) {
sdioh_sdmmc_devintr_on(sd);
} else {
sdioh_sdmmc_devintr_off(sd);
}
spin_unlock_irqrestore(&sdos->lock, flags);
return SDIOH_API_RC_SUCCESS;
}
#ifdef BCMSDH_MODULE
static int __init
bcmsdh_module_init(void)
{
int error = 0;
sdio_function_init();
return error;
}
static void __exit
bcmsdh_module_cleanup(void)
{
sdio_function_cleanup();
}
module_init(bcmsdh_module_init);
module_exit(bcmsdh_module_cleanup);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION(DESCRIPTION);
MODULE_AUTHOR(AUTHOR);
#endif /* BCMSDH_MODULE */
/*
* module init
*/
int sdio_function_init(void)
{
int error = 0;
sd_trace(("bcmsdh_sdmmc: %s Enter\n", __FUNCTION__));
gInstance = kzalloc(sizeof(BCMSDH_SDMMC_INSTANCE), GFP_KERNEL);
if (!gInstance)
return -ENOMEM;
bzero(&sdmmc_dev, sizeof(sdmmc_dev));
error = sdio_register_driver(&bcmsdh_sdmmc_driver);
return error;
}
/*
* module cleanup
*/
extern int bcmsdh_remove(struct device *dev);
void sdio_function_cleanup(void)
{
sd_trace(("%s Enter\n", __FUNCTION__));
sdio_unregister_driver(&bcmsdh_sdmmc_driver);
if (gInstance)
kfree(gInstance);
}

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/*
* Broadcom SPI Host Controller Driver - Linux Per-port
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdspi_linux.c,v 1.7.2.1.4.3 2008/06/30 21:09:36 Exp $
*/
#include <typedefs.h>
#include <pcicfg.h>
#include <bcmutils.h>
#include <sdio.h> /* SDIO Specs */
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* to get msglevel bit values */
#include <linux/sched.h> /* request_irq(), free_irq() */
#include <bcmsdspi.h>
#include <bcmspi.h>
extern uint sd_crc;
module_param(sd_crc, uint, 0);
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
#define KERNEL26
#endif
struct sdos_info {
sdioh_info_t *sd;
spinlock_t lock;
wait_queue_head_t intr_wait_queue;
};
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
#define BLOCKABLE() (!in_atomic())
#else
#define BLOCKABLE() (!in_interrupt())
#endif
/* Interrupt handler */
static irqreturn_t
sdspi_isr(int irq, void *dev_id
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20)
, struct pt_regs *ptregs
#endif
)
{
sdioh_info_t *sd;
struct sdos_info *sdos;
bool ours;
sd = (sdioh_info_t *)dev_id;
sd->local_intrcount++;
if (!sd->card_init_done) {
sd_err(("%s: Hey Bogus intr...not even initted: irq %d\n", __FUNCTION__, irq));
return IRQ_RETVAL(FALSE);
} else {
ours = spi_check_client_intr(sd, NULL);
/* For local interrupts, wake the waiting process */
if (ours && sd->got_hcint) {
sdos = (struct sdos_info *)sd->sdos_info;
wake_up_interruptible(&sdos->intr_wait_queue);
}
return IRQ_RETVAL(ours);
}
}
/* Register with Linux for interrupts */
int
spi_register_irq(sdioh_info_t *sd, uint irq)
{
sd_trace(("Entering %s: irq == %d\n", __FUNCTION__, irq));
if (request_irq(irq, sdspi_isr, IRQF_SHARED, "bcmsdspi", sd) < 0) {
sd_err(("%s: request_irq() failed\n", __FUNCTION__));
return ERROR;
}
return SUCCESS;
}
/* Free Linux irq */
void
spi_free_irq(uint irq, sdioh_info_t *sd)
{
free_irq(irq, sd);
}
/* Map Host controller registers */
uint32 *
spi_reg_map(osl_t *osh, uintptr addr, int size)
{
return (uint32 *)REG_MAP(addr, size);
}
void
spi_reg_unmap(osl_t *osh, uintptr addr, int size)
{
REG_UNMAP((void*)(uintptr)addr);
}
int
spi_osinit(sdioh_info_t *sd)
{
struct sdos_info *sdos;
sdos = (struct sdos_info*)MALLOC(sd->osh, sizeof(struct sdos_info));
sd->sdos_info = (void*)sdos;
if (sdos == NULL)
return BCME_NOMEM;
sdos->sd = sd;
spin_lock_init(&sdos->lock);
init_waitqueue_head(&sdos->intr_wait_queue);
return BCME_OK;
}
void
spi_osfree(sdioh_info_t *sd)
{
struct sdos_info *sdos;
ASSERT(sd && sd->sdos_info);
sdos = (struct sdos_info *)sd->sdos_info;
MFREE(sd->osh, sdos, sizeof(struct sdos_info));
}
/* Interrupt enable/disable */
SDIOH_API_RC
sdioh_interrupt_set(sdioh_info_t *sd, bool enable)
{
ulong flags;
struct sdos_info *sdos;
sd_trace(("%s: %s\n", __FUNCTION__, enable ? "Enabling" : "Disabling"));
sdos = (struct sdos_info *)sd->sdos_info;
ASSERT(sdos);
if (!(sd->host_init_done && sd->card_init_done)) {
sd_err(("%s: Card & Host are not initted - bailing\n", __FUNCTION__));
return SDIOH_API_RC_FAIL;
}
if (enable && !(sd->intr_handler && sd->intr_handler_arg)) {
sd_err(("%s: no handler registered, will not enable\n", __FUNCTION__));
return SDIOH_API_RC_FAIL;
}
/* Ensure atomicity for enable/disable calls */
spin_lock_irqsave(&sdos->lock, flags);
sd->client_intr_enabled = enable;
if (enable && !sd->lockcount)
spi_devintr_on(sd);
else
spi_devintr_off(sd);
spin_unlock_irqrestore(&sdos->lock, flags);
return SDIOH_API_RC_SUCCESS;
}
/* Protect against reentrancy (disable device interrupts while executing) */
void
spi_lock(sdioh_info_t *sd)
{
ulong flags;
struct sdos_info *sdos;
sdos = (struct sdos_info *)sd->sdos_info;
ASSERT(sdos);
sd_trace(("%s: %d\n", __FUNCTION__, sd->lockcount));
spin_lock_irqsave(&sdos->lock, flags);
if (sd->lockcount) {
sd_err(("%s: Already locked!\n", __FUNCTION__));
ASSERT(sd->lockcount == 0);
}
spi_devintr_off(sd);
sd->lockcount++;
spin_unlock_irqrestore(&sdos->lock, flags);
}
/* Enable client interrupt */
void
spi_unlock(sdioh_info_t *sd)
{
ulong flags;
struct sdos_info *sdos;
sd_trace(("%s: %d, %d\n", __FUNCTION__, sd->lockcount, sd->client_intr_enabled));
ASSERT(sd->lockcount > 0);
sdos = (struct sdos_info *)sd->sdos_info;
ASSERT(sdos);
spin_lock_irqsave(&sdos->lock, flags);
if (--sd->lockcount == 0 && sd->client_intr_enabled) {
spi_devintr_on(sd);
}
spin_unlock_irqrestore(&sdos->lock, flags);
}
void spi_waitbits(sdioh_info_t *sd, bool yield)
{
struct sdos_info *sdos;
sdos = (struct sdos_info *)sd->sdos_info;
#ifndef BCMSDYIELD
ASSERT(!yield);
#endif
sd_trace(("%s: yield %d canblock %d\n",
__FUNCTION__, yield, BLOCKABLE()));
/* Clear the "interrupt happened" flag and last intrstatus */
sd->got_hcint = FALSE;
#ifdef BCMSDYIELD
if (yield && BLOCKABLE()) {
/* Wait for the indication, the interrupt will be masked when the ISR fires. */
wait_event_interruptible(sdos->intr_wait_queue, (sd->got_hcint));
} else
#endif /* BCMSDYIELD */
{
spi_spinbits(sd);
}
}

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/*
* 'Standard' SDIO HOST CONTROLLER driver - linux portion
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdstd_linux.c,v 1.11.18.2 2008/05/28 18:36:56 Exp $
*/
#include <typedefs.h>
#include <pcicfg.h>
#include <bcmutils.h>
#include <sdio.h> /* SDIO Specs */
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* to get msglevel bit values */
#include <linux/sched.h> /* request_irq() */
#include <bcmsdstd.h>
struct sdos_info {
sdioh_info_t *sd;
spinlock_t lock;
wait_queue_head_t intr_wait_queue;
};
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
#define BLOCKABLE() (!in_atomic())
#else
#define BLOCKABLE() (!in_interrupt())
#endif
/* Interrupt handler */
static irqreturn_t
sdstd_isr(int irq, void *dev_id
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20)
, struct pt_regs *ptregs
#endif
)
{
sdioh_info_t *sd;
struct sdos_info *sdos;
bool ours;
sd = (sdioh_info_t *)dev_id;
if (!sd->card_init_done) {
sd_err(("%s: Hey Bogus intr...not even initted: irq %d\n", __FUNCTION__, irq));
return IRQ_RETVAL(FALSE);
} else {
ours = check_client_intr(sd);
/* For local interrupts, wake the waiting process */
if (ours && sd->got_hcint) {
sd_trace(("INTR->WAKE\n"));
sdos = (struct sdos_info *)sd->sdos_info;
wake_up_interruptible(&sdos->intr_wait_queue);
}
return IRQ_RETVAL(ours);
}
}
/* Register with Linux for interrupts */
int
sdstd_register_irq(sdioh_info_t *sd, uint irq)
{
sd_trace(("Entering %s: irq == %d\n", __FUNCTION__, irq));
if (request_irq(irq, sdstd_isr, IRQF_SHARED, "bcmsdstd", sd) < 0) {
sd_err(("%s: request_irq() failed\n", __FUNCTION__));
return ERROR;
}
return SUCCESS;
}
/* Free Linux irq */
void
sdstd_free_irq(uint irq, sdioh_info_t *sd)
{
free_irq(irq, sd);
}
/* Map Host controller registers */
uint32 *
sdstd_reg_map(osl_t *osh, int32 addr, int size)
{
return (uint32 *)REG_MAP(addr, size);
}
void
sdstd_reg_unmap(osl_t *osh, int32 addr, int size)
{
REG_UNMAP((void*)(uintptr)addr);
}
int
sdstd_osinit(sdioh_info_t *sd)
{
struct sdos_info *sdos;
sdos = (struct sdos_info*)MALLOC(sd->osh, sizeof(struct sdos_info));
sd->sdos_info = (void*)sdos;
if (sdos == NULL)
return BCME_NOMEM;
sdos->sd = sd;
spin_lock_init(&sdos->lock);
init_waitqueue_head(&sdos->intr_wait_queue);
return BCME_OK;
}
void
sdstd_osfree(sdioh_info_t *sd)
{
struct sdos_info *sdos;
ASSERT(sd && sd->sdos_info);
sdos = (struct sdos_info *)sd->sdos_info;
MFREE(sd->osh, sdos, sizeof(struct sdos_info));
}
/* Interrupt enable/disable */
SDIOH_API_RC
sdioh_interrupt_set(sdioh_info_t *sd, bool enable)
{
ulong flags;
struct sdos_info *sdos;
sd_trace(("%s: %s\n", __FUNCTION__, enable ? "Enabling" : "Disabling"));
sdos = (struct sdos_info *)sd->sdos_info;
ASSERT(sdos);
if (!(sd->host_init_done && sd->card_init_done)) {
sd_err(("%s: Card & Host are not initted - bailing\n", __FUNCTION__));
return SDIOH_API_RC_FAIL;
}
if (enable && !(sd->intr_handler && sd->intr_handler_arg)) {
sd_err(("%s: no handler registered, will not enable\n", __FUNCTION__));
return SDIOH_API_RC_FAIL;
}
/* Ensure atomicity for enable/disable calls */
spin_lock_irqsave(&sdos->lock, flags);
sd->client_intr_enabled = enable;
if (enable && !sd->lockcount)
sdstd_devintr_on(sd);
else
sdstd_devintr_off(sd);
spin_unlock_irqrestore(&sdos->lock, flags);
return SDIOH_API_RC_SUCCESS;
}
/* Protect against reentrancy (disable device interrupts while executing) */
void
sdstd_lock(sdioh_info_t *sd)
{
ulong flags;
struct sdos_info *sdos;
sdos = (struct sdos_info *)sd->sdos_info;
ASSERT(sdos);
sd_trace(("%s: %d\n", __FUNCTION__, sd->lockcount));
spin_lock_irqsave(&sdos->lock, flags);
if (sd->lockcount) {
sd_err(("%s: Already locked!\n", __FUNCTION__));
ASSERT(sd->lockcount == 0);
}
sdstd_devintr_off(sd);
sd->lockcount++;
spin_unlock_irqrestore(&sdos->lock, flags);
}
/* Enable client interrupt */
void
sdstd_unlock(sdioh_info_t *sd)
{
ulong flags;
struct sdos_info *sdos;
sd_trace(("%s: %d, %d\n", __FUNCTION__, sd->lockcount, sd->client_intr_enabled));
ASSERT(sd->lockcount > 0);
sdos = (struct sdos_info *)sd->sdos_info;
ASSERT(sdos);
spin_lock_irqsave(&sdos->lock, flags);
if (--sd->lockcount == 0 && sd->client_intr_enabled) {
sdstd_devintr_on(sd);
}
spin_unlock_irqrestore(&sdos->lock, flags);
}
uint16
sdstd_waitbits(sdioh_info_t *sd, uint16 norm, uint16 err, bool yield)
{
struct sdos_info *sdos;
sdos = (struct sdos_info *)sd->sdos_info;
#ifndef BCMSDYIELD
ASSERT(!yield);
#endif
sd_trace(("%s: int 0x%02x err 0x%02x yield %d canblock %d\n",
__FUNCTION__, norm, err, yield, BLOCKABLE()));
/* Clear the "interrupt happened" flag and last intrstatus */
sd->got_hcint = FALSE;
sd->last_intrstatus = 0;
#ifdef BCMSDYIELD
if (yield && BLOCKABLE()) {
/* Enable interrupts, wait for the indication, then disable */
sdstd_intrs_on(sd, norm, err);
wait_event_interruptible(sdos->intr_wait_queue, (sd->got_hcint));
sdstd_intrs_off(sd, norm, err);
} else
#endif /* BCMSDYIELD */
{
sdstd_spinbits(sd, norm, err);
}
sd_trace(("%s: last_intrstatus 0x%04x\n", __FUNCTION__, sd->last_intrstatus));
return sd->last_intrstatus;
}

1838
drivers/net/wireless/bcm4329_245/bcmutils.c Normal file
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199
drivers/net/wireless/bcm4329_245/bcmwifi.c Normal file
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/*
* Misc utility routines used by kernel or app-level.
* Contents are wifi-specific, used by any kernel or app-level
* software that might want wifi things as it grows.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: bcmwifi.c,v 1.18.24.2.4.1 2009/09/25 00:32:01 Exp $
*/
#include <typedefs.h>
#ifdef BCMDRIVER
#include <osl.h>
#include <bcmutils.h>
#define strtoul(nptr, endptr, base) bcm_strtoul((nptr), (endptr), (base))
#define tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
#else
#include <stdio.h>
#include <stdlib.h>
#include <ctype.h>
#endif
#include <bcmwifi.h>
#if defined(WIN32) && (defined(BCMDLL) || defined(WLMDLL))
#include <bcmstdlib.h>
#endif
char *
wf_chspec_ntoa(chanspec_t chspec, char *buf)
{
const char *band, *bw, *sb;
uint channel;
band = "";
bw = "";
sb = "";
channel = CHSPEC_CHANNEL(chspec);
if ((CHSPEC_IS2G(chspec) && channel > CH_MAX_2G_CHANNEL) ||
(CHSPEC_IS5G(chspec) && channel <= CH_MAX_2G_CHANNEL))
band = (CHSPEC_IS2G(chspec)) ? "b" : "a";
if (CHSPEC_IS40(chspec)) {
if (CHSPEC_SB_UPPER(chspec)) {
sb = "u";
channel += CH_10MHZ_APART;
} else {
sb = "l";
channel -= CH_10MHZ_APART;
}
} else if (CHSPEC_IS10(chspec)) {
bw = "n";
}
snprintf(buf, 6, "%d%s%s%s", channel, band, bw, sb);
return (buf);
}
chanspec_t
wf_chspec_aton(char *a)
{
char *endp = NULL;
uint channel, band, bw, ctl_sb;
char c;
channel = strtoul(a, &endp, 10);
if (endp == a)
return 0;
if (channel > MAXCHANNEL)
return 0;
band = ((channel <= CH_MAX_2G_CHANNEL) ? WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G);
bw = WL_CHANSPEC_BW_20;
ctl_sb = WL_CHANSPEC_CTL_SB_NONE;
a = endp;
c = tolower(a[0]);
if (c == '\0')
goto done;
if (c == 'a' || c == 'b') {
band = (c == 'a') ? WL_CHANSPEC_BAND_5G : WL_CHANSPEC_BAND_2G;
a++;
c = tolower(a[0]);
if (c == '\0')
goto done;
}
if (c == 'n') {
bw = WL_CHANSPEC_BW_10;
} else if (c == 'l') {
bw = WL_CHANSPEC_BW_40;
ctl_sb = WL_CHANSPEC_CTL_SB_LOWER;
if (channel <= (MAXCHANNEL - CH_20MHZ_APART))
channel += CH_10MHZ_APART;
else
return 0;
} else if (c == 'u') {
bw = WL_CHANSPEC_BW_40;
ctl_sb = WL_CHANSPEC_CTL_SB_UPPER;
if (channel > CH_20MHZ_APART)
channel -= CH_10MHZ_APART;
else
return 0;
} else {
return 0;
}
done:
return (channel | band | bw | ctl_sb);
}
int
wf_mhz2channel(uint freq, uint start_factor)
{
int ch = -1;
uint base;
int offset;
if (start_factor == 0) {
if (freq >= 2400 && freq <= 2500)
start_factor = WF_CHAN_FACTOR_2_4_G;
else if (freq >= 5000 && freq <= 6000)
start_factor = WF_CHAN_FACTOR_5_G;
}
if (freq == 2484 && start_factor == WF_CHAN_FACTOR_2_4_G)
return 14;
base = start_factor / 2;
if ((freq < base) || (freq > base + 1000))
return -1;
offset = freq - base;
ch = offset / 5;
if (offset != (ch * 5))
return -1;
if (start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 13))
return -1;
return ch;
}
int
wf_channel2mhz(uint ch, uint start_factor)
{
int freq;
if ((start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 14)) ||
(ch <= 200))
freq = -1;
if ((start_factor == WF_CHAN_FACTOR_2_4_G) && (ch == 14))
freq = 2484;
else
freq = ch * 5 + start_factor / 2;
return freq;
}

521
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/*
* Header file describing the internal (inter-module) DHD interfaces.
*
* Provides type definitions and function prototypes used to link the
* DHD OS, bus, and protocol modules.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dhd.h,v 1.32.4.7.2.4.14.44 2010/06/03 21:27:48 Exp $
*/
/****************
* Common types *
*/
#ifndef _dhd_h_
#define _dhd_h_
#if defined(LINUX)
#if defined(CHROMIUMOS_COMPAT_WIRELESS)
#include <linux/sched.h>
#endif
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/random.h>
#include <linux/spinlock.h>
#include <linux/ethtool.h>
#include <asm/uaccess.h>
#include <asm/unaligned.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
#include <linux/wakelock.h>
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
/* The kernel threading is sdio-specific */
#else /* LINUX */
#define ENOMEM 1
#define EFAULT 2
#define EINVAL 3
#define EIO 4
#define ETIMEDOUT 5
#define ERESTARTSYS 6
#endif /* LINUX */
#include <wlioctl.h>
/* Forward decls */
struct dhd_bus;
struct dhd_prot;
struct dhd_info;
/* The level of bus communication with the dongle */
enum dhd_bus_state {
DHD_BUS_DOWN, /* Not ready for frame transfers */
DHD_BUS_LOAD, /* Download access only (CPU reset) */
DHD_BUS_DATA /* Ready for frame transfers */
};
enum dhd_bus_wake_state {
WAKE_LOCK_OFF,
WAKE_LOCK_PRIV,
WAKE_LOCK_DPC,
WAKE_LOCK_IOCTL,
WAKE_LOCK_DOWNLOAD,
WAKE_LOCK_TMOUT,
WAKE_LOCK_WATCHDOG,
WAKE_LOCK_LINK_DOWN_TMOUT,
WAKE_LOCK_SOFTAP_SET,
WAKE_LOCK_SOFTAP_STOP,
WAKE_LOCK_SOFTAP_START,
WAKE_LOCK_MAX
};
enum dhd_prealloc_index {
DHD_PREALLOC_PROT = 0,
DHD_PREALLOC_RXBUF,
DHD_PREALLOC_DATABUF,
DHD_PREALLOC_OSL_BUF
};
#ifdef DHD_USE_STATIC_BUF
extern void * dhd_os_prealloc(int section, unsigned long size);
#endif
/* Common structure for module and instance linkage */
typedef struct dhd_pub {
/* Linkage ponters */
osl_t *osh; /* OSL handle */
struct dhd_bus *bus; /* Bus module handle */
struct dhd_prot *prot; /* Protocol module handle */
struct dhd_info *info; /* Info module handle */
/* Internal dhd items */
bool up; /* Driver up/down (to OS) */
bool txoff; /* Transmit flow-controlled */
bool dongle_reset; /* TRUE = DEVRESET put dongle into reset */
enum dhd_bus_state busstate;
uint hdrlen; /* Total DHD header length (proto + bus) */
uint maxctl; /* Max size rxctl request from proto to bus */
uint rxsz; /* Rx buffer size bus module should use */
uint8 wme_dp; /* wme discard priority */
/* Dongle media info */
bool iswl; /* Dongle-resident driver is wl */
ulong drv_version; /* Version of dongle-resident driver */
struct ether_addr mac; /* MAC address obtained from dongle */
dngl_stats_t dstats; /* Stats for dongle-based data */
/* Additional stats for the bus level */
ulong tx_packets; /* Data packets sent to dongle */
ulong tx_multicast; /* Multicast data packets sent to dongle */
ulong tx_errors; /* Errors in sending data to dongle */
ulong tx_ctlpkts; /* Control packets sent to dongle */
ulong tx_ctlerrs; /* Errors sending control frames to dongle */
ulong rx_packets; /* Packets sent up the network interface */
ulong rx_multicast; /* Multicast packets sent up the network interface */
ulong rx_errors; /* Errors processing rx data packets */
ulong rx_ctlpkts; /* Control frames processed from dongle */
ulong rx_ctlerrs; /* Errors in processing rx control frames */
ulong rx_dropped; /* Packets dropped locally (no memory) */
ulong rx_flushed; /* Packets flushed due to unscheduled sendup thread */
ulong wd_dpc_sched; /* Number of times dhd dpc scheduled by watchdog timer */
ulong rx_readahead_cnt; /* Number of packets where header read-ahead was used. */
ulong tx_realloc; /* Number of tx packets we had to realloc for headroom */
ulong fc_packets; /* Number of flow control pkts recvd */
/* Last error return */
int bcmerror;
uint tickcnt;
/* Last error from dongle */
int dongle_error;
/* Pkt filter defination */
char * pktfilter[100];
int pktfilter_count;
uint8 country_code[WLC_CNTRY_BUF_SZ];
char eventmask[WL_EVENTING_MASK_LEN];
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
struct wake_lock wakelock[WAKE_LOCK_MAX];
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
struct mutex wl_start_stop_lock; /* lock/unlock for Android start/stop */
struct mutex wl_softap_lock; /* lock/unlock for any SoftAP/STA settings */
#endif
} dhd_pub_t;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
#define DHD_PM_RESUME_WAIT_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
#define _DHD_PM_RESUME_WAIT(a, b) do {\
int retry = 0; \
while (dhd_mmc_suspend && retry++ != b) { \
wait_event_timeout(a, FALSE, HZ/100); \
} \
} while (0)
#define DHD_PM_RESUME_WAIT(a) _DHD_PM_RESUME_WAIT(a, 30)
#define DHD_PM_RESUME_WAIT_FOREVER(a) _DHD_PM_RESUME_WAIT(a, ~0)
#define DHD_PM_RESUME_RETURN_ERROR(a) do { if (dhd_mmc_suspend) return a; } while (0)
#define DHD_PM_RESUME_RETURN do { if (dhd_mmc_suspend) return; } while (0)
#define DHD_SPINWAIT_SLEEP_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
#define SPINWAIT_SLEEP(a, exp, us) do { \
uint countdown = (us) + 9999; \
while ((exp) && (countdown >= 10000)) { \
wait_event_timeout(a, FALSE, HZ/100); \
countdown -= 10000; \
} \
} while (0)
#else
#define DHD_PM_RESUME_WAIT_INIT(a)
#define DHD_PM_RESUME_WAIT(a)
#define DHD_PM_RESUME_WAIT_FOREVER(a)
#define DHD_PM_RESUME_RETURN_ERROR(a)
#define DHD_PM_RESUME_RETURN
#define DHD_SPINWAIT_SLEEP_INIT(a)
#define SPINWAIT_SLEEP(a, exp, us) do { \
uint countdown = (us) + 9; \
while ((exp) && (countdown >= 10)) { \
OSL_DELAY(10); \
countdown -= 10; \
} \
} while (0)
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP) */
#define DHD_IF_VIF 0x01 /* Virtual IF (Hidden from user) */
inline static void MUTEX_LOCK_INIT(dhd_pub_t * dhdp)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_init(&dhdp->wl_start_stop_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
inline static void MUTEX_LOCK(dhd_pub_t * dhdp)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_lock(&dhdp->wl_start_stop_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
inline static void MUTEX_UNLOCK(dhd_pub_t * dhdp)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_unlock(&dhdp->wl_start_stop_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
inline static void MUTEX_LOCK_SOFTAP_SET_INIT(dhd_pub_t * dhdp)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_init(&dhdp->wl_softap_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
inline static void MUTEX_LOCK_SOFTAP_SET(dhd_pub_t * dhdp)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_lock(&dhdp->wl_softap_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
inline static void MUTEX_UNLOCK_SOFTAP_SET(dhd_pub_t * dhdp)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_unlock(&dhdp->wl_softap_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
extern struct mutex g_wl_ss_scan_lock; /* lock/unlock for Scan/Cache settings */
#endif
inline static void MUTEX_LOCK_WL_SCAN_SET_INIT(void)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_init(&g_wl_ss_scan_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
inline static void MUTEX_LOCK_WL_SCAN_SET(void)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_lock(&g_wl_ss_scan_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
inline static void MUTEX_UNLOCK_WL_SCAN_SET(void)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && 1
mutex_unlock(&g_wl_ss_scan_lock);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
}
inline static void WAKE_LOCK_INIT(dhd_pub_t * dhdp, int index, char * y)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
wake_lock_init(&dhdp->wakelock[index], WAKE_LOCK_SUSPEND, y);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
}
inline static void WAKE_LOCK(dhd_pub_t * dhdp, int index)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
wake_lock(&dhdp->wakelock[index]);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
}
inline static void WAKE_UNLOCK(dhd_pub_t * dhdp, int index)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
wake_unlock(&dhdp->wakelock[index]);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
}
inline static void WAKE_LOCK_TIMEOUT(dhd_pub_t * dhdp, int index, long time)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
wake_lock_timeout(&dhdp->wakelock[index], time);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
}
inline static void WAKE_LOCK_DESTROY(dhd_pub_t * dhdp, int index)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
wake_lock_destroy(&dhdp->wakelock[index]);
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
}
typedef struct dhd_if_event {
uint8 ifidx;
uint8 action;
uint8 flags;
uint8 bssidx;
} dhd_if_event_t;
/*
* Exported from dhd OS modules (dhd_linux/dhd_ndis)
*/
/* To allow osl_attach/detach calls from os-independent modules */
osl_t *dhd_osl_attach(void *pdev, uint bustype);
void dhd_osl_detach(osl_t *osh);
/* Indication from bus module regarding presence/insertion of dongle.
* Return dhd_pub_t pointer, used as handle to OS module in later calls.
* Returned structure should have bus and prot pointers filled in.
* bus_hdrlen specifies required headroom for bus module header.
*/
extern dhd_pub_t *dhd_attach(osl_t *osh, struct dhd_bus *bus, uint bus_hdrlen);
extern int dhd_net_attach(dhd_pub_t *dhdp, int idx);
/* Indication from bus module regarding removal/absence of dongle */
extern void dhd_detach(dhd_pub_t *dhdp);
/* Indication from bus module to change flow-control state */
extern void dhd_txflowcontrol(dhd_pub_t *dhdp, int ifidx, bool on);
extern bool dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, void *pkt, int prec);
/* Receive frame for delivery to OS. Callee disposes of rxp. */
extern void dhd_rx_frame(dhd_pub_t *dhdp, int ifidx, void *rxp, int numpkt);
/* Return pointer to interface name */
extern char *dhd_ifname(dhd_pub_t *dhdp, int idx);
/* Request scheduling of the bus dpc */
extern void dhd_sched_dpc(dhd_pub_t *dhdp);
/* Notify tx completion */
extern void dhd_txcomplete(dhd_pub_t *dhdp, void *txp, bool success);
/* Query ioctl */
extern int dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len);
/* OS independent layer functions */
extern int dhd_os_proto_block(dhd_pub_t * pub);
extern int dhd_os_proto_unblock(dhd_pub_t * pub);
extern int dhd_os_ioctl_resp_wait(dhd_pub_t * pub, uint * condition, bool * pending);
extern int dhd_os_ioctl_resp_wake(dhd_pub_t * pub);
extern unsigned int dhd_os_get_ioctl_resp_timeout(void);
extern void dhd_os_set_ioctl_resp_timeout(unsigned int timeout_msec);
extern void * dhd_os_open_image(char * filename);
extern int dhd_os_get_image_block(char * buf, int len, void * image);
extern void dhd_os_close_image(void * image);
extern void dhd_os_wd_timer(void *bus, uint wdtick);
extern void dhd_os_sdlock(dhd_pub_t * pub);
extern void dhd_os_sdunlock(dhd_pub_t * pub);
extern void dhd_os_sdlock_txq(dhd_pub_t * pub);
extern void dhd_os_sdunlock_txq(dhd_pub_t * pub);
extern void dhd_os_sdlock_rxq(dhd_pub_t * pub);
extern void dhd_os_sdunlock_rxq(dhd_pub_t * pub);
extern void dhd_os_sdlock_sndup_rxq(dhd_pub_t * pub);
extern void dhd_customer_gpio_wlan_ctrl(int onoff);
extern int dhd_custom_get_mac_address(unsigned char *buf);
extern void dhd_os_sdunlock_sndup_rxq(dhd_pub_t * pub);
extern void dhd_os_sdlock_eventq(dhd_pub_t * pub);
extern void dhd_os_sdunlock_eventq(dhd_pub_t * pub);
#ifdef DHD_DEBUG
extern int write_to_file(dhd_pub_t *dhd, uint8 *buf, int size);
#endif /* DHD_DEBUG */
#if defined(OOB_INTR_ONLY)
extern int dhd_customer_oob_irq_map(unsigned long *irq_flags_ptr);
#endif /* defined(OOB_INTR_ONLY) */
extern void dhd_os_sdtxlock(dhd_pub_t * pub);
extern void dhd_os_sdtxunlock(dhd_pub_t * pub);
int setScheduler(struct task_struct *p, int policy, struct sched_param *param);
typedef struct {
uint32 limit; /* Expiration time (usec) */
uint32 increment; /* Current expiration increment (usec) */
uint32 elapsed; /* Current elapsed time (usec) */
uint32 tick; /* O/S tick time (usec) */
} dhd_timeout_t;
extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec);
extern int dhd_timeout_expired(dhd_timeout_t *tmo);
extern int dhd_ifname2idx(struct dhd_info *dhd, char *name);
extern uint8 *dhd_bssidx2bssid(dhd_pub_t *dhd, int idx);
extern int wl_host_event(struct dhd_info *dhd, int *idx, void *pktdata,
wl_event_msg_t *, void **data_ptr);
extern void wl_event_to_host_order(wl_event_msg_t * evt);
extern void dhd_common_init(void);
extern int dhd_add_if(struct dhd_info *dhd, int ifidx, void *handle,
char *name, uint8 *mac_addr, uint32 flags, uint8 bssidx);
extern void dhd_del_if(struct dhd_info *dhd, int ifidx);
extern void dhd_vif_add(struct dhd_info *dhd, int ifidx, char * name);
extern void dhd_vif_del(struct dhd_info *dhd, int ifidx);
extern void dhd_event(struct dhd_info *dhd, char *evpkt, int evlen, int ifidx);
extern void dhd_vif_sendup(struct dhd_info *dhd, int ifidx, uchar *cp, int len);
/* Send packet to dongle via data channel */
extern int dhd_sendpkt(dhd_pub_t *dhdp, int ifidx, void *pkt);
/* Send event to host */
extern void dhd_sendup_event(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data);
extern int dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag);
extern uint dhd_bus_status(dhd_pub_t *dhdp);
extern int dhd_bus_start(dhd_pub_t *dhdp);
extern void print_buf(void *pbuf, int len, int bytes_per_line);
typedef enum cust_gpio_modes {
WLAN_RESET_ON,
WLAN_RESET_OFF,
WLAN_POWER_ON,
WLAN_POWER_OFF
} cust_gpio_modes_t;
extern int wl_iw_iscan_set_scan_broadcast_prep(struct net_device *dev, uint flag);
extern int wl_iw_send_priv_event(struct net_device *dev, char *flag);
/*
* Insmod parameters for debug/test
*/
/* Watchdog timer interval */
extern uint dhd_watchdog_ms;
#if defined(DHD_DEBUG)
/* Console output poll interval */
extern uint dhd_console_ms;
#endif /* defined(DHD_DEBUG) */
/* Use interrupts */
extern uint dhd_intr;
/* Use polling */
extern uint dhd_poll;
/* ARP offload agent mode */
extern uint dhd_arp_mode;
/* ARP offload enable */
extern uint dhd_arp_enable;
/* Pkt filte enable control */
extern uint dhd_pkt_filter_enable;
/* Pkt filter init setup */
extern uint dhd_pkt_filter_init;
/* Pkt filter mode control */
extern uint dhd_master_mode;
/* Roaming mode control */
extern uint dhd_roam;
/* Roaming mode control */
extern uint dhd_radio_up;
/* Initial idletime ticks (may be -1 for immediate idle, 0 for no idle) */
extern int dhd_idletime;
#define DHD_IDLETIME_TICKS 1
/* SDIO Drive Strength */
extern uint dhd_sdiod_drive_strength;
/* Override to force tx queueing all the time */
extern uint dhd_force_tx_queueing;
#ifdef SDTEST
/* Echo packet generator (SDIO), pkts/s */
extern uint dhd_pktgen;
/* Echo packet len (0 => sawtooth, max 1800) */
extern uint dhd_pktgen_len;
#define MAX_PKTGEN_LEN 1800
#endif
/* optionally set by a module_param_string() */
#define MOD_PARAM_PATHLEN 2048
extern char fw_path[MOD_PARAM_PATHLEN];
extern char nv_path[MOD_PARAM_PATHLEN];
/* For supporting multiple interfaces */
#define DHD_MAX_IFS 16
#define DHD_DEL_IF -0xe
#define DHD_BAD_IF -0xf
#ifdef APSTA_PINGTEST
#define MAX_GUEST 8
#endif
extern void dhd_wait_for_event(dhd_pub_t *dhd, bool *lockvar);
extern void dhd_wait_event_wakeup(dhd_pub_t*dhd);
#endif /* _dhd_h_ */

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/*
* Header file describing the internal (inter-module) DHD interfaces.
*
* Provides type definitions and function prototypes used to link the
* DHD OS, bus, and protocol modules.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dhd_bus.h,v 1.4.6.3.2.3.6.6 2010/05/17 18:18:13 Exp $
*/
#ifndef _dhd_bus_h_
#define _dhd_bus_h_
/*
* Exported from dhd bus module (dhd_usb, dhd_sdio)
*/
/* Indicate (dis)interest in finding dongles. */
extern int dhd_bus_register(void);
extern void dhd_bus_unregister(void);
/* Download firmware image and nvram image */
extern bool dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
char *fw_path, char *nv_path);
/* Stop bus module: clear pending frames, disable data flow */
extern void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex);
/* Initialize bus module: prepare for communication w/dongle */
extern int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex);
/* Send a data frame to the dongle. Callee disposes of txp. */
extern int dhd_bus_txdata(struct dhd_bus *bus, void *txp);
/* Send/receive a control message to/from the dongle.
* Expects caller to enforce a single outstanding transaction.
*/
extern int dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen);
extern int dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen);
/* Watchdog timer function */
extern bool dhd_bus_watchdog(dhd_pub_t *dhd);
#ifdef DHD_DEBUG
/* Device console input function */
extern int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen);
#endif
/* Deferred processing for the bus, return TRUE requests reschedule */
extern bool dhd_bus_dpc(struct dhd_bus *bus);
extern void dhd_bus_isr(bool * InterruptRecognized, bool * QueueMiniportHandleInterrupt, void *arg);
/* Check for and handle local prot-specific iovar commands */
extern int dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
void *params, int plen, void *arg, int len, bool set);
/* Add bus dump output to a buffer */
extern void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
/* Clear any bus counters */
extern void dhd_bus_clearcounts(dhd_pub_t *dhdp);
/* return the dongle chipid */
extern uint dhd_bus_chip(struct dhd_bus *bus);
/* Set user-specified nvram parameters. */
extern void dhd_bus_set_nvram_params(struct dhd_bus * bus, const char *nvram_params);
extern void *dhd_bus_pub(struct dhd_bus *bus);
extern void *dhd_bus_txq(struct dhd_bus *bus);
extern uint dhd_bus_hdrlen(struct dhd_bus *bus);
#endif /* _dhd_bus_h_ */

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/*
* DHD Protocol Module for CDC and BDC.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dhd_cdc.c,v 1.22.4.2.4.7.2.41 2010/06/23 19:58:18 Exp $
*
* BDC is like CDC, except it includes a header for data packets to convey
* packet priority over the bus, and flags (e.g. to indicate checksum status
* for dongle offload).
*/
#include <typedefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <bcmcdc.h>
#include <bcmendian.h>
#include <dngl_stats.h>
#include <dhd.h>
#include <dhd_proto.h>
#include <dhd_bus.h>
#include <dhd_dbg.h>
#ifdef CUSTOMER_HW2
int wifi_get_mac_addr(unsigned char *buf);
#endif
extern int dhd_preinit_ioctls(dhd_pub_t *dhd);
/* Packet alignment for most efficient SDIO (can change based on platform) */
#ifndef DHD_SDALIGN
#define DHD_SDALIGN 32
#endif
#if !ISPOWEROF2(DHD_SDALIGN)
#error DHD_SDALIGN is not a power of 2!
#endif
#define RETRIES 2 /* # of retries to retrieve matching ioctl response */
#define BUS_HEADER_LEN (16+DHD_SDALIGN) /* Must be atleast SDPCM_RESERVE
* defined in dhd_sdio.c (amount of header tha might be added)
* plus any space that might be needed for alignment padding.
*/
#define ROUND_UP_MARGIN 2048 /* Biggest SDIO block size possible for
* round off at the end of buffer
*/
typedef struct dhd_prot {
uint16 reqid;
uint8 pending;
uint32 lastcmd;
uint8 bus_header[BUS_HEADER_LEN];
cdc_ioctl_t msg;
unsigned char buf[WLC_IOCTL_MAXLEN + ROUND_UP_MARGIN];
} dhd_prot_t;
static int
dhdcdc_msg(dhd_pub_t *dhd)
{
dhd_prot_t *prot = dhd->prot;
int len = ltoh32(prot->msg.len) + sizeof(cdc_ioctl_t);
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
/* NOTE : cdc->msg.len holds the desired length of the buffer to be
* returned. Only up to CDC_MAX_MSG_SIZE of this buffer area
* is actually sent to the dongle
*/
if (len > CDC_MAX_MSG_SIZE)
len = CDC_MAX_MSG_SIZE;
/* Send request */
return dhd_bus_txctl(dhd->bus, (uchar*)&prot->msg, len);
}
static int
dhdcdc_cmplt(dhd_pub_t *dhd, uint32 id, uint32 len)
{
int ret;
dhd_prot_t *prot = dhd->prot;
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
do {
ret = dhd_bus_rxctl(dhd->bus, (uchar*)&prot->msg, len+sizeof(cdc_ioctl_t));
if (ret < 0)
break;
} while (CDC_IOC_ID(ltoh32(prot->msg.flags)) != id);
return ret;
}
int
dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
{
dhd_prot_t *prot = dhd->prot;
cdc_ioctl_t *msg = &prot->msg;
void *info;
int ret = 0, retries = 0;
uint32 id, flags = 0;
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
DHD_CTL(("%s: cmd %d len %d\n", __FUNCTION__, cmd, len));
/* Respond "bcmerror" and "bcmerrorstr" with local cache */
if (cmd == WLC_GET_VAR && buf)
{
if (!strcmp((char *)buf, "bcmerrorstr"))
{
strncpy((char *)buf, bcmerrorstr(dhd->dongle_error), BCME_STRLEN);
goto done;
}
else if (!strcmp((char *)buf, "bcmerror"))
{
*(int *)buf = dhd->dongle_error;
goto done;
}
}
memset(msg, 0, sizeof(cdc_ioctl_t));
msg->cmd = htol32(cmd);
msg->len = htol32(len);
msg->flags = (++prot->reqid << CDCF_IOC_ID_SHIFT);
CDC_SET_IF_IDX(msg, ifidx);
msg->flags = htol32(msg->flags);
if (buf)
memcpy(prot->buf, buf, len);
if ((ret = dhdcdc_msg(dhd)) < 0) {
DHD_ERROR(("dhdcdc_query_ioctl: dhdcdc_msg failed w/status %d\n", ret));
goto done;
}
retry:
/* wait for interrupt and get first fragment */
if ((ret = dhdcdc_cmplt(dhd, prot->reqid, len)) < 0)
goto done;
flags = ltoh32(msg->flags);
id = (flags & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT;
if ((id < prot->reqid) && (++retries < RETRIES))
goto retry;
if (id != prot->reqid) {
DHD_ERROR(("%s: %s: unexpected request id %d (expected %d)\n",
dhd_ifname(dhd, ifidx), __FUNCTION__, id, prot->reqid));
ret = -EINVAL;
goto done;
}
/* Check info buffer */
info = (void*)&msg[1];
/* Copy info buffer */
if (buf)
{
if (ret < (int)len)
len = ret;
memcpy(buf, info, len);
}
/* Check the ERROR flag */
if (flags & CDCF_IOC_ERROR)
{
ret = ltoh32(msg->status);
/* Cache error from dongle */
dhd->dongle_error = ret;
}
done:
return ret;
}
int
dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
{
dhd_prot_t *prot = dhd->prot;
cdc_ioctl_t *msg = &prot->msg;
int ret = 0;
uint32 flags, id;
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
DHD_CTL(("%s: cmd %d len %d\n", __FUNCTION__, cmd, len));
memset(msg, 0, sizeof(cdc_ioctl_t));
msg->cmd = htol32(cmd);
msg->len = htol32(len);
msg->flags = (++prot->reqid << CDCF_IOC_ID_SHIFT) | CDCF_IOC_SET;
CDC_SET_IF_IDX(msg, ifidx);
msg->flags = htol32(msg->flags);
if (buf)
memcpy(prot->buf, buf, len);
if ((ret = dhdcdc_msg(dhd)) < 0)
goto done;
if ((ret = dhdcdc_cmplt(dhd, prot->reqid, len)) < 0)
goto done;
flags = ltoh32(msg->flags);
id = (flags & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT;
if (id != prot->reqid) {
DHD_ERROR(("%s: %s: unexpected request id %d (expected %d)\n",
dhd_ifname(dhd, ifidx), __FUNCTION__, id, prot->reqid));
ret = -EINVAL;
goto done;
}
/* Check the ERROR flag */
if (flags & CDCF_IOC_ERROR)
{
ret = ltoh32(msg->status);
/* Cache error from dongle */
dhd->dongle_error = ret;
}
done:
return ret;
}
extern int dhd_bus_interface(struct dhd_bus *bus, uint arg, void* arg2);
int
dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t * ioc, void * buf, int len)
{
dhd_prot_t *prot = dhd->prot;
int ret = -1;
if (dhd->busstate == DHD_BUS_DOWN) {
DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
return ret;
}
dhd_os_proto_block(dhd);
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
ASSERT(len <= WLC_IOCTL_MAXLEN);
if (len > WLC_IOCTL_MAXLEN)
goto done;
if (prot->pending == TRUE) {
DHD_TRACE(("CDC packet is pending!!!! cmd=0x%x (%lu) lastcmd=0x%x (%lu)\n",
ioc->cmd, (unsigned long)ioc->cmd, prot->lastcmd,
(unsigned long)prot->lastcmd));
if ((ioc->cmd == WLC_SET_VAR) || (ioc->cmd == WLC_GET_VAR)) {
DHD_TRACE(("iovar cmd=%s\n", (char*)buf));
}
goto done;
}
prot->pending = TRUE;
prot->lastcmd = ioc->cmd;
if (ioc->set)
ret = dhdcdc_set_ioctl(dhd, ifidx, ioc->cmd, buf, len);
else {
ret = dhdcdc_query_ioctl(dhd, ifidx, ioc->cmd, buf, len);
if (ret > 0)
ioc->used = ret - sizeof(cdc_ioctl_t);
}
/* Too many programs assume ioctl() returns 0 on success */
if (ret >= 0)
ret = 0;
else {
cdc_ioctl_t *msg = &prot->msg;
ioc->needed = ltoh32(msg->len); /* len == needed when set/query fails from dongle */
}
/* Intercept the wme_dp ioctl here */
if ((!ret) && (ioc->cmd == WLC_SET_VAR) && (!strcmp(buf, "wme_dp"))) {
int slen, val = 0;
slen = strlen("wme_dp") + 1;
if (len >= (int)(slen + sizeof(int)))
bcopy(((char *)buf + slen), &val, sizeof(int));
dhd->wme_dp = (uint8) ltoh32(val);
}
prot->pending = FALSE;
done:
dhd_os_proto_unblock(dhd);
return ret;
}
int
dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
void *params, int plen, void *arg, int len, bool set)
{
return BCME_UNSUPPORTED;
}
void
dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
{
bcm_bprintf(strbuf, "Protocol CDC: reqid %d\n", dhdp->prot->reqid);
}
#ifdef APSTA_PINGTEST
extern struct ether_addr guest_eas[MAX_GUEST];
#endif
void
dhd_prot_hdrpush(dhd_pub_t *dhd, int ifidx, void *pktbuf)
{
#ifdef BDC
struct bdc_header *h;
#ifdef APSTA_PINGTEST
struct ether_header *eh;
int i;
#ifdef DHD_DEBUG
char eabuf1[ETHER_ADDR_STR_LEN];
char eabuf2[ETHER_ADDR_STR_LEN];
#endif /* DHD_DEBUG */
#endif /* APSTA_PINGTEST */
#endif /* BDC */
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
#ifdef BDC
/* Push BDC header used to convey priority for buses that don't */
#ifdef APSTA_PINGTEST
eh = (struct ether_header *)PKTDATA(dhd->osh, pktbuf);
#endif
PKTPUSH(dhd->osh, pktbuf, BDC_HEADER_LEN);
h = (struct bdc_header *)PKTDATA(dhd->osh, pktbuf);
h->flags = (BDC_PROTO_VER << BDC_FLAG_VER_SHIFT);
if (PKTSUMNEEDED(pktbuf))
h->flags |= BDC_FLAG_SUM_NEEDED;
h->priority = (PKTPRIO(pktbuf) & BDC_PRIORITY_MASK);
h->flags2 = 0;
#ifdef APSTA_PINGTEST
for (i = 0; i < MAX_GUEST; ++i) {
if (!ETHER_ISNULLADDR(eh->ether_dhost) &&
bcmp(eh->ether_dhost, guest_eas[i].octet, ETHER_ADDR_LEN) == 0) {
DHD_TRACE(("send on if 1; sa %s, da %s\n",
bcm_ether_ntoa((struct ether_addr *)(eh->ether_shost), eabuf1),
bcm_ether_ntoa((struct ether_addr *)(eh->ether_dhost), eabuf2)));
/* assume all guest STAs are on interface 1 */
h->flags2 = 1;
break;
}
}
#endif /* APSTA_PINGTEST */
h->rssi = 0;
#endif /* BDC */
BDC_SET_IF_IDX(h, ifidx);
}
bool
dhd_proto_fcinfo(dhd_pub_t *dhd, void *pktbuf, uint8 *fcbits)
{
#ifdef BDC
struct bdc_header *h;
if (PKTLEN(dhd->osh, pktbuf) < BDC_HEADER_LEN) {
DHD_ERROR(("%s: rx data too short (%d < %d)\n",
__FUNCTION__, PKTLEN(dhd->osh, pktbuf), BDC_HEADER_LEN));
return BCME_ERROR;
}
h = (struct bdc_header *)PKTDATA(dhd->osh, pktbuf);
*fcbits = h->priority >> BDC_PRIORITY_FC_SHIFT;
if ((h->flags2 & BDC_FLAG2_FC_FLAG) == BDC_FLAG2_FC_FLAG)
return TRUE;
#endif
return FALSE;
}
int
dhd_prot_hdrpull(dhd_pub_t *dhd, int *ifidx, void *pktbuf)
{
#ifdef BDC
struct bdc_header *h;
#endif
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
#ifdef BDC
/* Pop BDC header used to convey priority for buses that don't */
if (PKTLEN(dhd->osh, pktbuf) < BDC_HEADER_LEN) {
DHD_ERROR(("%s: rx data too short (%d < %d)\n", __FUNCTION__,
PKTLEN(dhd->osh, pktbuf), BDC_HEADER_LEN));
return BCME_ERROR;
}
h = (struct bdc_header *)PKTDATA(dhd->osh, pktbuf);
if ((*ifidx = BDC_GET_IF_IDX(h)) >= DHD_MAX_IFS) {
DHD_ERROR(("%s: rx data ifnum out of range (%d)\n",
__FUNCTION__, *ifidx));
return BCME_ERROR;
}
if (((h->flags & BDC_FLAG_VER_MASK) >> BDC_FLAG_VER_SHIFT) != BDC_PROTO_VER) {
DHD_ERROR(("%s: non-BDC packet received, flags 0x%x\n",
dhd_ifname(dhd, *ifidx), h->flags));
return BCME_ERROR;
}
if (h->flags & BDC_FLAG_SUM_GOOD) {
DHD_INFO(("%s: BDC packet received with good rx-csum, flags 0x%x\n",
dhd_ifname(dhd, *ifidx), h->flags));
PKTSETSUMGOOD(pktbuf, TRUE);
}
PKTSETPRIO(pktbuf, (h->priority & BDC_PRIORITY_MASK));
PKTPULL(dhd->osh, pktbuf, BDC_HEADER_LEN);
#endif /* BDC */
return 0;
}
int
dhd_prot_attach(dhd_pub_t *dhd)
{
dhd_prot_t *cdc;
#ifndef DHD_USE_STATIC_BUF
if (!(cdc = (dhd_prot_t *)MALLOC(dhd->osh, sizeof(dhd_prot_t)))) {
DHD_ERROR(("%s: kmalloc failed\n", __FUNCTION__));
goto fail;
}
#else
if (!(cdc = (dhd_prot_t *)dhd_os_prealloc(DHD_PREALLOC_PROT, sizeof(dhd_prot_t)))) {
DHD_ERROR(("%s: kmalloc failed\n", __FUNCTION__));
goto fail;
}
#endif /* DHD_USE_STATIC_BUF */
memset(cdc, 0, sizeof(dhd_prot_t));
/* ensure that the msg buf directly follows the cdc msg struct */
if ((uintptr)(&cdc->msg + 1) != (uintptr)cdc->buf) {
DHD_ERROR(("dhd_prot_t is not correctly defined\n"));
goto fail;
}
dhd->prot = cdc;
#ifdef BDC
dhd->hdrlen += BDC_HEADER_LEN;
#endif
dhd->maxctl = WLC_IOCTL_MAXLEN + sizeof(cdc_ioctl_t) + ROUND_UP_MARGIN;
return 0;
fail:
#ifndef DHD_USE_STATIC_BUF
if (cdc != NULL)
MFREE(dhd->osh, cdc, sizeof(dhd_prot_t));
#endif
return BCME_NOMEM;
}
/* ~NOTE~ What if another thread is waiting on the semaphore? Holding it? */
void
dhd_prot_detach(dhd_pub_t *dhd)
{
#ifndef DHD_USE_STATIC_BUF
MFREE(dhd->osh, dhd->prot, sizeof(dhd_prot_t));
#endif
dhd->prot = NULL;
}
void
dhd_prot_dstats(dhd_pub_t *dhd)
{
/* No stats from dongle added yet, copy bus stats */
dhd->dstats.tx_packets = dhd->tx_packets;
dhd->dstats.tx_errors = dhd->tx_errors;
dhd->dstats.rx_packets = dhd->rx_packets;
dhd->dstats.rx_errors = dhd->rx_errors;
dhd->dstats.rx_dropped = dhd->rx_dropped;
dhd->dstats.multicast = dhd->rx_multicast;
return;
}
int
dhd_prot_init(dhd_pub_t *dhd)
{
int ret = 0;
char buf[128];
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
dhd_os_proto_block(dhd);
/* Get the device MAC address */
strcpy(buf, "cur_etheraddr");
ret = dhdcdc_query_ioctl(dhd, 0, WLC_GET_VAR, buf, sizeof(buf));
if (ret < 0) {
dhd_os_proto_unblock(dhd);
return ret;
}
memcpy(dhd->mac.octet, buf, ETHER_ADDR_LEN);
dhd_os_proto_unblock(dhd);
#ifdef EMBEDDED_PLATFORM
ret = dhd_preinit_ioctls(dhd);
#endif /* EMBEDDED_PLATFORM */
/* Always assumes wl for now */
dhd->iswl = TRUE;
return ret;
}
void
dhd_prot_stop(dhd_pub_t *dhd)
{
/* Nothing to do for CDC */
}

1976
drivers/net/wireless/bcm4329_245/dhd_common.c Normal file
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File diff suppressed because it is too large Load Diff

173
drivers/net/wireless/bcm4329_245/dhd_custom_gpio.c Normal file
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@ -0,0 +1,173 @@
/*
* Customer code to add GPIO control during WLAN start/stop
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dhd_custom_gpio.c,v 1.1.4.7 2010/06/03 21:27:48 Exp $
*/
#include <typedefs.h>
#include <linuxver.h>
#include <osl.h>
#include <bcmutils.h>
#include <dngl_stats.h>
#include <dhd.h>
#include <wlioctl.h>
#include <wl_iw.h>
#define WL_ERROR(x) printf x
#define WL_TRACE(x)
#ifdef CUSTOMER_HW
extern void bcm_wlan_power_off(int);
extern void bcm_wlan_power_on(int);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
int wifi_set_carddetect(int on);
int wifi_set_power(int on, unsigned long msec);
int wifi_get_irq_number(unsigned long *irq_flags_ptr);
#endif
#if defined(OOB_INTR_ONLY)
#if defined(BCMLXSDMMC)
extern int sdioh_mmc_irq(int irq);
#endif /* (BCMLXSDMMC) */
#ifdef CUSTOMER_HW3
#include <mach/gpio.h>
#endif
/* Customer specific Host GPIO defintion */
static int dhd_oob_gpio_num = -1; /* GG 19 */
module_param(dhd_oob_gpio_num, int, 0644);
MODULE_PARM_DESC(dhd_oob_gpio_num, "DHD oob gpio number");
int dhd_customer_oob_irq_map(unsigned long *irq_flags_ptr)
{
int host_oob_irq = 0;
#ifdef CUSTOMER_HW2
host_oob_irq = wifi_get_irq_number(irq_flags_ptr);
#else /* for NOT CUSTOMER_HW2 */
#if defined(CUSTOM_OOB_GPIO_NUM)
if (dhd_oob_gpio_num < 0) {
dhd_oob_gpio_num = CUSTOM_OOB_GPIO_NUM;
}
#endif
*irq_flags_ptr = IRQF_TRIGGER_FALLING;
if (dhd_oob_gpio_num < 0) {
WL_ERROR(("%s: ERROR customer specific Host GPIO is NOT defined \n",
__FUNCTION__));
return (dhd_oob_gpio_num);
}
WL_ERROR(("%s: customer specific Host GPIO number is (%d)\n",
__FUNCTION__, dhd_oob_gpio_num));
#if defined CUSTOMER_HW
host_oob_irq = MSM_GPIO_TO_INT(dhd_oob_gpio_num);
#elif defined CUSTOMER_HW3
gpio_request(dhd_oob_gpio_num, "oob irq");
host_oob_irq = gpio_to_irq(dhd_oob_gpio_num);
gpio_direction_input(dhd_oob_gpio_num);
#endif /* CUSTOMER_HW */
#endif /* CUSTOMER_HW2 */
return (host_oob_irq);
}
#endif /* defined(OOB_INTR_ONLY) */
/* Customer function to control hw specific wlan gpios */
void
dhd_customer_gpio_wlan_ctrl(int onoff)
{
switch (onoff) {
case WLAN_RESET_OFF:
WL_TRACE(("%s: call customer specific GPIO to insert WLAN RESET\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_off(2);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
wifi_set_power(0, 0);
#endif
WL_ERROR(("=========== WLAN placed in RESET ========\n"));
break;
case WLAN_RESET_ON:
WL_TRACE(("%s: callc customer specific GPIO to remove WLAN RESET\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_on(2);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
wifi_set_power(1, 0);
#endif
WL_ERROR(("=========== WLAN going back to live ========\n"));
break;
case WLAN_POWER_OFF:
WL_TRACE(("%s: call customer specific GPIO to turn off WL_REG_ON\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_off(1);
#endif /* CUSTOMER_HW */
break;
case WLAN_POWER_ON:
WL_TRACE(("%s: call customer specific GPIO to turn on WL_REG_ON\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_on(1);
#endif /* CUSTOMER_HW */
/* Lets customer power to get stable */
OSL_DELAY(500);
break;
}
}
#ifdef GET_CUSTOM_MAC_ENABLE
/* Function to get custom MAC address */
int
dhd_custom_get_mac_address(unsigned char *buf)
{
WL_TRACE(("%s Enter\n", __FUNCTION__));
if (!buf)
return -EINVAL;
/* Customer access to MAC address stored outside of DHD driver */
#ifdef EXAMPLE_GET_MAC
/* EXAMPLE code */
{
struct ether_addr ea_example = {{0x00, 0x11, 0x22, 0x33, 0x44, 0xFF}};
bcopy((char *)&ea_example, buf, sizeof(struct ether_addr));
}
#endif /* EXAMPLE_GET_MAC */
return 0;
}
#endif /* GET_CUSTOM_MAC_ENABLE */

100
drivers/net/wireless/bcm4329_245/dhd_dbg.h Normal file
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@ -0,0 +1,100 @@
/*
* Debug/trace/assert driver definitions for Dongle Host Driver.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dhd_dbg.h,v 1.5.6.2.4.2.14.10 2010/05/21 21:49:38 Exp $
*/
#ifndef _dhd_dbg_
#define _dhd_dbg_
#if 0 || (defined DHD_DEBUG)
#define DHD_ERROR(args) do {if ((dhd_msg_level & DHD_ERROR_VAL) && (net_ratelimit())) \
printf args;} while (0)
#define DHD_TRACE(args) do {if (dhd_msg_level & DHD_TRACE_VAL) printf args;} while (0)
#define DHD_INFO(args) do {if (dhd_msg_level & DHD_INFO_VAL) printf args;} while (0)
#define DHD_DATA(args) do {if (dhd_msg_level & DHD_DATA_VAL) printf args;} while (0)
#define DHD_CTL(args) do {if (dhd_msg_level & DHD_CTL_VAL) printf args;} while (0)
#define DHD_TIMER(args) do {if (dhd_msg_level & DHD_TIMER_VAL) printf args;} while (0)
#define DHD_HDRS(args) do {if (dhd_msg_level & DHD_HDRS_VAL) printf args;} while (0)
#define DHD_BYTES(args) do {if (dhd_msg_level & DHD_BYTES_VAL) printf args;} while (0)
#define DHD_INTR(args) do {if (dhd_msg_level & DHD_INTR_VAL) printf args;} while (0)
#define DHD_GLOM(args) do {if (dhd_msg_level & DHD_GLOM_VAL) printf args;} while (0)
#define DHD_EVENT(args) do {if (dhd_msg_level & DHD_EVENT_VAL) printf args;} while (0)
#define DHD_BTA(args) do {if (dhd_msg_level & DHD_BTA_VAL) printf args;} while (0)
#define DHD_ISCAN(args) do {if (dhd_msg_level & DHD_ISCAN_VAL) printf args;} while (0)
#define DHD_ERROR_ON() (dhd_msg_level & DHD_ERROR_VAL)
#define DHD_TRACE_ON() (dhd_msg_level & DHD_TRACE_VAL)
#define DHD_INFO_ON() (dhd_msg_level & DHD_INFO_VAL)
#define DHD_DATA_ON() (dhd_msg_level & DHD_DATA_VAL)
#define DHD_CTL_ON() (dhd_msg_level & DHD_CTL_VAL)
#define DHD_TIMER_ON() (dhd_msg_level & DHD_TIMER_VAL)
#define DHD_HDRS_ON() (dhd_msg_level & DHD_HDRS_VAL)
#define DHD_BYTES_ON() (dhd_msg_level & DHD_BYTES_VAL)
#define DHD_INTR_ON() (dhd_msg_level & DHD_INTR_VAL)
#define DHD_GLOM_ON() (dhd_msg_level & DHD_GLOM_VAL)
#define DHD_EVENT_ON() (dhd_msg_level & DHD_EVENT_VAL)
#define DHD_BTA_ON() (dhd_msg_level & DHD_BTA_VAL)
#define DHD_ISCAN_ON() (dhd_msg_level & DHD_ISCAN_VAL)
#else /* (defined BCMDBG) || (defined DHD_DEBUG) */
#define DHD_ERROR(args) do {if (net_ratelimit()) printf args;} while (0)
#define DHD_TRACE(args)
#define DHD_INFO(args)
#define DHD_DATA(args)
#define DHD_CTL(args)
#define DHD_TIMER(args)
#define DHD_HDRS(args)
#define DHD_BYTES(args)
#define DHD_INTR(args)
#define DHD_GLOM(args)
#define DHD_EVENT(args)
#define DHD_BTA(args)
#define DHD_ISCAN(args)
#define DHD_ERROR_ON() 0
#define DHD_TRACE_ON() 0
#define DHD_INFO_ON() 0
#define DHD_DATA_ON() 0
#define DHD_CTL_ON() 0
#define DHD_TIMER_ON() 0
#define DHD_HDRS_ON() 0
#define DHD_BYTES_ON() 0
#define DHD_INTR_ON() 0
#define DHD_GLOM_ON() 0
#define DHD_EVENT_ON() 0
#define DHD_BTA_ON() 0
#define DHD_ISCAN_ON() 0
#endif
#define DHD_LOG(args)
#define DHD_NONE(args)
extern int dhd_msg_level;
/* Defines msg bits */
#include <dhdioctl.h>
#endif /* _dhd_dbg_ */

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/*
* Expose some of the kernel scheduler routines
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dhd_linux_sched.c,v 1.1.34.1.6.1 2009/01/16 01:17:40 Exp $
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linuxver.h>
int setScheduler(struct task_struct *p, int policy, struct sched_param *param)
{
int rc = 0;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
rc = sched_setscheduler(p, policy, param);
#endif /* LinuxVer */
return rc;
}

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/*
* Header file describing the internal (inter-module) DHD interfaces.
*
* Provides type definitions and function prototypes used to link the
* DHD OS, bus, and protocol modules.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dhd_proto.h,v 1.2.82.1.4.1.16.7 2010/05/10 12:54:59 Exp $
*/
#ifndef _dhd_proto_h_
#define _dhd_proto_h_
#include <dhdioctl.h>
#include <wlioctl.h>
#ifndef IOCTL_RESP_TIMEOUT
#define IOCTL_RESP_TIMEOUT 2000 /* In milli second */
#endif
#ifndef IOCTL_CHIP_ACTIVE_TIMEOUT
#define IOCTL_CHIP_ACTIVE_TIMEOUT 10 /* In milli second */
#endif
/*
* Exported from the dhd protocol module (dhd_cdc, dhd_rndis)
*/
/* Linkage, sets prot link and updates hdrlen in pub */
extern int dhd_prot_attach(dhd_pub_t *dhdp);
/* Unlink, frees allocated protocol memory (including dhd_prot) */
extern void dhd_prot_detach(dhd_pub_t *dhdp);
/* Initialize protocol: sync w/dongle state.
* Sets dongle media info (iswl, drv_version, mac address).
*/
extern int dhd_prot_init(dhd_pub_t *dhdp);
/* Stop protocol: sync w/dongle state. */
extern void dhd_prot_stop(dhd_pub_t *dhdp);
extern bool dhd_proto_fcinfo(dhd_pub_t *dhd, void *pktbuf, uint8 *fcbits);
/* Add any protocol-specific data header.
* Caller must reserve prot_hdrlen prepend space.
*/
extern void dhd_prot_hdrpush(dhd_pub_t *, int ifidx, void *txp);
/* Remove any protocol-specific data header. */
extern int dhd_prot_hdrpull(dhd_pub_t *, int *ifidx, void *rxp);
/* Use protocol to issue ioctl to dongle */
extern int dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t * ioc, void * buf, int len);
/* Check for and handle local prot-specific iovar commands */
extern int dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
void *params, int plen, void *arg, int len, bool set);
/* Add prot dump output to a buffer */
extern void dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
/* Update local copy of dongle statistics */
extern void dhd_prot_dstats(dhd_pub_t *dhdp);
extern int dhd_ioctl(dhd_pub_t * dhd_pub, dhd_ioctl_t *ioc, void * buf, uint buflen);
extern int dhd_preinit_ioctls(dhd_pub_t *dhd);
/********************************
* For version-string expansion *
*/
#if defined(BDC)
#define DHD_PROTOCOL "bdc"
#elif defined(CDC)
#define DHD_PROTOCOL "cdc"
#elif defined(RNDIS)
#define DHD_PROTOCOL "rndis"
#else
#define DHD_PROTOCOL "unknown"
#endif /* proto */
#endif /* _dhd_proto_h_ */

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/*
* Common stats definitions for clients of dongle
* ports
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dngl_stats.h,v 1.2.140.3 2008/05/26 16:52:08 Exp $
*/
#ifndef _dngl_stats_h_
#define _dngl_stats_h_
typedef struct {
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* packets dropped by dongle */
unsigned long tx_dropped; /* packets dropped by dongle */
unsigned long multicast; /* multicast packets received */
} dngl_stats_t;
#endif /* _dngl_stats_h_ */

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/*
* Misc utility routines for accessing PMU corerev specific features
* of the SiliconBackplane-based Broadcom chips.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: hndpmu.c,v 1.95.2.17.4.11.2.63 2010/07/21 13:55:09 Exp $
*/
#include <typedefs.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <siutils.h>
#include <bcmdevs.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <hndpmu.h>
/* debug/trace */
#define PMU_ERROR(args)
#define PMU_MSG(args)
/* SDIO Pad drive strength to select value mappings */
typedef struct {
uint8 strength; /* Pad Drive Strength in mA */
uint8 sel; /* Chip-specific select value */
} sdiod_drive_str_t;
/* SDIO Drive Strength to sel value table for PMU Rev 1 */
static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = {
{4, 0x2},
{2, 0x3},
{1, 0x0},
{0, 0x0} };
/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = {
{12, 0x7},
{10, 0x6},
{8, 0x5},
{6, 0x4},
{4, 0x2},
{2, 0x1},
{0, 0x0} };
#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
void
si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength)
{
chipcregs_t *cc;
uint origidx, intr_val = 0;
sdiod_drive_str_t *str_tab = NULL;
uint32 str_mask = 0;
uint32 str_shift = 0;
if (!(sih->cccaps & CC_CAP_PMU)) {
return;
}
/* Remember original core before switch to chipc */
cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) {
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1;
str_mask = 0x30000000;
str_shift = 28;
break;
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
case SDIOD_DRVSTR_KEY(BCM4315_CHIP_ID, 4):
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2;
str_mask = 0x00003800;
str_shift = 11;
break;
default:
PMU_MSG(("No SDIO Drive strength init done for chip %x rev %d pmurev %d\n",
sih->chip, sih->chiprev, sih->pmurev));
break;
}
if (str_tab != NULL) {
uint32 drivestrength_sel = 0;
uint32 cc_data_temp;
int i;
for (i = 0; str_tab[i].strength != 0; i ++) {
if (drivestrength >= str_tab[i].strength) {
drivestrength_sel = str_tab[i].sel;
break;
}
}
W_REG(osh, &cc->chipcontrol_addr, 1);
cc_data_temp = R_REG(osh, &cc->chipcontrol_data);
cc_data_temp &= ~str_mask;
drivestrength_sel <<= str_shift;
cc_data_temp |= drivestrength_sel;
W_REG(osh, &cc->chipcontrol_data, cc_data_temp);
PMU_MSG(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
drivestrength, cc_data_temp));
}
/* Return to original core */
si_restore_core(sih, origidx, intr_val);
}

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#
# include/Makefile
#
# Copyright 2005, Broadcom, Inc.
#
# $Id: Makefile,v 13.5 2005/02/17 19:11:31 Exp $
#
SRCBASE = ..
TARGETS = epivers.h
all release:
bash epivers.sh
clean:
rm -rf ${TARGETS} *.prev
.PHONY: all release clean

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/*
* Broadcom AMBA Interconnect definitions.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: aidmp.h,v 13.2.10.1 2008/05/07 20:32:12 Exp $
*/
#ifndef _AIDMP_H
#define _AIDMP_H
#define MFGID_ARM 0x43b
#define MFGID_BRCM 0x4bf
#define MFGID_MIPS 0x4a7
#define CC_SIM 0
#define CC_EROM 1
#define CC_CORESIGHT 9
#define CC_VERIF 0xb
#define CC_OPTIMO 0xd
#define CC_GEN 0xe
#define CC_PRIMECELL 0xf
#define ER_EROMENTRY 0x000
#define ER_REMAPCONTROL 0xe00
#define ER_REMAPSELECT 0xe04
#define ER_MASTERSELECT 0xe10
#define ER_ITCR 0xf00
#define ER_ITIP 0xf04
#define ER_TAG 0xe
#define ER_TAG1 0x6
#define ER_VALID 1
#define ER_CI 0
#define ER_MP 2
#define ER_ADD 4
#define ER_END 0xe
#define ER_BAD 0xffffffff
#define CIA_MFG_MASK 0xfff00000
#define CIA_MFG_SHIFT 20
#define CIA_CID_MASK 0x000fff00
#define CIA_CID_SHIFT 8
#define CIA_CCL_MASK 0x000000f0
#define CIA_CCL_SHIFT 4
#define CIB_REV_MASK 0xff000000
#define CIB_REV_SHIFT 24
#define CIB_NSW_MASK 0x00f80000
#define CIB_NSW_SHIFT 19
#define CIB_NMW_MASK 0x0007c000
#define CIB_NMW_SHIFT 14
#define CIB_NSP_MASK 0x00003e00
#define CIB_NSP_SHIFT 9
#define CIB_NMP_MASK 0x000001f0
#define CIB_NMP_SHIFT 4
#define MPD_MUI_MASK 0x0000ff00
#define MPD_MUI_SHIFT 8
#define MPD_MP_MASK 0x000000f0
#define MPD_MP_SHIFT 4
#define AD_ADDR_MASK 0xfffff000
#define AD_SP_MASK 0x00000f00
#define AD_SP_SHIFT 8
#define AD_ST_MASK 0x000000c0
#define AD_ST_SHIFT 6
#define AD_ST_SLAVE 0x00000000
#define AD_ST_BRIDGE 0x00000040
#define AD_ST_SWRAP 0x00000080
#define AD_ST_MWRAP 0x000000c0
#define AD_SZ_MASK 0x00000030
#define AD_SZ_SHIFT 4
#define AD_SZ_4K 0x00000000
#define AD_SZ_8K 0x00000010
#define AD_SZ_16K 0x00000020
#define AD_SZ_SZD 0x00000030
#define AD_AG32 0x00000008
#define AD_ADDR_ALIGN 0x00000fff
#define AD_SZ_BASE 0x00001000
#define SD_SZ_MASK 0xfffff000
#define SD_SG32 0x00000008
#define SD_SZ_ALIGN 0x00000fff
#ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _aidmp {
uint32 oobselina30;
uint32 oobselina74;
uint32 PAD[6];
uint32 oobselinb30;
uint32 oobselinb74;
uint32 PAD[6];
uint32 oobselinc30;
uint32 oobselinc74;
uint32 PAD[6];
uint32 oobselind30;
uint32 oobselind74;
uint32 PAD[38];
uint32 oobselouta30;
uint32 oobselouta74;
uint32 PAD[6];
uint32 oobseloutb30;
uint32 oobseloutb74;
uint32 PAD[6];
uint32 oobseloutc30;
uint32 oobseloutc74;
uint32 PAD[6];
uint32 oobseloutd30;
uint32 oobseloutd74;
uint32 PAD[38];
uint32 oobsynca;
uint32 oobseloutaen;
uint32 PAD[6];
uint32 oobsyncb;
uint32 oobseloutben;
uint32 PAD[6];
uint32 oobsyncc;
uint32 oobseloutcen;
uint32 PAD[6];
uint32 oobsyncd;
uint32 oobseloutden;
uint32 PAD[38];
uint32 oobaextwidth;
uint32 oobainwidth;
uint32 oobaoutwidth;
uint32 PAD[5];
uint32 oobbextwidth;
uint32 oobbinwidth;
uint32 oobboutwidth;
uint32 PAD[5];
uint32 oobcextwidth;
uint32 oobcinwidth;
uint32 oobcoutwidth;
uint32 PAD[5];
uint32 oobdextwidth;
uint32 oobdinwidth;
uint32 oobdoutwidth;
uint32 PAD[37];
uint32 ioctrlset;
uint32 ioctrlclear;
uint32 ioctrl;
uint32 PAD[61];
uint32 iostatus;
uint32 PAD[127];
uint32 ioctrlwidth;
uint32 iostatuswidth;
uint32 PAD[62];
uint32 resetctrl;
uint32 resetstatus;
uint32 resetreadid;
uint32 resetwriteid;
uint32 PAD[60];
uint32 errlogctrl;
uint32 errlogdone;
uint32 errlogstatus;
uint32 errlogaddrlo;
uint32 errlogaddrhi;
uint32 errlogid;
uint32 errloguser;
uint32 errlogflags;
uint32 PAD[56];
uint32 intstatus;
uint32 PAD[127];
uint32 config;
uint32 PAD[63];
uint32 itcr;
uint32 PAD[3];
uint32 itipooba;
uint32 itipoobb;
uint32 itipoobc;
uint32 itipoobd;
uint32 PAD[4];
uint32 itipoobaout;
uint32 itipoobbout;
uint32 itipoobcout;
uint32 itipoobdout;
uint32 PAD[4];
uint32 itopooba;
uint32 itopoobb;
uint32 itopoobc;
uint32 itopoobd;
uint32 PAD[4];
uint32 itopoobain;
uint32 itopoobbin;
uint32 itopoobcin;
uint32 itopoobdin;
uint32 PAD[4];
uint32 itopreset;
uint32 PAD[15];
uint32 peripherialid4;
uint32 peripherialid5;
uint32 peripherialid6;
uint32 peripherialid7;
uint32 peripherialid0;
uint32 peripherialid1;
uint32 peripherialid2;
uint32 peripherialid3;
uint32 componentid0;
uint32 componentid1;
uint32 componentid2;
uint32 componentid3;
} aidmp_t;
#endif
#define OOB_BUSCONFIG 0x020
#define OOB_STATUSA 0x100
#define OOB_STATUSB 0x104
#define OOB_STATUSC 0x108
#define OOB_STATUSD 0x10c
#define OOB_ENABLEA0 0x200
#define OOB_ENABLEA1 0x204
#define OOB_ENABLEA2 0x208
#define OOB_ENABLEA3 0x20c
#define OOB_ENABLEB0 0x280
#define OOB_ENABLEB1 0x284
#define OOB_ENABLEB2 0x288
#define OOB_ENABLEB3 0x28c
#define OOB_ENABLEC0 0x300
#define OOB_ENABLEC1 0x304
#define OOB_ENABLEC2 0x308
#define OOB_ENABLEC3 0x30c
#define OOB_ENABLED0 0x380
#define OOB_ENABLED1 0x384
#define OOB_ENABLED2 0x388
#define OOB_ENABLED3 0x38c
#define OOB_ITCR 0xf00
#define OOB_ITIPOOBA 0xf10
#define OOB_ITIPOOBB 0xf14
#define OOB_ITIPOOBC 0xf18
#define OOB_ITIPOOBD 0xf1c
#define OOB_ITOPOOBA 0xf30
#define OOB_ITOPOOBB 0xf34
#define OOB_ITOPOOBC 0xf38
#define OOB_ITOPOOBD 0xf3c
#define AI_OOBSELINA30 0x000
#define AI_OOBSELINA74 0x004
#define AI_OOBSELINB30 0x020
#define AI_OOBSELINB74 0x024
#define AI_OOBSELINC30 0x040
#define AI_OOBSELINC74 0x044
#define AI_OOBSELIND30 0x060
#define AI_OOBSELIND74 0x064
#define AI_OOBSELOUTA30 0x100
#define AI_OOBSELOUTA74 0x104
#define AI_OOBSELOUTB30 0x120
#define AI_OOBSELOUTB74 0x124
#define AI_OOBSELOUTC30 0x140
#define AI_OOBSELOUTC74 0x144
#define AI_OOBSELOUTD30 0x160
#define AI_OOBSELOUTD74 0x164
#define AI_OOBSYNCA 0x200
#define AI_OOBSELOUTAEN 0x204
#define AI_OOBSYNCB 0x220
#define AI_OOBSELOUTBEN 0x224
#define AI_OOBSYNCC 0x240
#define AI_OOBSELOUTCEN 0x244
#define AI_OOBSYNCD 0x260
#define AI_OOBSELOUTDEN 0x264
#define AI_OOBAEXTWIDTH 0x300
#define AI_OOBAINWIDTH 0x304
#define AI_OOBAOUTWIDTH 0x308
#define AI_OOBBEXTWIDTH 0x320
#define AI_OOBBINWIDTH 0x324
#define AI_OOBBOUTWIDTH 0x328
#define AI_OOBCEXTWIDTH 0x340
#define AI_OOBCINWIDTH 0x344
#define AI_OOBCOUTWIDTH 0x348
#define AI_OOBDEXTWIDTH 0x360
#define AI_OOBDINWIDTH 0x364
#define AI_OOBDOUTWIDTH 0x368
#define AI_IOCTRLSET 0x400
#define AI_IOCTRLCLEAR 0x404
#define AI_IOCTRL 0x408
#define AI_IOSTATUS 0x500
#define AI_IOCTRLWIDTH 0x700
#define AI_IOSTATUSWIDTH 0x704
#define AI_RESETCTRL 0x800
#define AI_RESETSTATUS 0x804
#define AI_RESETREADID 0x808
#define AI_RESETWRITEID 0x80c
#define AI_ERRLOGCTRL 0xa00
#define AI_ERRLOGDONE 0xa04
#define AI_ERRLOGSTATUS 0xa08
#define AI_ERRLOGADDRLO 0xa0c
#define AI_ERRLOGADDRHI 0xa10
#define AI_ERRLOGID 0xa14
#define AI_ERRLOGUSER 0xa18
#define AI_ERRLOGFLAGS 0xa1c
#define AI_INTSTATUS 0xa00
#define AI_CONFIG 0xe00
#define AI_ITCR 0xf00
#define AI_ITIPOOBA 0xf10
#define AI_ITIPOOBB 0xf14
#define AI_ITIPOOBC 0xf18
#define AI_ITIPOOBD 0xf1c
#define AI_ITIPOOBAOUT 0xf30
#define AI_ITIPOOBBOUT 0xf34
#define AI_ITIPOOBCOUT 0xf38
#define AI_ITIPOOBDOUT 0xf3c
#define AI_ITOPOOBA 0xf50
#define AI_ITOPOOBB 0xf54
#define AI_ITOPOOBC 0xf58
#define AI_ITOPOOBD 0xf5c
#define AI_ITOPOOBAIN 0xf70
#define AI_ITOPOOBBIN 0xf74
#define AI_ITOPOOBCIN 0xf78
#define AI_ITOPOOBDIN 0xf7c
#define AI_ITOPRESET 0xf90
#define AI_PERIPHERIALID4 0xfd0
#define AI_PERIPHERIALID5 0xfd4
#define AI_PERIPHERIALID6 0xfd8
#define AI_PERIPHERIALID7 0xfdc
#define AI_PERIPHERIALID0 0xfe0
#define AI_PERIPHERIALID1 0xfe4
#define AI_PERIPHERIALID2 0xfe8
#define AI_PERIPHERIALID3 0xfec
#define AI_COMPONENTID0 0xff0
#define AI_COMPONENTID1 0xff4
#define AI_COMPONENTID2 0xff8
#define AI_COMPONENTID3 0xffc
#define AIRC_RESET 1
#define AICFG_OOB 0x00000020
#define AICFG_IOS 0x00000010
#define AICFG_IOC 0x00000008
#define AICFG_TO 0x00000004
#define AICFG_ERRL 0x00000002
#define AICFG_RST 0x00000001
#endif

100
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/*
* CDC network driver ioctl/indication encoding
* Broadcom 802.11abg Networking Device Driver
*
* Definitions subject to change without notice.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmcdc.h,v 13.14.16.3.16.4 2009/04/12 16:58:45 Exp $
*/
#include <proto/ethernet.h>
typedef struct cdc_ioctl {
uint32 cmd; /* ioctl command value */
uint32 len; /* lower 16: output buflen; upper 16: input buflen (excludes header) */
uint32 flags; /* flag defns given below */
uint32 status; /* status code returned from the device */
} cdc_ioctl_t;
/* Max valid buffer size that can be sent to the dongle */
#define CDC_MAX_MSG_SIZE ETHER_MAX_LEN
/* len field is divided into input and output buffer lengths */
#define CDCL_IOC_OUTLEN_MASK 0x0000FFFF /* maximum or expected response length, */
/* excluding IOCTL header */
#define CDCL_IOC_OUTLEN_SHIFT 0
#define CDCL_IOC_INLEN_MASK 0xFFFF0000 /* input buffer length, excluding IOCTL header */
#define CDCL_IOC_INLEN_SHIFT 16
/* CDC flag definitions */
#define CDCF_IOC_ERROR 0x01 /* 0=success, 1=ioctl cmd failed */
#define CDCF_IOC_SET 0x02 /* 0=get, 1=set cmd */
#define CDCF_IOC_IF_MASK 0xF000 /* I/F index */
#define CDCF_IOC_IF_SHIFT 12
#define CDCF_IOC_ID_MASK 0xFFFF0000 /* used to uniquely id an ioctl req/resp pairing */
#define CDCF_IOC_ID_SHIFT 16 /* # of bits of shift for ID Mask */
#define CDC_IOC_IF_IDX(flags) (((flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT)
#define CDC_IOC_ID(flags) (((flags) & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT)
#define CDC_GET_IF_IDX(hdr) \
((int)((((hdr)->flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT))
#define CDC_SET_IF_IDX(hdr, idx) \
((hdr)->flags = (((hdr)->flags & ~CDCF_IOC_IF_MASK) | ((idx) << CDCF_IOC_IF_SHIFT)))
/*
* BDC header
*
* The BDC header is used on data packets to convey priority across USB.
*/
#define BDC_HEADER_LEN 4
#define BDC_PROTO_VER 1 /* Protocol version */
#define BDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */
#define BDC_FLAG_VER_SHIFT 4 /* Protocol version shift */
#define BDC_FLAG__UNUSED 0x03 /* Unassigned */
#define BDC_FLAG_SUM_GOOD 0x04 /* Dongle has verified good RX checksums */
#define BDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */
#define BDC_PRIORITY_MASK 0x7
#define BDC_FLAG2_FC_FLAG 0x10 /* flag to indicate if pkt contains */
/* FLOW CONTROL info only */
#define BDC_PRIORITY_FC_SHIFT 4 /* flow control info shift */
#define BDC_FLAG2_IF_MASK 0x0f /* APSTA: interface on which the packet was received */
#define BDC_FLAG2_IF_SHIFT 0
#define BDC_GET_IF_IDX(hdr) \
((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT))
#define BDC_SET_IF_IDX(hdr, idx) \
((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | ((idx) << BDC_FLAG2_IF_SHIFT)))
struct bdc_header {
uint8 flags; /* Flags */
uint8 priority; /* 802.1d Priority 0:2 bits, 4:7 flow control info for usb */
uint8 flags2;
uint8 rssi;
};

115
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/*
* Misc system wide definitions
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: bcmdefs.h,v 13.38.4.10.2.7.6.11 2010/02/01 05:51:55 Exp $
*/
#ifndef _bcmdefs_h_
#define _bcmdefs_h_
#define STATIC static
#define SI_BUS 0
#define PCI_BUS 1
#define PCMCIA_BUS 2
#define SDIO_BUS 3
#define JTAG_BUS 4
#define USB_BUS 5
#define SPI_BUS 6
#ifdef BCMBUSTYPE
#define BUSTYPE(bus) (BCMBUSTYPE)
#else
#define BUSTYPE(bus) (bus)
#endif
#ifdef BCMCHIPTYPE
#define CHIPTYPE(bus) (BCMCHIPTYPE)
#else
#define CHIPTYPE(bus) (bus)
#endif
#if defined(BCMSPROMBUS)
#define SPROMBUS (BCMSPROMBUS)
#elif defined(SI_PCMCIA_SROM)
#define SPROMBUS (PCMCIA_BUS)
#else
#define SPROMBUS (PCI_BUS)
#endif
#ifdef BCMCHIPID
#define CHIPID(chip) (BCMCHIPID)
#else
#define CHIPID(chip) (chip)
#endif
#define DMADDR_MASK_32 0x0
#define DMADDR_MASK_30 0xc0000000
#define DMADDR_MASK_0 0xffffffff
#define DMADDRWIDTH_30 30
#define DMADDRWIDTH_32 32
#define DMADDRWIDTH_63 63
#define DMADDRWIDTH_64 64
#define BCMEXTRAHDROOM 164
#define BCMDONGLEHDRSZ 12
#define BCMDONGLEPADSZ 16
#define BCMDONGLEOVERHEAD (BCMDONGLEHDRSZ + BCMDONGLEPADSZ)
#define BITFIELD_MASK(width) \
(((unsigned)1 << (width)) - 1)
#define GFIELD(val, field) \
(((val) >> field ## _S) & field ## _M)
#define SFIELD(val, field, bits) \
(((val) & (~(field ## _M << field ## _S))) | \
((unsigned)(bits) << field ## _S))
#ifdef BCMSMALL
#undef BCMSPACE
#define bcmspace FALSE
#else
#define BCMSPACE
#define bcmspace TRUE
#endif
#define MAXSZ_NVRAM_VARS 4096
#define LOCATOR_EXTERN static
#endif

124
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/*
* Broadcom device-specific manifest constants.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmdevs.h,v 13.172.4.5.4.10.2.36 2010/05/25 08:33:44 Exp $
*/
#ifndef _BCMDEVS_H
#define _BCMDEVS_H
#define VENDOR_EPIGRAM 0xfeda
#define VENDOR_BROADCOM 0x14e4
#define VENDOR_SI_IMAGE 0x1095
#define VENDOR_TI 0x104c
#define VENDOR_RICOH 0x1180
#define VENDOR_JMICRON 0x197b
#define VENDOR_BROADCOM_PCMCIA 0x02d0
#define VENDOR_BROADCOM_SDIO 0x00BF
#define BCM_DNGL_VID 0xa5c
#define BCM_DNGL_BL_PID_4320 0xbd11
#define BCM_DNGL_BL_PID_4328 0xbd12
#define BCM_DNGL_BL_PID_4322 0xbd13
#define BCM_DNGL_BL_PID_4325 0xbd14
#define BCM_DNGL_BL_PID_4315 0xbd15
#define BCM_DNGL_BL_PID_4319 0xbd16
#define BCM_DNGL_BDC_PID 0xbdc
#define BCM4325_D11DUAL_ID 0x431b
#define BCM4325_D11G_ID 0x431c
#define BCM4325_D11A_ID 0x431d
#define BCM4329_D11NDUAL_ID 0x432e
#define BCM4329_D11N2G_ID 0x432f
#define BCM4329_D11N5G_ID 0x4330
#define BCM4336_D11N_ID 0x4343
#define BCM4315_D11DUAL_ID 0x4334
#define BCM4315_D11G_ID 0x4335
#define BCM4315_D11A_ID 0x4336
#define BCM4319_D11N_ID 0x4337
#define BCM4319_D11N2G_ID 0x4338
#define BCM4319_D11N5G_ID 0x4339
#define SDIOH_FPGA_ID 0x43f2
#define SPIH_FPGA_ID 0x43f5
#define BCM4710_DEVICE_ID 0x4710
#define BCM27XX_SDIOH_ID 0x2702
#define PCIXX21_FLASHMEDIA0_ID 0x8033
#define PCIXX21_SDIOH0_ID 0x8034
#define PCIXX21_FLASHMEDIA_ID 0x803b
#define PCIXX21_SDIOH_ID 0x803c
#define R5C822_SDIOH_ID 0x0822
#define JMICRON_SDIOH_ID 0x2381
#define BCM4306_CHIP_ID 0x4306
#define BCM4311_CHIP_ID 0x4311
#define BCM4312_CHIP_ID 0x4312
#define BCM4315_CHIP_ID 0x4315
#define BCM4318_CHIP_ID 0x4318
#define BCM4319_CHIP_ID 0x4319
#define BCM4320_CHIP_ID 0x4320
#define BCM4321_CHIP_ID 0x4321
#define BCM4322_CHIP_ID 0x4322
#define BCM4325_CHIP_ID 0x4325
#define BCM4328_CHIP_ID 0x4328
#define BCM4329_CHIP_ID 0x4329
#define BCM4336_CHIP_ID 0x4336
#define BCM4402_CHIP_ID 0x4402
#define BCM4704_CHIP_ID 0x4704
#define BCM4710_CHIP_ID 0x4710
#define BCM4712_CHIP_ID 0x4712
#define BCM4785_CHIP_ID 0x4785
#define BCM5350_CHIP_ID 0x5350
#define BCM5352_CHIP_ID 0x5352
#define BCM5354_CHIP_ID 0x5354
#define BCM5365_CHIP_ID 0x5365
#define BCM4303_PKG_ID 2
#define BCM4309_PKG_ID 1
#define BCM4712LARGE_PKG_ID 0
#define BCM4712SMALL_PKG_ID 1
#define BCM4712MID_PKG_ID 2
#define BCM4328USBD11G_PKG_ID 2
#define BCM4328USBDUAL_PKG_ID 3
#define BCM4328SDIOD11G_PKG_ID 4
#define BCM4328SDIODUAL_PKG_ID 5
#define BCM4329_289PIN_PKG_ID 0
#define BCM4329_182PIN_PKG_ID 1
#define BCM5354E_PKG_ID 1
#define HDLSIM5350_PKG_ID 1
#define HDLSIM_PKG_ID 14
#define HWSIM_PKG_ID 15
#endif

205
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/*
* Byte order utilities
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmendian.h,v 1.31.302.1.16.1 2009/02/03 18:34:31 Exp $
*
* This file by default provides proper behavior on little-endian architectures.
* On big-endian architectures, IL_BIGENDIAN should be defined.
*/
#ifndef _BCMENDIAN_H_
#define _BCMENDIAN_H_
#include <typedefs.h>
#define BCMSWAP16(val) \
((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \
(((uint16)(val) & (uint16)0xff00U) >> 8)))
#define BCMSWAP32(val) \
((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
(((uint32)(val) & (uint32)0x0000ff00U) << 8) | \
(((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \
(((uint32)(val) & (uint32)0xff000000U) >> 24)))
#define BCMSWAP32BY16(val) \
((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \
(((uint32)(val) & (uint32)0xffff0000U) >> 16)))
static INLINE uint16
bcmswap16(uint16 val)
{
return BCMSWAP16(val);
}
static INLINE uint32
bcmswap32(uint32 val)
{
return BCMSWAP32(val);
}
static INLINE uint32
bcmswap32by16(uint32 val)
{
return BCMSWAP32BY16(val);
}
static INLINE void
bcmswap16_buf(uint16 *buf, uint len)
{
len = len / 2;
while (len--) {
*buf = bcmswap16(*buf);
buf++;
}
}
#ifndef hton16
#ifndef IL_BIGENDIAN
#define HTON16(i) BCMSWAP16(i)
#define HTON32(i) BCMSWAP32(i)
#define hton16(i) bcmswap16(i)
#define hton32(i) bcmswap32(i)
#define ntoh16(i) bcmswap16(i)
#define ntoh32(i) bcmswap32(i)
#define HTOL16(i) (i)
#define HTOL32(i) (i)
#define ltoh16(i) (i)
#define ltoh32(i) (i)
#define htol16(i) (i)
#define htol32(i) (i)
#else
#define HTON16(i) (i)
#define HTON32(i) (i)
#define hton16(i) (i)
#define hton32(i) (i)
#define ntoh16(i) (i)
#define ntoh32(i) (i)
#define HTOL16(i) BCMSWAP16(i)
#define HTOL32(i) BCMSWAP32(i)
#define ltoh16(i) bcmswap16(i)
#define ltoh32(i) bcmswap32(i)
#define htol16(i) bcmswap16(i)
#define htol32(i) bcmswap32(i)
#endif
#endif
#ifndef IL_BIGENDIAN
#define ltoh16_buf(buf, i)
#define htol16_buf(buf, i)
#else
#define ltoh16_buf(buf, i) bcmswap16_buf((uint16 *)buf, i)
#define htol16_buf(buf, i) bcmswap16_buf((uint16 *)buf, i)
#endif
static INLINE void
htol16_ua_store(uint16 val, uint8 *bytes)
{
bytes[0] = val & 0xff;
bytes[1] = val >> 8;
}
static INLINE void
htol32_ua_store(uint32 val, uint8 *bytes)
{
bytes[0] = val & 0xff;
bytes[1] = (val >> 8) & 0xff;
bytes[2] = (val >> 16) & 0xff;
bytes[3] = val >> 24;
}
static INLINE void
hton16_ua_store(uint16 val, uint8 *bytes)
{
bytes[0] = val >> 8;
bytes[1] = val & 0xff;
}
static INLINE void
hton32_ua_store(uint32 val, uint8 *bytes)
{
bytes[0] = val >> 24;
bytes[1] = (val >> 16) & 0xff;
bytes[2] = (val >> 8) & 0xff;
bytes[3] = val & 0xff;
}
#define _LTOH16_UA(cp) ((cp)[0] | ((cp)[1] << 8))
#define _LTOH32_UA(cp) ((cp)[0] | ((cp)[1] << 8) | ((cp)[2] << 16) | ((cp)[3] << 24))
#define _NTOH16_UA(cp) (((cp)[0] << 8) | (cp)[1])
#define _NTOH32_UA(cp) (((cp)[0] << 24) | ((cp)[1] << 16) | ((cp)[2] << 8) | (cp)[3])
static INLINE uint16
ltoh16_ua(const void *bytes)
{
return _LTOH16_UA((const uint8 *)bytes);
}
static INLINE uint32
ltoh32_ua(const void *bytes)
{
return _LTOH32_UA((const uint8 *)bytes);
}
static INLINE uint16
ntoh16_ua(const void *bytes)
{
return _NTOH16_UA((const uint8 *)bytes);
}
static INLINE uint32
ntoh32_ua(const void *bytes)
{
return _NTOH32_UA((const uint8 *)bytes);
}
#define ltoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)ptr : \
sizeof(*(ptr)) == sizeof(uint16) ? _LTOH16_UA((const uint8 *)ptr) : \
sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const uint8 *)ptr) : \
0xfeedf00d)
#define ntoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)ptr : \
sizeof(*(ptr)) == sizeof(uint16) ? _NTOH16_UA((const uint8 *)ptr) : \
sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const uint8 *)ptr) : \
0xfeedf00d)
#endif

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/*
* Broadcom PCI-SPI Host Controller Register Definitions
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmpcispi.h,v 13.11.8.3 2008/07/09 21:23:29 Exp $
*/
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
/*
+---------------------------------------------------------------------------+
| |
| 7 6 5 4 3 2 1 0 |
| 0x0000 SPI_CTRL SPIE SPE 0 MSTR CPOL CPHA SPR1 SPR0 |
| 0x0004 SPI_STAT SPIF WCOL ST1 ST0 WFFUL WFEMP RFFUL RFEMP |
| 0x0008 SPI_DATA Bits 31:0, data to send out on MOSI |
| 0x000C SPI_EXT ICNT1 ICNT0 BSWAP *HSMODE ESPR1 ESPR0 |
| 0x0020 GPIO_OE 0=input, 1=output PWR_OE CS_OE |
| 0x0024 GPIO_DATA CARD:1=missing, 0=present CARD PWR_DAT CS_DAT |
| 0x0040 INT_EDGE 0=level, 1=edge DEV_E SPI_E |
| 0x0044 INT_POL 1=active high, 0=active low DEV_P SPI_P |
| 0x0048 INTMASK DEV SPI |
| 0x004C INTSTATUS DEV SPI |
| 0x0060 HEXDISP Reset value: 0x14e443f5. In hexdisp mode, value |
| shows on the Raggedstone1 4-digit 7-segment display. |
| 0x0064 CURRENT_MA Low 16 bits indicate card current consumption in mA |
| 0x006C DISP_SEL Display mode (0=hexdisp, 1=current) DSP |
| 0x00C0 PLL_CTL bit31=ext_clk, remainder unused. |
| 0x00C4 PLL_STAT LOCK |
| 0x00C8 CLK_FREQ |
| 0x00CC CLK_CNT |
| |
| *Notes: HSMODE is not implemented, never set this bit! |
| BSWAP is available in rev >= 8 |
| |
+---------------------------------------------------------------------------+
*/
typedef volatile struct {
uint32 spih_ctrl; /* 0x00 SPI Control Register */
uint32 spih_stat; /* 0x04 SPI Status Register */
uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */
uint32 spih_ext; /* 0x0C SPI Extension Register */
uint32 PAD[4]; /* 0x10-0x1F PADDING */
uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */
uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */
uint32 PAD[6]; /* 0x28-0x3F PADDING */
uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
/* 1=Active High) */
uint32 spih_int_mask; /* 0x48 SPI Interrupt Mask */
uint32 spih_int_status; /* 0x4C SPI Interrupt Status */
uint32 PAD[4]; /* 0x50-0x5F PADDING */
uint32 spih_hex_disp; /* 0x60 SPI 4-digit hex display value */
uint32 spih_current_ma; /* 0x64 SPI SD card current consumption in mA */
uint32 PAD[1]; /* 0x68 PADDING */
uint32 spih_disp_sel; /* 0x6c SPI 4-digit hex display mode select (1=current) */
uint32 PAD[4]; /* 0x70-0x7F PADDING */
uint32 PAD[8]; /* 0x80-0x9F PADDING */
uint32 PAD[8]; /* 0xA0-0xBF PADDING */
uint32 spih_pll_ctrl; /* 0xC0 PLL Control Register */
uint32 spih_pll_status; /* 0xC4 PLL Status Register */
uint32 spih_xtal_freq; /* 0xC8 External Clock Frequency in units of 10000Hz */
uint32 spih_clk_count; /* 0xCC External Clock Count Register */
} spih_regs_t;
typedef volatile struct {
uint32 cfg_space[0x40]; /* 0x000-0x0FF PCI Configuration Space (Read Only) */
uint32 P_IMG_CTRL0; /* 0x100 PCI Image0 Control Register */
uint32 P_BA0; /* 0x104 32 R/W PCI Image0 Base Address register */
uint32 P_AM0; /* 0x108 32 R/W PCI Image0 Address Mask register */
uint32 P_TA0; /* 0x10C 32 R/W PCI Image0 Translation Address register */
uint32 P_IMG_CTRL1; /* 0x110 32 R/W PCI Image1 Control register */
uint32 P_BA1; /* 0x114 32 R/W PCI Image1 Base Address register */
uint32 P_AM1; /* 0x118 32 R/W PCI Image1 Address Mask register */
uint32 P_TA1; /* 0x11C 32 R/W PCI Image1 Translation Address register */
uint32 P_IMG_CTRL2; /* 0x120 32 R/W PCI Image2 Control register */
uint32 P_BA2; /* 0x124 32 R/W PCI Image2 Base Address register */
uint32 P_AM2; /* 0x128 32 R/W PCI Image2 Address Mask register */
uint32 P_TA2; /* 0x12C 32 R/W PCI Image2 Translation Address register */
uint32 P_IMG_CTRL3; /* 0x130 32 R/W PCI Image3 Control register */
uint32 P_BA3; /* 0x134 32 R/W PCI Image3 Base Address register */
uint32 P_AM3; /* 0x138 32 R/W PCI Image3 Address Mask register */
uint32 P_TA3; /* 0x13C 32 R/W PCI Image3 Translation Address register */
uint32 P_IMG_CTRL4; /* 0x140 32 R/W PCI Image4 Control register */
uint32 P_BA4; /* 0x144 32 R/W PCI Image4 Base Address register */
uint32 P_AM4; /* 0x148 32 R/W PCI Image4 Address Mask register */
uint32 P_TA4; /* 0x14C 32 R/W PCI Image4 Translation Address register */
uint32 P_IMG_CTRL5; /* 0x150 32 R/W PCI Image5 Control register */
uint32 P_BA5; /* 0x154 32 R/W PCI Image5 Base Address register */
uint32 P_AM5; /* 0x158 32 R/W PCI Image5 Address Mask register */
uint32 P_TA5; /* 0x15C 32 R/W PCI Image5 Translation Address register */
uint32 P_ERR_CS; /* 0x160 32 R/W PCI Error Control and Status register */
uint32 P_ERR_ADDR; /* 0x164 32 R PCI Erroneous Address register */
uint32 P_ERR_DATA; /* 0x168 32 R PCI Erroneous Data register */
uint32 PAD[5]; /* 0x16C-0x17F PADDING */
uint32 WB_CONF_SPC_BAR; /* 0x180 32 R WISHBONE Configuration Space Base Address */
uint32 W_IMG_CTRL1; /* 0x184 32 R/W WISHBONE Image1 Control register */
uint32 W_BA1; /* 0x188 32 R/W WISHBONE Image1 Base Address register */
uint32 W_AM1; /* 0x18C 32 R/W WISHBONE Image1 Address Mask register */
uint32 W_TA1; /* 0x190 32 R/W WISHBONE Image1 Translation Address reg */
uint32 W_IMG_CTRL2; /* 0x194 32 R/W WISHBONE Image2 Control register */
uint32 W_BA2; /* 0x198 32 R/W WISHBONE Image2 Base Address register */
uint32 W_AM2; /* 0x19C 32 R/W WISHBONE Image2 Address Mask register */
uint32 W_TA2; /* 0x1A0 32 R/W WISHBONE Image2 Translation Address reg */
uint32 W_IMG_CTRL3; /* 0x1A4 32 R/W WISHBONE Image3 Control register */
uint32 W_BA3; /* 0x1A8 32 R/W WISHBONE Image3 Base Address register */
uint32 W_AM3; /* 0x1AC 32 R/W WISHBONE Image3 Address Mask register */
uint32 W_TA3; /* 0x1B0 32 R/W WISHBONE Image3 Translation Address reg */
uint32 W_IMG_CTRL4; /* 0x1B4 32 R/W WISHBONE Image4 Control register */
uint32 W_BA4; /* 0x1B8 32 R/W WISHBONE Image4 Base Address register */
uint32 W_AM4; /* 0x1BC 32 R/W WISHBONE Image4 Address Mask register */
uint32 W_TA4; /* 0x1C0 32 R/W WISHBONE Image4 Translation Address reg */
uint32 W_IMG_CTRL5; /* 0x1C4 32 R/W WISHBONE Image5 Control register */
uint32 W_BA5; /* 0x1C8 32 R/W WISHBONE Image5 Base Address register */
uint32 W_AM5; /* 0x1CC 32 R/W WISHBONE Image5 Address Mask register */
uint32 W_TA5; /* 0x1D0 32 R/W WISHBONE Image5 Translation Address reg */
uint32 W_ERR_CS; /* 0x1D4 32 R/W WISHBONE Error Control and Status reg */
uint32 W_ERR_ADDR; /* 0x1D8 32 R WISHBONE Erroneous Address register */
uint32 W_ERR_DATA; /* 0x1DC 32 R WISHBONE Erroneous Data register */
uint32 CNF_ADDR; /* 0x1E0 32 R/W Configuration Cycle register */
uint32 CNF_DATA; /* 0x1E4 32 R/W Configuration Cycle Generation Data reg */
uint32 INT_ACK; /* 0x1E8 32 R Interrupt Acknowledge register */
uint32 ICR; /* 0x1EC 32 R/W Interrupt Control register */
uint32 ISR; /* 0x1F0 32 R/W Interrupt Status register */
} spih_pciregs_t;
/*
* PCI Core interrupt enable and status bit definitions.
*/
/* PCI Core ICR Register bit definitions */
#define PCI_INT_PROP_EN (1 << 0) /* Interrupt Propagation Enable */
#define PCI_WB_ERR_INT_EN (1 << 1) /* Wishbone Error Interrupt Enable */
#define PCI_PCI_ERR_INT_EN (1 << 2) /* PCI Error Interrupt Enable */
#define PCI_PAR_ERR_INT_EN (1 << 3) /* Parity Error Interrupt Enable */
#define PCI_SYS_ERR_INT_EN (1 << 4) /* System Error Interrupt Enable */
#define PCI_SOFTWARE_RESET (1U << 31) /* Software reset of the PCI Core. */
/* PCI Core ISR Register bit definitions */
#define PCI_INT_PROP_ST (1 << 0) /* Interrupt Propagation Status */
#define PCI_WB_ERR_INT_ST (1 << 1) /* Wishbone Error Interrupt Status */
#define PCI_PCI_ERR_INT_ST (1 << 2) /* PCI Error Interrupt Status */
#define PCI_PAR_ERR_INT_ST (1 << 3) /* Parity Error Interrupt Status */
#define PCI_SYS_ERR_INT_ST (1 << 4) /* System Error Interrupt Status */
/* Registers on the Wishbone bus */
#define SPIH_CTLR_INTR (1 << 0) /* SPI Host Controller Core Interrupt */
#define SPIH_DEV_INTR (1 << 1) /* SPI Device Interrupt */
#define SPIH_WFIFO_INTR (1 << 2) /* SPI Tx FIFO Empty Intr (FPGA Rev >= 8) */
/* GPIO Bit definitions */
#define SPIH_CS (1 << 0) /* SPI Chip Select (active low) */
#define SPIH_SLOT_POWER (1 << 1) /* SD Card Slot Power Enable */
#define SPIH_CARD_DETECT (1 << 2) /* SD Card Detect */
/* SPI Status Register Bit definitions */
#define SPIH_STATE_MASK 0x30 /* SPI Transfer State Machine state mask */
#define SPIH_STATE_SHIFT 4 /* SPI Transfer State Machine state shift */
#define SPIH_WFFULL (1 << 3) /* SPI Write FIFO Full */
#define SPIH_WFEMPTY (1 << 2) /* SPI Write FIFO Empty */
#define SPIH_RFFULL (1 << 1) /* SPI Read FIFO Full */
#define SPIH_RFEMPTY (1 << 0) /* SPI Read FIFO Empty */
#define SPIH_EXT_CLK (1U << 31) /* Use External Clock as PLL Clock source. */
#define SPIH_PLL_NO_CLK (1 << 1) /* Set to 1 if the PLL's input clock is lost. */
#define SPIH_PLL_LOCKED (1 << 3) /* Set to 1 when the PLL is locked. */
/* Spin bit loop bound check */
#define SPI_SPIN_BOUND 0xf4240 /* 1 million */

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/*
* Performance counters software interface.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmperf.h,v 13.5 2007/09/14 22:00:59 Exp $
*/
/* essai */
#ifndef _BCMPERF_H_
#define _BCMPERF_H_
/* get cache hits and misses */
#define BCMPERF_ENABLE_INSTRCOUNT()
#define BCMPERF_ENABLE_ICACHE_MISS()
#define BCMPERF_ENABLE_ICACHE_HIT()
#define BCMPERF_GETICACHE_MISS(x) ((x) = 0)
#define BCMPERF_GETICACHE_HIT(x) ((x) = 0)
#define BCMPERF_GETINSTRCOUNT(x) ((x) = 0)
#endif /* _BCMPERF_H_ */

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/*
* Definitions for API from sdio common code (bcmsdh) to individual
* host controller drivers.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdbus.h,v 13.11.14.2.6.6 2009/10/27 17:20:28 Exp $
*/
#ifndef _sdio_api_h_
#define _sdio_api_h_
#define SDIOH_API_RC_SUCCESS (0x00)
#define SDIOH_API_RC_FAIL (0x01)
#define SDIOH_API_SUCCESS(status) (status == 0)
#define SDIOH_READ 0 /* Read request */
#define SDIOH_WRITE 1 /* Write request */
#define SDIOH_DATA_FIX 0 /* Fixed addressing */
#define SDIOH_DATA_INC 1 /* Incremental addressing */
#define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */
#define SDIOH_CMD_TYPE_APPEND 1 /* Append command */
#define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */
#define SDIOH_DATA_PIO 0 /* PIO mode */
#define SDIOH_DATA_DMA 1 /* DMA mode */
typedef int SDIOH_API_RC;
/* SDio Host structure */
typedef struct sdioh_info sdioh_info_t;
/* callback function, taking one arg */
typedef void (*sdioh_cb_fn_t)(void *);
/* attach, return handler on success, NULL if failed.
* The handler shall be provided by all subsequent calls. No local cache
* cfghdl points to the starting address of pci device mapped memory
*/
extern sdioh_info_t * sdioh_attach(osl_t *osh, void *cfghdl, uint irq);
extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *si);
extern SDIOH_API_RC sdioh_interrupt_register(sdioh_info_t *si, sdioh_cb_fn_t fn, void *argh);
extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *si);
/* query whether SD interrupt is enabled or not */
extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *si, bool *onoff);
/* enable or disable SD interrupt */
extern SDIOH_API_RC sdioh_interrupt_set(sdioh_info_t *si, bool enable_disable);
#if defined(DHD_DEBUG)
extern bool sdioh_interrupt_pending(sdioh_info_t *si);
#endif
/* read or write one byte using cmd52 */
extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc, uint addr, uint8 *byte);
/* read or write 2/4 bytes using cmd53 */
extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type, uint rw, uint fnc,
uint addr, uint32 *word, uint nbyte);
/* read or write any buffer using cmd53 */
extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, uint fix_inc,
uint rw, uint fnc_num, uint32 addr, uint regwidth, uint32 buflen, uint8 *buffer,
void *pkt);
/* get cis data */
extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, uint8 *cis, uint32 length);
extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, uint32 addr, uint8 *data);
extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, uint32 addr, uint8 *data);
/* query number of io functions */
extern uint sdioh_query_iofnum(sdioh_info_t *si);
/* handle iovars */
extern int sdioh_iovar_op(sdioh_info_t *si, const char *name,
void *params, int plen, void *arg, int len, bool set);
/* Issue abort to the specified function and clear controller as needed */
extern int sdioh_abort(sdioh_info_t *si, uint fnc);
/* Start and Stop SDIO without re-enumerating the SD card. */
extern int sdioh_start(sdioh_info_t *si, int stage);
extern int sdioh_stop(sdioh_info_t *si);
/* Reset and re-initialize the device */
extern int sdioh_sdio_reset(sdioh_info_t *si);
/* Helper function */
void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh);
#endif /* _sdio_api_h_ */

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/*
* SDIO host client driver interface of Broadcom HNBU
* export functions to client drivers
* abstract OS and BUS specific details of SDIO
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdh.h,v 13.35.14.7.6.8 2009/10/14 04:22:25 Exp $
*/
#ifndef _bcmsdh_h_
#define _bcmsdh_h_
#define BCMSDH_ERROR_VAL 0x0001 /* Error */
#define BCMSDH_INFO_VAL 0x0002 /* Info */
extern const uint bcmsdh_msglevel;
#define BCMSDH_ERROR(x)
#define BCMSDH_INFO(x)
/* forward declarations */
typedef struct bcmsdh_info bcmsdh_info_t;
typedef void (*bcmsdh_cb_fn_t)(void *);
/* Attach and build an interface to the underlying SD host driver.
* - Allocates resources (structs, arrays, mem, OS handles, etc) needed by bcmsdh.
* - Returns the bcmsdh handle and virtual address base for register access.
* The returned handle should be used in all subsequent calls, but the bcmsh
* implementation may maintain a single "default" handle (e.g. the first or
* most recent one) to enable single-instance implementations to pass NULL.
*/
extern bcmsdh_info_t *bcmsdh_attach(osl_t *osh, void *cfghdl, void **regsva, uint irq);
/* Detach - freeup resources allocated in attach */
extern int bcmsdh_detach(osl_t *osh, void *sdh);
/* Query if SD device interrupts are enabled */
extern bool bcmsdh_intr_query(void *sdh);
/* Enable/disable SD interrupt */
extern int bcmsdh_intr_enable(void *sdh);
extern int bcmsdh_intr_disable(void *sdh);
/* Register/deregister device interrupt handler. */
extern int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
extern int bcmsdh_intr_dereg(void *sdh);
#if defined(DHD_DEBUG)
/* Query pending interrupt status from the host controller */
extern bool bcmsdh_intr_pending(void *sdh);
#endif
#ifdef BCMLXSDMMC
extern int bcmsdh_claim_host_and_lock(void *sdh);
extern int bcmsdh_release_host_and_unlock(void *sdh);
#endif /* BCMLXSDMMC */
/* Register a callback to be called if and when bcmsdh detects
* device removal. No-op in the case of non-removable/hardwired devices.
*/
extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
* fn: function number
* addr: unmodified SDIO-space address
* data: data byte to write
* err: pointer to error code (or NULL)
*/
extern uint8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err);
extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, uint8 data, int *err);
/* Read/Write 4bytes from/to cfg space */
extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err);
extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err);
/* Read CIS content for specified function.
* fn: function whose CIS is being requested (0 is common CIS)
* cis: pointer to memory location to place results
* length: number of bytes to read
* Internally, this routine uses the values from the cis base regs (0x9-0xB)
* to form an SDIO-space address to read the data from.
*/
extern int bcmsdh_cis_read(void *sdh, uint func, uint8 *cis, uint length);
/* Synchronous access to device (client) core registers via CMD53 to F1.
* addr: backplane address (i.e. >= regsva from attach)
* size: register width in bytes (2 or 4)
* data: data for register write
*/
extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size);
extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data);
/* Indicate if last reg read/write failed */
extern bool bcmsdh_regfail(void *sdh);
/* Buffer transfer to/from device (client) core via cmd53.
* fn: function number
* addr: backplane address (i.e. >= regsva from attach)
* flags: backplane width, address increment, sync/async
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* pkt: pointer to packet associated with buf (if any)
* complete: callback function for command completion (async only)
* handle: handle for completion callback (first arg in callback)
* Returns 0 or error code.
* NOTE: Async operation is not currently supported.
*/
typedef void (*bcmsdh_cmplt_fn_t)(void *handle, int status, bool sync_waiting);
extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle);
extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle);
/* Flags bits */
#define SDIO_REQ_4BYTE 0x1 /* Four-byte target (backplane) width (vs. two-byte) */
#define SDIO_REQ_FIXED 0x2 /* Fixed address (FIFO) (vs. incrementing address) */
#define SDIO_REQ_ASYNC 0x4 /* Async request (vs. sync request) */
/* Pending (non-error) return code */
#define BCME_PENDING 1
/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
* rw: read or write (0/1)
* addr: direct SDIO address
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* Returns 0 or error code.
*/
extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes);
/* Issue an abort to the specified function */
extern int bcmsdh_abort(void *sdh, uint fn);
/* Start SDIO Host Controller communication */
extern int bcmsdh_start(void *sdh, int stage);
/* Stop SDIO Host Controller communication */
extern int bcmsdh_stop(void *sdh);
/* Returns the "Device ID" of target device on the SDIO bus. */
extern int bcmsdh_query_device(void *sdh);
/* Returns the number of IO functions reported by the device */
extern uint bcmsdh_query_iofnum(void *sdh);
/* Miscellaneous knob tweaker. */
extern int bcmsdh_iovar_op(void *sdh, const char *name,
void *params, int plen, void *arg, int len, bool set);
/* Reset and reinitialize the device */
extern int bcmsdh_reset(bcmsdh_info_t *sdh);
/* helper functions */
extern void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh);
/* callback functions */
typedef struct {
/* attach to device */
void *(*attach)(uint16 vend_id, uint16 dev_id, uint16 bus, uint16 slot,
uint16 func, uint bustype, void * regsva, osl_t * osh,
void * param);
/* detach from device */
void (*detach)(void *ch);
} bcmsdh_driver_t;
/* platform specific/high level functions */
extern int bcmsdh_register(bcmsdh_driver_t *driver);
extern void bcmsdh_unregister(void);
extern bool bcmsdh_chipmatch(uint16 vendor, uint16 device);
extern void bcmsdh_device_remove(void * sdh);
#if defined(OOB_INTR_ONLY)
extern int bcmsdh_register_oob_intr(void * dhdp);
extern void bcmsdh_unregister_oob_intr(void);
extern void bcmsdh_oob_intr_set(bool enable);
#endif /* defined(OOB_INTR_ONLY) */
/* Function to pass device-status bits to DHD. */
extern uint32 bcmsdh_get_dstatus(void *sdh);
/* Function to return current window addr */
extern uint32 bcmsdh_cur_sbwad(void *sdh);
/* Function to pass chipid and rev to lower layers for controlling pr's */
extern void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev);
#endif /* _bcmsdh_h_ */

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/*
* BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdh_sdmmc.h,v 13.1.2.1.8.7 2009/10/27 18:22:52 Exp $
*/
#ifndef __BCMSDH_SDMMC_H__
#define __BCMSDH_SDMMC_H__
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#define sd_sync_dma(sd, read, nbytes)
#define sd_init_dma(sd)
#define sd_ack_intr(sd)
#define sd_wakeup(sd);
/* Allocate/init/free per-OS private data */
extern int sdioh_sdmmc_osinit(sdioh_info_t *sd);
extern void sdioh_sdmmc_osfree(sdioh_info_t *sd);
#define sd_log(x)
#define SDIOH_ASSERT(exp) \
do { if (!(exp)) \
printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
} while (0)
#define BLOCK_SIZE_4318 64
#define BLOCK_SIZE_4328 512
/* internal return code */
#define SUCCESS 0
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SD4 2
#define CLIENT_INTR 0x100 /* Get rid of this! */
struct sdioh_info {
osl_t *osh; /* osh handler */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
uint16 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint irq; /* Client irq */
int intrcount; /* Client interrupts */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
uint max_dma_len;
uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */
// SDDMA_DESCRIPTOR SGList[32]; /* Scatter/Gather DMA List */
};
/************************************************************
* Internal interfaces: per-port references into bcmsdh_sdmmc.c
*/
/* Global message bits */
extern uint sd_msglevel;
/* OS-independent interrupt handler */
extern bool check_client_intr(sdioh_info_t *sd);
/* Core interrupt enable/disable of device interrupts */
extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd);
extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd);
/**************************************************************
* Internal interfaces: bcmsdh_sdmmc.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *sdioh_sdmmc_reg_map(osl_t *osh, int32 addr, int size);
extern void sdioh_sdmmc_reg_unmap(osl_t *osh, int32 addr, int size);
/* Interrupt (de)registration routines */
extern int sdioh_sdmmc_register_irq(sdioh_info_t *sd, uint irq);
extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd);
typedef struct _BCMSDH_SDMMC_INSTANCE {
sdioh_info_t *sd;
struct sdio_func *func[SDIOD_MAX_IOFUNCS];
} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE;
#endif /* __BCMSDH_SDMMC_H__ */

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/*
* Broadcom SDIO/PCMCIA
* Software-specific definitions shared between device and host side
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdpcm.h,v 1.1.2.4 2010/07/02 01:15:46 Exp $
*/
#ifndef _bcmsdpcm_h_
#define _bcmsdpcm_h_
/*
* Software allocation of To SB Mailbox resources
*/
/* intstatus bits */
#define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */
#define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */
#define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */
#define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */
/* tosbmailbox bits corresponding to intstatus bits */
#define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */
#define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */
#define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */
#define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */
#define SMB_MASK 0x0000000f /* To SB Mailbox Mask */
/* tosbmailboxdata */
#define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */
#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */
/*
* Software allocation of To Host Mailbox resources
*/
/* intstatus bits */
#define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */
#define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */
#define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */
#define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */
/* tohostmailbox bits corresponding to intstatus bits */
#define HMB_FC_ON (1 << 0) /* To Host Mailbox Flow Control State */
#define HMB_FC_CHANGE (1 << 1) /* To Host Mailbox Flow Control State Changed */
#define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */
#define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */
#define HMB_MASK 0x0000000f /* To Host Mailbox Mask */
/* tohostmailboxdata */
#define HMB_DATA_NAKHANDLED 1 /* we're ready to retransmit NAK'd frame to host */
#define HMB_DATA_DEVREADY 2 /* we're ready to to talk to host after enable */
#define HMB_DATA_FC 4 /* per prio flowcontrol update flag to host */
#define HMB_DATA_FWREADY 8 /* firmware is ready for protocol activity */
#define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */
#define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */
#define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */
#define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */
/*
* Software-defined protocol header
*/
/* Current protocol version */
#define SDPCM_PROT_VERSION 4
/* SW frame header */
#define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */
#define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */
#define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */
#define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */
#define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */
#define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */
#define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */
#define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */
/* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */
#define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */
#define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */
#define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */
#define SDPCM_NEXTLEN_OFFSET 2
/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
#define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
#define SDPCM_DOFFSET_MASK 0xff000000
#define SDPCM_DOFFSET_SHIFT 24
#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
#define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff)
#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
#define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
#define SDPCM_VERSION_OFFSET 6 /* Version # */
#define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff)
#define SDPCM_UNUSED_OFFSET 7 /* Spare */
#define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff)
#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
/* logical channel numbers */
#define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */
#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */
#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
#define SDPCM_MAX_CHANNEL 15
#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */
#define SDPCM_FLAG_RESVD0 0x01
#define SDPCM_FLAG_RESVD1 0x02
#define SDPCM_FLAG_GSPI_TXENAB 0x04
#define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */
/* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */
#define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT)
#define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80)
/* For TEST_CHANNEL packets, define another 4-byte header */
#define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2);
* Semantics of Ext byte depend on command.
* Len is current or requested frame length, not
* including test header; sent little-endian.
*/
#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */
#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */
#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */
#define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count */
#define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off */
/* Handy macro for filling in datagen packets with a pattern */
#define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno))
/*
* Software counters (first part matches hardware counters)
*/
typedef volatile struct {
uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
uint32 abort; /* AbortCount, SDIO: aborts */
uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */
uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */
uint32 rxdescuflo; /* receive descriptor underflows */
uint32 rxfifooflo; /* receive fifo overflows */
uint32 txfifouflo; /* transmit fifo underflows */
uint32 runt; /* runt (too short) frames recv'd from bus */
uint32 badlen; /* frame's rxh len does not match its hw tag len */
uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */
uint32 seqbreak; /* break in sequence # space from one rx frame to the next */
uint32 rxfcrc; /* frame rx header indicates crc error */
uint32 rxfwoos; /* frame rx header indicates write out of sync */
uint32 rxfwft; /* frame rx header indicates write frame termination */
uint32 rxfabort; /* frame rx header indicates frame aborted */
uint32 woosint; /* write out of sync interrupt */
uint32 roosint; /* read out of sync interrupt */
uint32 rftermint; /* read frame terminate interrupt */
uint32 wftermint; /* write frame terminate interrupt */
} sdpcmd_cnt_t;
/*
* Register Access Macros
*/
#define SDIODREV_IS(var, val) ((var) == (val))
#define SDIODREV_GE(var, val) ((var) >= (val))
#define SDIODREV_GT(var, val) ((var) > (val))
#define SDIODREV_LT(var, val) ((var) < (val))
#define SDIODREV_LE(var, val) ((var) <= (val))
#define SDIODDMAREG32(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \
(void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv))
#define SDIODDMAREG64(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \
(void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv))
#define SDIODDMAREG(h, dir, chnl) \
(SDIODREV_LT((h)->corerev, 1) ? \
SDIODDMAREG32((h), (dir), (chnl)) : \
SDIODDMAREG64((h), (dir), (chnl)))
#define PCMDDMAREG(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \
(void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv))
#define SDPCMDMAREG(h, dir, chnl, coreid) \
((coreid) == SDIOD_CORE_ID ? \
SDIODDMAREG(h, dir, chnl) : \
PCMDDMAREG(h, dir, chnl))
#define SDIODFIFOREG(h, corerev) \
(SDIODREV_LT((corerev), 1) ? \
((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \
((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo)))
#define PCMDFIFOREG(h) \
((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo))
#define SDPCMFIFOREG(h, coreid, corerev) \
((coreid) == SDIOD_CORE_ID ? \
SDIODFIFOREG(h, corerev) : \
PCMDFIFOREG(h))
/*
* Shared structure between dongle and the host
* The structure contains pointers to trap or assert information shared with the host
*/
#define SDPCM_SHARED_VERSION 0x0002
#define SDPCM_SHARED_VERSION_MASK 0x00FF
#define SDPCM_SHARED_ASSERT_BUILT 0x0100
#define SDPCM_SHARED_ASSERT 0x0200
#define SDPCM_SHARED_TRAP 0x0400
typedef struct {
uint32 flags;
uint32 trap_addr;
uint32 assert_exp_addr;
uint32 assert_file_addr;
uint32 assert_line;
uint32 console_addr; /* Address of hndrte_cons_t */
uint32 msgtrace_addr;
uint8 tag[32];
} sdpcm_shared_t;
extern sdpcm_shared_t sdpcm_shared;
#endif /* _bcmsdpcm_h_ */

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/*
* SD-SPI Protocol Conversion - BCMSDH->SPI Translation Layer
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdspi.h,v 13.8.10.2 2008/06/30 21:09:40 Exp $
*/
/* global msglevel for debug messages - bitvals come from sdiovar.h */
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#define sd_log(x)
#define SDIOH_ASSERT(exp) \
do { if (!(exp)) \
printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
} while (0)
#define BLOCK_SIZE_4318 64
#define BLOCK_SIZE_4328 512
/* internal return code */
#define SUCCESS 0
#undef ERROR
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SPI 0
#define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */
#define USE_MULTIBLOCK 0x4
struct sdioh_info {
uint cfg_bar; /* pci cfg address for bar */
uint32 caps; /* cached value of capabilities reg */
uint bar0; /* BAR0 for PCI Device */
osl_t *osh; /* osh handler */
void *controller; /* Pointer to SPI Controller's private data struct */
uint lockcount; /* nest count of sdspi_lock() calls */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
bool initialized; /* card initialized */
uint32 target_dev; /* Target device ID */
uint32 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint32 controller_type; /* Host controller type */
uint8 version; /* Host Controller Spec Compliance Version */
uint irq; /* Client irq */
uint32 intrcount; /* Client interrupts */
uint32 local_intrcount; /* Controller interrupts */
bool host_init_done; /* Controller initted */
bool card_init_done; /* Client SDIO interface initted */
bool polled_mode; /* polling for command completion */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
bool got_hcint; /* Host Controller interrupt. */
/* polling hack in wl_linux.c:wl_timer() */
int adapter_slot; /* Maybe dealing with multiple slots/controllers */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint32 data_xfer_count; /* Current register transfer size */
uint32 cmd53_wr_data; /* Used to pass CMD53 write data */
uint32 card_response; /* Used to pass back response status byte */
uint32 card_rsp_data; /* Used to pass back response data word */
uint16 card_rca; /* Current Address */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
void *dma_buf;
ulong dma_phys;
int r_cnt; /* rx count */
int t_cnt; /* tx_count */
};
/************************************************************
* Internal interfaces: per-port references into bcmsdspi.c
*/
/* Global message bits */
extern uint sd_msglevel;
/**************************************************************
* Internal interfaces: bcmsdspi.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *spi_reg_map(osl_t *osh, uintptr addr, int size);
extern void spi_reg_unmap(osl_t *osh, uintptr addr, int size);
/* Interrupt (de)registration routines */
extern int spi_register_irq(sdioh_info_t *sd, uint irq);
extern void spi_free_irq(uint irq, sdioh_info_t *sd);
/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
extern void spi_lock(sdioh_info_t *sd);
extern void spi_unlock(sdioh_info_t *sd);
/* Allocate/init/free per-OS private data */
extern int spi_osinit(sdioh_info_t *sd);
extern void spi_osfree(sdioh_info_t *sd);

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/*
* 'Standard' SDIO HOST CONTROLLER driver
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdstd.h,v 13.16.18.1.16.3 2009/12/10 01:09:23 Exp $
*/
/* global msglevel for debug messages - bitvals come from sdiovar.h */
#define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#define sd_dma(x)
#define sd_sync_dma(sd, read, nbytes)
#define sd_init_dma(sd)
#define sd_ack_intr(sd)
#define sd_wakeup(sd);
/* Allocate/init/free per-OS private data */
extern int sdstd_osinit(sdioh_info_t *sd);
extern void sdstd_osfree(sdioh_info_t *sd);
#define sd_log(x)
#define SDIOH_ASSERT(exp) \
do { if (!(exp)) \
printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
} while (0)
#define BLOCK_SIZE_4318 64
#define BLOCK_SIZE_4328 512
/* internal return code */
#define SUCCESS 0
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SPI 0
#define SDIOH_MODE_SD1 1
#define SDIOH_MODE_SD4 2
#define MAX_SLOTS 6 /* For PCI: Only 6 BAR entries => 6 slots */
#define SDIOH_REG_WINSZ 0x100 /* Number of registers in Standard Host Controller */
#define SDIOH_TYPE_ARASAN_HDK 1
#define SDIOH_TYPE_BCM27XX 2
#define SDIOH_TYPE_TI_PCIXX21 4 /* TI PCIxx21 Standard Host Controller */
#define SDIOH_TYPE_RICOH_R5C822 5 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter */
#define SDIOH_TYPE_JMICRON 6 /* JMicron Standard SDIO Host Controller */
/* For linux, allow yielding for dongle */
#define BCMSDYIELD
/* Expected card status value for CMD7 */
#define SDIOH_CMD7_EXP_STATUS 0x00001E00
#define RETRIES_LARGE 100000
#define RETRIES_SMALL 100
#define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */
#define USE_MULTIBLOCK 0x4
#define USE_FIFO 0x8 /* Fifo vs non-fifo */
#define CLIENT_INTR 0x100 /* Get rid of this! */
struct sdioh_info {
uint cfg_bar; /* pci cfg address for bar */
uint32 caps; /* cached value of capabilities reg */
uint32 curr_caps; /* max current capabilities reg */
osl_t *osh; /* osh handler */
volatile char *mem_space; /* pci device memory va */
uint lockcount; /* nest count of sdstd_lock() calls */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
bool initialized; /* card initialized */
uint target_dev; /* Target device ID */
uint16 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint32 controller_type; /* Host controller type */
uint8 version; /* Host Controller Spec Compliance Version */
uint irq; /* Client irq */
int intrcount; /* Client interrupts */
int local_intrcount; /* Controller interrupts */
bool host_init_done; /* Controller initted */
bool card_init_done; /* Client SDIO interface initted */
bool polled_mode; /* polling for command completion */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
/* polling hack in wl_linux.c:wl_timer() */
int adapter_slot; /* Maybe dealing with multiple slots/controllers */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint32 data_xfer_count; /* Current transfer */
uint16 card_rca; /* Current Address */
int8 sd_dma_mode; /* DMA Mode (PIO, SDMA, ... ADMA2) on CMD53 */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
void *dma_buf; /* DMA Buffer virtual address */
ulong dma_phys; /* DMA Buffer physical address */
void *adma2_dscr_buf; /* ADMA2 Descriptor Buffer virtual address */
ulong adma2_dscr_phys; /* ADMA2 Descriptor Buffer physical address */
/* adjustments needed to make the dma align properly */
void *dma_start_buf;
ulong dma_start_phys;
uint alloced_dma_size;
void *adma2_dscr_start_buf;
ulong adma2_dscr_start_phys;
uint alloced_adma2_dscr_size;
int r_cnt; /* rx count */
int t_cnt; /* tx_count */
bool got_hcint; /* local interrupt flag */
uint16 last_intrstatus; /* to cache intrstatus */
};
#define DMA_MODE_NONE 0
#define DMA_MODE_SDMA 1
#define DMA_MODE_ADMA1 2
#define DMA_MODE_ADMA2 3
#define DMA_MODE_ADMA2_64 4
#define DMA_MODE_AUTO -1
#define USE_DMA(sd) ((bool)((sd->sd_dma_mode > 0) ? TRUE : FALSE))
/* SDIO Host Control Register DMA Mode Definitions */
#define SDIOH_SDMA_MODE 0
#define SDIOH_ADMA1_MODE 1
#define SDIOH_ADMA2_MODE 2
#define SDIOH_ADMA2_64_MODE 3
#define ADMA2_ATTRIBUTE_VALID (1 << 0) /* ADMA Descriptor line valid */
#define ADMA2_ATTRIBUTE_END (1 << 1) /* End of Descriptor */
#define ADMA2_ATTRIBUTE_INT (1 << 2) /* Interrupt when line is done */
#define ADMA2_ATTRIBUTE_ACT_NOP (0 << 4) /* Skip current line, go to next. */
#define ADMA2_ATTRIBUTE_ACT_RSV (1 << 4) /* Same as NOP */
#define ADMA1_ATTRIBUTE_ACT_SET (1 << 4) /* ADMA1 Only - set transfer length */
#define ADMA2_ATTRIBUTE_ACT_TRAN (2 << 4) /* Transfer Data of one descriptor line. */
#define ADMA2_ATTRIBUTE_ACT_LINK (3 << 4) /* Link Descriptor */
/* ADMA2 Descriptor Table Entry for 32-bit Address */
typedef struct adma2_dscr_32b {
uint32 len_attr;
uint32 phys_addr;
} adma2_dscr_32b_t;
/* ADMA1 Descriptor Table Entry */
typedef struct adma1_dscr {
uint32 phys_addr_attr;
} adma1_dscr_t;
/************************************************************
* Internal interfaces: per-port references into bcmsdstd.c
*/
/* Global message bits */
extern uint sd_msglevel;
/* OS-independent interrupt handler */
extern bool check_client_intr(sdioh_info_t *sd);
/* Core interrupt enable/disable of device interrupts */
extern void sdstd_devintr_on(sdioh_info_t *sd);
extern void sdstd_devintr_off(sdioh_info_t *sd);
/* Enable/disable interrupts for local controller events */
extern void sdstd_intrs_on(sdioh_info_t *sd, uint16 norm, uint16 err);
extern void sdstd_intrs_off(sdioh_info_t *sd, uint16 norm, uint16 err);
/* Wait for specified interrupt and error bits to be set */
extern void sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err);
/**************************************************************
* Internal interfaces: bcmsdstd.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *sdstd_reg_map(osl_t *osh, int32 addr, int size);
extern void sdstd_reg_unmap(osl_t *osh, int32 addr, int size);
/* Interrupt (de)registration routines */
extern int sdstd_register_irq(sdioh_info_t *sd, uint irq);
extern void sdstd_free_irq(uint irq, sdioh_info_t *sd);
/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
extern void sdstd_lock(sdioh_info_t *sd);
extern void sdstd_unlock(sdioh_info_t *sd);
/* OS-specific wait-for-interrupt-or-status */
extern uint16 sdstd_waitbits(sdioh_info_t *sd, uint16 norm, uint16 err, bool yield);

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/*
* Broadcom SPI Low-Level Hardware Driver API
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmspi.h,v 13.3.10.2 2008/06/30 21:09:40 Exp $
*/
extern void spi_devintr_off(sdioh_info_t *sd);
extern void spi_devintr_on(sdioh_info_t *sd);
extern bool spi_start_clock(sdioh_info_t *sd, uint16 new_sd_divisor);
extern bool spi_controller_highspeed_mode(sdioh_info_t *sd, bool hsmode);
extern bool spi_check_client_intr(sdioh_info_t *sd, int *is_dev_intr);
extern bool spi_hw_attach(sdioh_info_t *sd);
extern bool spi_hw_detach(sdioh_info_t *sd);
extern void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen);
extern void spi_spinbits(sdioh_info_t *sd);
extern void spi_waitbits(sdioh_info_t *sd, bool yield);

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/*
* Misc useful os-independent macros and functions.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: bcmutils.h,v 13.184.4.6.2.1.18.25 2010/04/26 06:05:24 Exp $
*/
#ifndef _bcmutils_h_
#define _bcmutils_h_
#ifdef __cplusplus
extern "C" {
#endif
#define _BCM_U 0x01
#define _BCM_L 0x02
#define _BCM_D 0x04
#define _BCM_C 0x08
#define _BCM_P 0x10
#define _BCM_S 0x20
#define _BCM_X 0x40
#define _BCM_SP 0x80
extern const unsigned char bcm_ctype[];
#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
#define bcm_tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
#define bcm_toupper(c) (bcm_islower((c)) ? ((c) + 'A' - 'a') : (c))
struct bcmstrbuf {
char *buf;
unsigned int size;
char *origbuf;
unsigned int origsize;
};
#ifdef BCMDRIVER
#include <osl.h>
#define GPIO_PIN_NOTDEFINED 0x20
#define SPINWAIT(exp, us) { \
uint countdown = (us) + 9; \
while ((exp) && (countdown >= 10)) {\
OSL_DELAY(10); \
countdown -= 10; \
} \
}
#ifndef PKTQ_LEN_DEFAULT
#define PKTQ_LEN_DEFAULT 128
#endif
#ifndef PKTQ_MAX_PREC
#define PKTQ_MAX_PREC 16
#endif
typedef struct pktq_prec {
void *head;
void *tail;
uint16 len;
uint16 max;
} pktq_prec_t;
struct pktq {
uint16 num_prec;
uint16 hi_prec;
uint16 max;
uint16 len;
struct pktq_prec q[PKTQ_MAX_PREC];
};
struct spktq {
uint16 num_prec;
uint16 hi_prec;
uint16 max;
uint16 len;
struct pktq_prec q[1];
};
#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
struct ether_addr;
extern int ether_isbcast(const void *ea);
extern int ether_isnulladdr(const void *ea);
#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
#define pktq_plen(pq, prec) ((pq)->q[prec].len)
#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
extern void *pktq_penq(struct pktq *pq, int prec, void *p);
extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
extern void *pktq_pdeq(struct pktq *pq, int prec);
extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
extern bool pktq_pdel(struct pktq *pq, void *p, int prec);
extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir);
extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir);
extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
#define pktq_len(pq) ((int)(pq)->len)
#define pktq_max(pq) ((int)(pq)->max)
#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
#define pktq_full(pq) ((pq)->len >= (pq)->max)
#define pktq_empty(pq) ((pq)->len == 0)
#define pktenq(pq, p) pktq_penq(((struct pktq *)pq), 0, (p))
#define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)pq), 0, (p))
#define pktdeq(pq) pktq_pdeq(((struct pktq *)pq), 0)
#define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)pq), 0)
#define pktqinit(pq, len) pktq_init(((struct pktq *)pq), 1, len)
extern void pktq_init(struct pktq *pq, int num_prec, int max_len);
extern void *pktq_deq(struct pktq *pq, int *prec_out);
extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
extern void *pktq_peek(struct pktq *pq, int *prec_out);
extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
extern uint pktfrombuf(osl_t *osh, void *p, uint offset, int len, uchar *buf);
extern uint pkttotlen(osl_t *osh, void *p);
extern void *pktlast(osl_t *osh, void *p);
extern uint pktsegcnt(osl_t *osh, void *p);
extern uint pktsetprio(void *pkt, bool update_vtag);
#define PKTPRIO_VDSCP 0x100
#define PKTPRIO_VLAN 0x200
#define PKTPRIO_UPD 0x400
#define PKTPRIO_DSCP 0x800
extern int bcm_atoi(char *s);
extern ulong bcm_strtoul(char *cp, char **endp, uint base);
extern char *bcmstrstr(char *haystack, char *needle);
extern char *bcmstrcat(char *dest, const char *src);
extern char *bcmstrncat(char *dest, const char *src, uint size);
extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
char* bcmstrtok(char **string, const char *delimiters, char *tokdelim);
int bcmstricmp(const char *s1, const char *s2);
int bcmstrnicmp(const char* s1, const char* s2, int cnt);
extern char *bcm_ether_ntoa(const struct ether_addr *ea, char *buf);
extern int bcm_ether_atoe(char *p, struct ether_addr *ea);
struct ipv4_addr;
extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf);
extern void bcm_mdelay(uint ms);
extern char *getvar(char *vars, const char *name);
extern int getintvar(char *vars, const char *name);
extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
#define bcm_perf_enable()
#define bcmstats(fmt)
#define bcmlog(fmt, a1, a2)
#define bcmdumplog(buf, size) *buf = '\0'
#define bcmdumplogent(buf, idx) -1
#define bcmtslog(tstamp, fmt, a1, a2)
#define bcmprinttslogs()
#define bcmprinttstamp(us)
typedef struct bcm_iovar {
const char *name;
uint16 varid;
uint16 flags;
uint16 type;
uint16 minlen;
} bcm_iovar_t;
#define IOV_GET 0
#define IOV_SET 1
#define IOV_GVAL(id) ((id)*2)
#define IOV_SVAL(id) (((id)*2)+IOV_SET)
#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
#endif
#define IOVT_VOID 0
#define IOVT_BOOL 1
#define IOVT_INT8 2
#define IOVT_UINT8 3
#define IOVT_INT16 4
#define IOVT_UINT16 5
#define IOVT_INT32 6
#define IOVT_UINT32 7
#define IOVT_BUFFER 8
#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER)
#define BCM_IOV_TYPE_INIT { \
"void", \
"bool", \
"int8", \
"uint8", \
"int16", \
"uint16", \
"int32", \
"uint32", \
"buffer", \
"" }
#define BCM_IOVT_IS_INT(type) (\
(type == IOVT_BOOL) || \
(type == IOVT_INT8) || \
(type == IOVT_UINT8) || \
(type == IOVT_INT16) || \
(type == IOVT_UINT16) || \
(type == IOVT_INT32) || \
(type == IOVT_UINT32))
#define BCME_STRLEN 64
#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
#define BCME_OK 0
#define BCME_ERROR -1
#define BCME_BADARG -2
#define BCME_BADOPTION -3
#define BCME_NOTUP -4
#define BCME_NOTDOWN -5
#define BCME_NOTAP -6
#define BCME_NOTSTA -7
#define BCME_BADKEYIDX -8
#define BCME_RADIOOFF -9
#define BCME_NOTBANDLOCKED -10
#define BCME_NOCLK -11
#define BCME_BADRATESET -12
#define BCME_BADBAND -13
#define BCME_BUFTOOSHORT -14
#define BCME_BUFTOOLONG -15
#define BCME_BUSY -16
#define BCME_NOTASSOCIATED -17
#define BCME_BADSSIDLEN -18
#define BCME_OUTOFRANGECHAN -19
#define BCME_BADCHAN -20
#define BCME_BADADDR -21
#define BCME_NORESOURCE -22
#define BCME_UNSUPPORTED -23
#define BCME_BADLEN -24
#define BCME_NOTREADY -25
#define BCME_EPERM -26
#define BCME_NOMEM -27
#define BCME_ASSOCIATED -28
#define BCME_RANGE -29
#define BCME_NOTFOUND -30
#define BCME_WME_NOT_ENABLED -31
#define BCME_TSPEC_NOTFOUND -32
#define BCME_ACM_NOTSUPPORTED -33
#define BCME_NOT_WME_ASSOCIATION -34
#define BCME_SDIO_ERROR -35
#define BCME_DONGLE_DOWN -36
#define BCME_VERSION -37
#define BCME_TXFAIL -38
#define BCME_RXFAIL -39
#define BCME_NODEVICE -40
#define BCME_UNFINISHED -41
#define BCME_LAST BCME_UNFINISHED
#define BCMERRSTRINGTABLE { \
"OK", \
"Undefined error", \
"Bad Argument", \
"Bad Option", \
"Not up", \
"Not down", \
"Not AP", \
"Not STA", \
"Bad Key Index", \
"Radio Off", \
"Not band locked", \
"No clock", \
"Bad Rate valueset", \
"Bad Band", \
"Buffer too short", \
"Buffer too long", \
"Busy", \
"Not Associated", \
"Bad SSID len", \
"Out of Range Channel", \
"Bad Channel", \
"Bad Address", \
"Not Enough Resources", \
"Unsupported", \
"Bad length", \
"Not Ready", \
"Not Permitted", \
"No Memory", \
"Associated", \
"Not In Range", \
"Not Found", \
"WME Not Enabled", \
"TSPEC Not Found", \
"ACM Not Supported", \
"Not WME Association", \
"SDIO Bus Error", \
"Dongle Not Accessible", \
"Incorrect version", \
"TX Failure", \
"RX Failure", \
"Device Not Present", \
"Command not finished", \
}
#ifndef ABS
#define ABS(a) (((a) < 0)?-(a):(a))
#endif
#ifndef MIN
#define MIN(a, b) (((a) < (b))?(a):(b))
#endif
#ifndef MAX
#define MAX(a, b) (((a) > (b))?(a):(b))
#endif
#define CEIL(x, y) (((x) + ((y)-1)) / (y))
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
#define ALIGN_ADDR(addr, boundary) (void *)(((uintptr)(addr) + (boundary) - 1) \
& ~((boundary) - 1))
#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
#ifndef OFFSETOF
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
#endif
#ifndef ARRAYSIZE
#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
#endif
#ifndef setbit
#ifndef NBBY
#define NBBY 8
#endif
#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
#define isset(a, i) (((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
#define isclr(a, i) ((((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
#endif
#define NBITS(type) (sizeof(type) * 8)
#define NBITVAL(nbits) (1 << (nbits))
#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
#define NBITMASK(nbits) MAXBITVAL(nbits)
#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
#define MUX(pred, true, false) ((pred) ? (true) : (false))
#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
#define MODADD(x, y, bound) \
MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
#define MODSUB(x, y, bound) \
MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
#define CRC8_INIT_VALUE 0xff
#define CRC8_GOOD_VALUE 0x9f
#define CRC16_INIT_VALUE 0xffff
#define CRC16_GOOD_VALUE 0xf0b8
#define CRC32_INIT_VALUE 0xffffffff
#define CRC32_GOOD_VALUE 0xdebb20e3
typedef struct bcm_bit_desc {
uint32 bit;
const char* name;
} bcm_bit_desc_t;
typedef struct bcm_tlv {
uint8 id;
uint8 len;
uint8 data[1];
} bcm_tlv_t;
#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
#define ETHER_ADDR_STR_LEN 18
#ifdef IL_BIGENDIAN
static INLINE uint32
load32_ua(uint8 *a)
{
return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
}
static INLINE void
store32_ua(uint8 *a, uint32 v)
{
a[0] = (v >> 24) & 0xff;
a[1] = (v >> 16) & 0xff;
a[2] = (v >> 8) & 0xff;
a[3] = v & 0xff;
}
static INLINE uint16
load16_ua(uint8 *a)
{
return ((a[0] << 8) | a[1]);
}
static INLINE void
store16_ua(uint8 *a, uint16 v)
{
a[0] = (v >> 8) & 0xff;
a[1] = v & 0xff;
}
#else
static INLINE uint32
load32_ua(uint8 *a)
{
return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
}
static INLINE void
store32_ua(uint8 *a, uint32 v)
{
a[3] = (v >> 24) & 0xff;
a[2] = (v >> 16) & 0xff;
a[1] = (v >> 8) & 0xff;
a[0] = v & 0xff;
}
static INLINE uint16
load16_ua(uint8 *a)
{
return ((a[1] << 8) | a[0]);
}
static INLINE void
store16_ua(uint8 *a, uint16 v)
{
a[1] = (v >> 8) & 0xff;
a[0] = v & 0xff;
}
#endif
static INLINE void
xor_128bit_block(const uint8 *src1, const uint8 *src2, uint8 *dst)
{
if (
#ifdef __i386__
1 ||
#endif
(((uintptr)src1 | (uintptr)src2 | (uintptr)dst) & 3) == 0) {
((uint32 *)dst)[0] = ((uint32 *)src1)[0] ^ ((uint32 *)src2)[0];
((uint32 *)dst)[1] = ((uint32 *)src1)[1] ^ ((uint32 *)src2)[1];
((uint32 *)dst)[2] = ((uint32 *)src1)[2] ^ ((uint32 *)src2)[2];
((uint32 *)dst)[3] = ((uint32 *)src1)[3] ^ ((uint32 *)src2)[3];
} else {
int k;
for (k = 0; k < 16; k++)
dst[k] = src1[k] ^ src2[k];
}
}
extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
#if defined(DHD_DEBUG) || defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || \
defined(WLMSG_ASSOC)
extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char* buf, int len);
extern int bcm_format_hex(char *str, const void *bytes, int len);
extern void prhex(const char *msg, uchar *buf, uint len);
#endif
extern char *bcm_brev_str(uint32 brev, char *buf);
extern void printbig(char *buf);
extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
extern const char *bcmerrorstr(int bcmerror);
typedef uint32 mbool;
#define mboolset(mb, bit) ((mb) |= (bit))
#define mboolclr(mb, bit) ((mb) &= ~(bit))
#define mboolisset(mb, bit) (((mb) & (bit)) != 0)
#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
extern uint8 bcm_mw_to_qdbm(uint16 mw);
struct fielddesc {
const char *nameandfmt;
uint32 offset;
uint32 len;
};
extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
extern void bcm_inc_bytes(uchar *num, int num_bytes, uint8 amount);
extern int bcm_cmp_bytes(uchar *arg1, uchar *arg2, uint8 nbytes);
extern void bcm_print_bytes(char *name, const uchar *cdata, int len);
typedef uint32 (*bcmutl_rdreg_rtn)(void *arg0, uint arg1, uint32 offset);
extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0, uint arg1, struct fielddesc *str,
char *buf, uint32 bufsize);
extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
#if defined(WLTINYDUMP) || defined(WLMSG_INFORM) || defined(WLMSG_ASSOC) || \
defined(WLMSG_PRPKT) || defined(WLMSG_WSEC)
extern int bcm_format_ssid(char* buf, const uchar ssid[], uint ssid_len);
#endif
#define SSID_FMT_BUF_LEN ((4 * DOT11_MAX_SSID_LEN) + 1)
#ifdef __cplusplus
}
#endif
#endif

154
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/*
* Misc utility routines for WL and Apps
* This header file housing the define and function prototype use by
* both the wl driver, tools & Apps.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: bcmwifi.h,v 1.15.30.4 2010/03/10 20:10:52 Exp $
*/
#ifndef _bcmwifi_h_
#define _bcmwifi_h_
typedef uint16 chanspec_t;
#define CH_UPPER_SB 0x01
#define CH_LOWER_SB 0x02
#define CH_EWA_VALID 0x04
#define CH_20MHZ_APART 4
#define CH_10MHZ_APART 2
#define CH_5MHZ_APART 1
#define CH_MAX_2G_CHANNEL 14
#define WLC_MAX_2G_CHANNEL CH_MAX_2G_CHANNEL
#define MAXCHANNEL 224
#define WL_CHANSPEC_CHAN_MASK 0x00ff
#define WL_CHANSPEC_CHAN_SHIFT 0
#define WL_CHANSPEC_CTL_SB_MASK 0x0300
#define WL_CHANSPEC_CTL_SB_SHIFT 8
#define WL_CHANSPEC_CTL_SB_LOWER 0x0100
#define WL_CHANSPEC_CTL_SB_UPPER 0x0200
#define WL_CHANSPEC_CTL_SB_NONE 0x0300
#define WL_CHANSPEC_BW_MASK 0x0C00
#define WL_CHANSPEC_BW_SHIFT 10
#define WL_CHANSPEC_BW_10 0x0400
#define WL_CHANSPEC_BW_20 0x0800
#define WL_CHANSPEC_BW_40 0x0C00
#define WL_CHANSPEC_BAND_MASK 0xf000
#define WL_CHANSPEC_BAND_SHIFT 12
#define WL_CHANSPEC_BAND_5G 0x1000
#define WL_CHANSPEC_BAND_2G 0x2000
#define INVCHANSPEC 255
#define WF_CHAN_FACTOR_2_4_G 4814
#define WF_CHAN_FACTOR_5_G 10000
#define WF_CHAN_FACTOR_4_G 8000
#define LOWER_20_SB(channel) ((channel > CH_10MHZ_APART) ? (channel - CH_10MHZ_APART) : 0)
#define UPPER_20_SB(channel) ((channel < (MAXCHANNEL - CH_10MHZ_APART)) ? \
(channel + CH_10MHZ_APART) : 0)
#define CHSPEC_WLCBANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX)
#define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
WL_CHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
#define NEXT_20MHZ_CHAN(channel) ((channel < (MAXCHANNEL - CH_20MHZ_APART)) ? \
(channel + CH_20MHZ_APART) : 0)
#define CH40MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
WL_CHANSPEC_BAND_5G))
#define CHSPEC_CHANNEL(chspec) ((uint8)(chspec & WL_CHANSPEC_CHAN_MASK))
#define CHSPEC_BAND(chspec) (chspec & WL_CHANSPEC_BAND_MASK)
#ifdef WL20MHZ_ONLY
#define CHSPEC_CTL_SB(chspec) WL_CHANSPEC_CTL_SB_NONE
#define CHSPEC_BW(chspec) WL_CHANSPEC_BW_20
#define CHSPEC_IS10(chspec) 0
#define CHSPEC_IS20(chspec) 1
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) 0
#endif
#else
#define CHSPEC_CTL_SB(chspec) (chspec & WL_CHANSPEC_CTL_SB_MASK)
#define CHSPEC_BW(chspec) (chspec & WL_CHANSPEC_BW_MASK)
#define CHSPEC_IS10(chspec) ((chspec & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
#define CHSPEC_IS20(chspec) ((chspec & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
#endif
#endif
#define CHSPEC_IS5G(chspec) ((chspec & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
#define CHSPEC_IS2G(chspec) ((chspec & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
#define CHSPEC_SB_NONE(chspec) ((chspec & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
#define CHSPEC_SB_UPPER(chspec) ((chspec & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
#define CHSPEC_SB_LOWER(chspec) ((chspec & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
#define CHSPEC_CTL_CHAN(chspec) ((CHSPEC_SB_LOWER(chspec)) ? \
(LOWER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
(UPPER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))))
#define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G((chspec))? WLC_BAND_5G: WLC_BAND_2G)
#define CHANSPEC_STR_LEN 8
#define WLC_MAXRATE 108
#define WLC_RATE_1M 2
#define WLC_RATE_2M 4
#define WLC_RATE_5M5 11
#define WLC_RATE_11M 22
#define WLC_RATE_6M 12
#define WLC_RATE_9M 18
#define WLC_RATE_12M 24
#define WLC_RATE_18M 36
#define WLC_RATE_24M 48
#define WLC_RATE_36M 72
#define WLC_RATE_48M 96
#define WLC_RATE_54M 108
#define WLC_2G_25MHZ_OFFSET 5
extern char * wf_chspec_ntoa(chanspec_t chspec, char *buf);
extern chanspec_t wf_chspec_aton(char *a);
extern int wf_mhz2channel(uint freq, uint start_factor);
extern int wf_channel2mhz(uint channel, uint start_factor);
#endif

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/*
* Definitions for ioctls to access DHD iovars.
* Based on wlioctl.h (for Broadcom 802.11abg driver).
* (Moves towards generic ioctls for BCM drivers/iovars.)
*
* Definitions subject to change without notice.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: dhdioctl.h,v 13.7.8.1.4.1.16.5 2010/05/21 21:49:38 Exp $
*/
#ifndef _dhdioctl_h_
#define _dhdioctl_h_
#include <typedefs.h>
/* require default structure packing */
#define BWL_DEFAULT_PACKING
#include <packed_section_start.h>
/* Linux network driver ioctl encoding */
typedef struct dhd_ioctl {
uint cmd; /* common ioctl definition */
void *buf; /* pointer to user buffer */
uint len; /* length of user buffer */
bool set; /* get or set request (optional) */
uint used; /* bytes read or written (optional) */
uint needed; /* bytes needed (optional) */
uint driver; /* to identify target driver */
} dhd_ioctl_t;
/* per-driver magic numbers */
#define DHD_IOCTL_MAGIC 0x00444944
/* bump this number if you change the ioctl interface */
#define DHD_IOCTL_VERSION 1
#define DHD_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
#define DHD_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
/* common ioctl definitions */
#define DHD_GET_MAGIC 0
#define DHD_GET_VERSION 1
#define DHD_GET_VAR 2
#define DHD_SET_VAR 3
/* message levels */
#define DHD_ERROR_VAL 0x0001
#define DHD_TRACE_VAL 0x0002
#define DHD_INFO_VAL 0x0004
#define DHD_DATA_VAL 0x0008
#define DHD_CTL_VAL 0x0010
#define DHD_TIMER_VAL 0x0020
#define DHD_HDRS_VAL 0x0040
#define DHD_BYTES_VAL 0x0080
#define DHD_INTR_VAL 0x0100
#define DHD_LOG_VAL 0x0200
#define DHD_GLOM_VAL 0x0400
#define DHD_EVENT_VAL 0x0800
#define DHD_BTA_VAL 0x1000
#define DHD_ISCAN_VAL 0x2000
#ifdef SDTEST
/* For pktgen iovar */
typedef struct dhd_pktgen {
uint version; /* To allow structure change tracking */
uint freq; /* Max ticks between tx/rx attempts */
uint count; /* Test packets to send/rcv each attempt */
uint print; /* Print counts every <print> attempts */
uint total; /* Total packets (or bursts) */
uint minlen; /* Minimum length of packets to send */
uint maxlen; /* Maximum length of packets to send */
uint numsent; /* Count of test packets sent */
uint numrcvd; /* Count of test packets received */
uint numfail; /* Count of test send failures */
uint mode; /* Test mode (type of test packets) */
uint stop; /* Stop after this many tx failures */
} dhd_pktgen_t;
/* Version in case structure changes */
#define DHD_PKTGEN_VERSION 2
/* Type of test packets to use */
#define DHD_PKTGEN_ECHO 1 /* Send echo requests */
#define DHD_PKTGEN_SEND 2 /* Send discard packets */
#define DHD_PKTGEN_RXBURST 3 /* Request dongle send N packets */
#define DHD_PKTGEN_RECV 4 /* Continuous rx from continuous tx dongle */
#endif /* SDTEST */
/* Enter idle immediately (no timeout) */
#define DHD_IDLE_IMMEDIATE (-1)
/* Values for idleclock iovar: other values are the sd_divisor to use when idle */
#define DHD_IDLE_ACTIVE 0 /* Do not request any SD clock change when idle */
#define DHD_IDLE_STOP (-1) /* Request SD clock be stopped (and use SD1 mode) */
/* require default structure packing */
#include <packed_section_end.h>
#endif /* _dhdioctl_h_ */

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drivers/net/wireless/bcm4329_245/include/epivers.h Normal file
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/*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: epivers.h.in,v 13.25 2005/10/28 18:35:33 Exp $
*
*/
#ifndef _epivers_h_
#define _epivers_h_
#define EPI_MAJOR_VERSION 4
#define EPI_MINOR_VERSION 218
#define EPI_RC_NUMBER 245
#define EPI_INCREMENTAL_NUMBER 0
#define EPI_BUILD_NUMBER 0
#define EPI_VERSION 4, 218, 245, 0
#define EPI_VERSION_NUM 0x04daf500
#define EPI_VERSION_STR "4.218.245.0"
#define EPI_ROUTER_VERSION_STR "4.219.245.0"
#endif

34
drivers/net/wireless/bcm4329_245/include/hndpmu.h Normal file
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/*
* HND SiliconBackplane PMU support.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: hndpmu.h,v 13.14.4.3.4.3.8.7 2010/04/09 13:20:51 Exp $
*/
#ifndef _hndpmu_h_
#define _hndpmu_h_
extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on);
extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength);
#endif /* _hndpmu_h_ */

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drivers/net/wireless/bcm4329_245/include/hndrte_armtrap.h Normal file
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/*
* HNDRTE arm trap handling.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: hndrte_armtrap.h,v 13.3.196.2 2010/07/15 19:06:11 Exp $
*/
#ifndef _hndrte_armtrap_h
#define _hndrte_armtrap_h
/* ARM trap handling */
/* Trap types defined by ARM (see arminc.h) */
/* Trap locations in lo memory */
#define TRAP_STRIDE 4
#define FIRST_TRAP TR_RST
#define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
#if defined(__ARM_ARCH_4T__)
#define MAX_TRAP_TYPE (TR_FIQ + 1)
#elif defined(__ARM_ARCH_7M__)
#define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
#endif /* __ARM_ARCH_7M__ */
/* The trap structure is defined here as offsets for assembly */
#define TR_TYPE 0x00
#define TR_EPC 0x04
#define TR_CPSR 0x08
#define TR_SPSR 0x0c
#define TR_REGS 0x10
#define TR_REG(n) (TR_REGS + (n) * 4)
#define TR_SP TR_REG(13)
#define TR_LR TR_REG(14)
#define TR_PC TR_REG(15)
#define TRAP_T_SIZE 80
#ifndef _LANGUAGE_ASSEMBLY
#include <typedefs.h>
typedef struct _trap_struct {
uint32 type;
uint32 epc;
uint32 cpsr;
uint32 spsr;
uint32 r0;
uint32 r1;
uint32 r2;
uint32 r3;
uint32 r4;
uint32 r5;
uint32 r6;
uint32 r7;
uint32 r8;
uint32 r9;
uint32 r10;
uint32 r11;
uint32 r12;
uint32 r13;
uint32 r14;
uint32 pc;
} trap_t;
#endif /* !_LANGUAGE_ASSEMBLY */
#endif /* _hndrte_armtrap_h */

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drivers/net/wireless/bcm4329_245/include/hndrte_cons.h Normal file
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/*
* Console support for hndrte.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: hndrte_cons.h,v 13.1.2.4 2010/07/15 19:06:11 Exp $
*/
#include <typedefs.h>
#define CBUF_LEN (128)
#define LOG_BUF_LEN 1024
typedef struct {
uint32 buf; /* Can't be pointer on (64-bit) hosts */
uint buf_size;
uint idx;
char *_buf_compat; /* Redundant pointer for backward compat. */
} hndrte_log_t;
typedef struct {
/* Virtual UART
* When there is no UART (e.g. Quickturn), the host should write a complete
* input line directly into cbuf and then write the length into vcons_in.
* This may also be used when there is a real UART (at risk of conflicting with
* the real UART). vcons_out is currently unused.
*/
volatile uint vcons_in;
volatile uint vcons_out;
/* Output (logging) buffer
* Console output is written to a ring buffer log_buf at index log_idx.
* The host may read the output when it sees log_idx advance.
* Output will be lost if the output wraps around faster than the host polls.
*/
hndrte_log_t log;
/* Console input line buffer
* Characters are read one at a time into cbuf until <CR> is received, then
* the buffer is processed as a command line. Also used for virtual UART.
*/
uint cbuf_idx;
char cbuf[CBUF_LEN];
} hndrte_cons_t;

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drivers/net/wireless/bcm4329_245/include/hndsoc.h Normal file
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/*
* Broadcom HND chip & on-chip-interconnect-related definitions.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: hndsoc.h,v 13.3.10.3 2008/08/06 03:43:25 Exp $
*/
#ifndef _HNDSOC_H
#define _HNDSOC_H
/* Include the soci specific files */
#include <sbconfig.h>
#include <aidmp.h>
/*
* SOC Interconnect Address Map.
* All regions may not exist on all chips.
*/
#define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
#define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
#define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
#define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
#ifndef SI_MAXCORES
#define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software
* convenience and could be changed if we
* make any larger chips
*/
#endif
#define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
#define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
#define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
#define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
#define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
#define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
#define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
#define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
#define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
#define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
#define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
#define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
#define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */
#define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
#define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
* (2 ZettaBytes), low 32 bits
*/
#define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
* (2 ZettaBytes), high 32 bits
*/
/* core codes */
#define NODEV_CORE_ID 0x700 /* Invalid coreid */
#define CC_CORE_ID 0x800 /* chipcommon core */
#define ILINE20_CORE_ID 0x801 /* iline20 core */
#define SRAM_CORE_ID 0x802 /* sram core */
#define SDRAM_CORE_ID 0x803 /* sdram core */
#define PCI_CORE_ID 0x804 /* pci core */
#define MIPS_CORE_ID 0x805 /* mips core */
#define ENET_CORE_ID 0x806 /* enet mac core */
#define CODEC_CORE_ID 0x807 /* v90 codec core */
#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
#define ADSL_CORE_ID 0x809 /* ADSL core */
#define ILINE100_CORE_ID 0x80a /* iline100 core */
#define IPSEC_CORE_ID 0x80b /* ipsec core */
#define UTOPIA_CORE_ID 0x80c /* utopia core */
#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
#define SOCRAM_CORE_ID 0x80e /* internal memory core */
#define MEMC_CORE_ID 0x80f /* memc sdram core */
#define OFDM_CORE_ID 0x810 /* OFDM phy core */
#define EXTIF_CORE_ID 0x811 /* external interface core */
#define D11_CORE_ID 0x812 /* 802.11 MAC core */
#define APHY_CORE_ID 0x813 /* 802.11a phy core */
#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
#define MIPS33_CORE_ID 0x816 /* mips3302 core */
#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
#define SDIOH_CORE_ID 0x81b /* sdio host core */
#define ROBO_CORE_ID 0x81c /* roboswitch core */
#define ATA100_CORE_ID 0x81d /* parallel ATA core */
#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
#define PCIE_CORE_ID 0x820 /* pci express core */
#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
#define PMU_CORE_ID 0x827 /* PMU core */
#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
#define SDIOD_CORE_ID 0x829 /* SDIO device core */
#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
#define QNPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
#define SC_CORE_ID 0x831 /* shared common core */
#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
#define SPIH_CORE_ID 0x833 /* SPI host core */
#define I2S_CORE_ID 0x834 /* I2S core */
#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
* unused address ranges
*/
/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
* and chipcommon being the first core:
*/
#define SI_CC_IDX 0
/* SOC Interconnect types (aka chip types) */
#define SOCI_SB 0
#define SOCI_AI 1
/* Common core control flags */
#define SICF_BIST_EN 0x8000
#define SICF_PME_EN 0x4000
#define SICF_CORE_BITS 0x3ffc
#define SICF_FGC 0x0002
#define SICF_CLOCK_EN 0x0001
/* Common core status flags */
#define SISF_BIST_DONE 0x8000
#define SISF_BIST_ERROR 0x4000
#define SISF_GATED_CLK 0x2000
#define SISF_DMA64 0x1000
#define SISF_CORE_BITS 0x0fff
/* A register that is common to all cores to
* communicate w/PMU regarding clock control.
*/
#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
/* clk_ctl_st register */
#define CCS_FORCEALP 0x00000001 /* force ALP request */
#define CCS_FORCEHT 0x00000002 /* force HT request */
#define CCS_FORCEILP 0x00000004 /* force ILP request */
#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
#define CCS_HTAVAIL 0x00020000 /* HT is available */
#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
/* Not really related to SOC Interconnect, but a couple of software
* conventions for the use the flash space:
*/
/* Minumum amount of flash we support */
#define FLASH_MIN 0x00020000 /* Minimum flash size */
/* A boot/binary may have an embedded block that describes its size */
#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
#define BISZ_TXTST_IDX 1 /* 1: text start */
#define BISZ_TXTEND_IDX 2 /* 2: text end */
#define BISZ_DATAST_IDX 3 /* 3: data start */
#define BISZ_DATAEND_IDX 4 /* 4: data end */
#define BISZ_BSSST_IDX 5 /* 5: bss start */
#define BISZ_BSSEND_IDX 6 /* 6: bss end */
#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
#endif /* _HNDSOC_H */

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/*
* Linux OS Independent Layer
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: linux_osl.h,v 13.131.30.8 2010/04/26 05:42:18 Exp $
*/
#ifndef _linux_osl_h_
#define _linux_osl_h_
#include <typedefs.h>
#include <linuxver.h>
#ifdef __GNUC__
#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
#if GCC_VERSION > 30100
#define ASSERT(exp) do {} while (0)
#else
#define ASSERT(exp)
#endif
#endif
#define OSL_DELAY(usec) osl_delay(usec)
extern void osl_delay(uint usec);
#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
osl_pcmcia_read_attr((osh), (offset), (buf), (size))
#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
osl_pcmcia_write_attr((osh), (offset), (buf), (size))
extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
#define OSL_PCI_READ_CONFIG(osh, offset, size) \
osl_pci_read_config((osh), (offset), (size))
#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
osl_pci_write_config((osh), (offset), (size), (val))
extern uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size);
extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
extern uint osl_pci_bus(osl_t *osh);
extern uint osl_pci_slot(osl_t *osh);
typedef struct {
bool pkttag;
uint pktalloced;
bool mmbus;
pktfree_cb_fn_t tx_fn;
void *tx_ctx;
} osl_pubinfo_t;
extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag);
extern void osl_detach(osl_t *osh);
#define PKTFREESETCB(osh, _tx_fn, _tx_ctx) \
do { \
((osl_pubinfo_t*)osh)->tx_fn = _tx_fn; \
((osl_pubinfo_t*)osh)->tx_ctx = _tx_ctx; \
} while (0)
#define BUS_SWAP32(v) (v)
#define MALLOC(osh, size) osl_malloc((osh), (size))
#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
#define MALLOCED(osh) osl_malloced((osh))
#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
extern void *osl_malloc(osl_t *osh, uint size);
extern void osl_mfree(osl_t *osh, void *addr, uint size);
extern uint osl_malloced(osl_t *osh);
extern uint osl_malloc_failed(osl_t *osh);
#define DMA_CONSISTENT_ALIGN PAGE_SIZE
#define DMA_ALLOC_CONSISTENT(osh, size, pap, dmah, alignbits) \
osl_dma_alloc_consistent((osh), (size), (pap))
#define DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \
osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
#define DMA_TX 1
#define DMA_RX 2
#define DMA_MAP(osh, va, size, direction, p, dmah) \
osl_dma_map((osh), (va), (size), (direction))
#define DMA_UNMAP(osh, pa, size, direction, p, dmah) \
osl_dma_unmap((osh), (pa), (size), (direction))
extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
#define OSL_DMADDRWIDTH(osh, addrwidth) do {} while (0)
#include <bcmsdh.h>
#define OSL_WRITE_REG(osh, r, v) (bcmsdh_reg_write(NULL, (uintptr)(r), sizeof(*(r)), (v)))
#define OSL_READ_REG(osh, r) (bcmsdh_reg_read(NULL, (uintptr)(r), sizeof(*(r))))
#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) if (((osl_pubinfo_t*)(osh))->mmbus) \
mmap_op else bus_op
#define SELECT_BUS_READ(osh, mmap_op, bus_op) (((osl_pubinfo_t*)(osh))->mmbus) ? \
mmap_op : bus_op
#ifndef printf
#define printf(fmt, args...) printk(fmt, ## args)
#endif
#include <linux/kernel.h>
#include <linux/string.h>
#ifndef IL_BIGENDIAN
#define R_REG(osh, r) (\
SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
readl((volatile uint32*)(r)), OSL_READ_REG(osh, r)) \
)
#define W_REG(osh, r, v) do { \
SELECT_BUS_WRITE(osh, \
switch (sizeof(*(r))) { \
case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
}, \
(OSL_WRITE_REG(osh, r, v))); \
} while (0)
#else
#define R_REG(osh, r) (\
SELECT_BUS_READ(osh, \
({ \
__typeof(*(r)) __osl_v; \
switch (sizeof(*(r))) { \
case sizeof(uint8): __osl_v = \
readb((volatile uint8*)((uintptr)(r)^3)); break; \
case sizeof(uint16): __osl_v = \
readw((volatile uint16*)((uintptr)(r)^2)); break; \
case sizeof(uint32): __osl_v = \
readl((volatile uint32*)(r)); break; \
} \
__osl_v; \
}), \
OSL_READ_REG(osh, r)) \
)
#define W_REG(osh, r, v) do { \
SELECT_BUS_WRITE(osh, \
switch (sizeof(*(r))) { \
case sizeof(uint8): writeb((uint8)(v), \
(volatile uint8*)((uintptr)(r)^3)); break; \
case sizeof(uint16): writew((uint16)(v), \
(volatile uint16*)((uintptr)(r)^2)); break; \
case sizeof(uint32): writel((uint32)(v), \
(volatile uint32*)(r)); break; \
}, \
(OSL_WRITE_REG(osh, r, v))); \
} while (0)
#endif
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
#define bcopy(src, dst, len) memcpy((dst), (src), (len))
#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
#define bzero(b, len) memset((b), '\0', (len))
#define OSL_UNCACHED(va) ((void*)va)
#if defined(__i386__)
#define OSL_GETCYCLES(x) rdtscl((x))
#else
#define OSL_GETCYCLES(x) ((x) = 0)
#endif
#define BUSPROBE(val, addr) ({ (val) = R_REG(NULL, (addr)); 0; })
#if !defined(CONFIG_MMC_MSM7X00A)
#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
#else
#define REG_MAP(pa, size) (void *)(0)
#endif
#define REG_UNMAP(va) iounmap((va))
#define R_SM(r) *(r)
#define W_SM(r, v) (*(r) = (v))
#define BZERO_SM(r, len) memset((r), '\0', (len))
#define PKTGET(osh, len, send) osl_pktget((osh), (len))
#define PKTFREE(osh, skb, send) osl_pktfree((osh), (skb), (send))
#ifdef DHD_USE_STATIC_BUF
#define PKTGET_STATIC(osh, len, send) osl_pktget_static((osh), (len))
#define PKTFREE_STATIC(osh, skb, send) osl_pktfree_static((osh), (skb), (send))
#endif
#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
#define PKTHEADROOM(osh, skb) (PKTDATA(osh, skb)-(((struct sk_buff*)(skb))->head))
#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
#define PKTSETNEXT(osh, skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
#define PKTTAG(skb) ((void*)(((struct sk_buff*)(skb))->cb))
#define PKTALLOCED(osh) ((osl_pubinfo_t *)(osh))->pktalloced
#define PKTSETPOOL(osh, skb, x, y) do {} while (0)
#define PKTPOOL(osh, skb) FALSE
#define PKTPOOLLEN(osh, pktp) (0)
#define PKTPOOLAVAIL(osh, pktp) (0)
#define PKTPOOLADD(osh, pktp, p) BCME_ERROR
#define PKTPOOLGET(osh, pktp) NULL
#define PKTLIST_DUMP(osh, buf)
extern void *osl_pktget(osl_t *osh, uint len);
extern void osl_pktfree(osl_t *osh, void *skb, bool send);
extern void *osl_pktget_static(osl_t *osh, uint len);
extern void osl_pktfree_static(osl_t *osh, void *skb, bool send);
extern void *osl_pktdup(osl_t *osh, void *skb);
static INLINE void *
osl_pkt_frmnative(osl_pubinfo_t *osh, struct sk_buff *skb)
{
struct sk_buff *nskb;
if (osh->pkttag)
bzero((void*)skb->cb, OSL_PKTTAG_SZ);
for (nskb = skb; nskb; nskb = nskb->next) {
osh->pktalloced++;
}
return (void *)skb;
}
#define PKTFRMNATIVE(osh, skb) osl_pkt_frmnative(((osl_pubinfo_t *)osh), (struct sk_buff*)(skb))
static INLINE struct sk_buff *
osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt)
{
struct sk_buff *nskb;
if (osh->pkttag)
bzero(((struct sk_buff*)pkt)->cb, OSL_PKTTAG_SZ);
for (nskb = (struct sk_buff *)pkt; nskb; nskb = nskb->next) {
osh->pktalloced--;
}
return (struct sk_buff *)pkt;
}
#define PKTTONATIVE(osh, pkt) osl_pkt_tonative((osl_pubinfo_t *)(osh), (pkt))
#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
#define PKTSUMNEEDED(skb) (((struct sk_buff*)(skb))->ip_summed == CHECKSUM_HW)
#define PKTSETSUMGOOD(skb, x) (((struct sk_buff*)(skb))->ip_summed = \
((x) ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE))
#define PKTSHARED(skb) (((struct sk_buff*)(skb))->cloned)
#define OSL_ERROR(bcmerror) osl_error(bcmerror)
extern int osl_error(int bcmerror);
#define PKTBUFSZ 2048
#define OSL_SYSUPTIME() ((uint32)jiffies * (1000 / HZ))
#endif

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/*
* Linux-specific abstractions to gain some independence from linux kernel versions.
* Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: linuxver.h,v 13.38.8.1.8.6 2010/04/29 05:00:46 Exp $
*/
#ifndef _linuxver_h_
#define _linuxver_h_
#include <linux/version.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#include <linux/config.h>
#else
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
#include <generated/autoconf.h>
#else
#include <linux/autoconf.h>
#endif
#endif
#include <linux/module.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
#ifdef __UNDEF_NO_VERSION__
#undef __NO_VERSION__
#else
#define __NO_VERSION__
#endif
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
#define module_param_string(_name_, _string_, _size_, _perm_) \
MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
#include <linux/malloc.h>
#else
#include <linux/slab.h>
#endif
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
#undef IP_TOS
#endif
#include <asm/io.h>
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
#include <linux/workqueue.h>
#else
#include <linux/tqueue.h>
#ifndef work_struct
#define work_struct tq_struct
#endif
#ifndef INIT_WORK
#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
#endif
#ifndef schedule_work
#define schedule_work(_work) schedule_task((_work))
#endif
#ifndef flush_scheduled_work
#define flush_scheduled_work() flush_scheduled_tasks()
#endif
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func)
#else
#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func, _data)
typedef void (*work_func_t)(void *work);
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#ifndef IRQ_NONE
typedef void irqreturn_t;
#define IRQ_NONE
#define IRQ_HANDLED
#define IRQ_RETVAL(x)
#endif
#else
typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
#define IRQF_SHARED SA_SHIRQ
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17)
#ifdef CONFIG_NET_RADIO
#define CONFIG_WIRELESS_EXT
#endif
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 67)
#ifndef SANDGATE2G
#define MOD_INC_USE_COUNT
#endif
#endif
#ifndef __exit
#define __exit
#endif
#ifndef __devexit
#define __devexit
#endif
#ifndef __devinit
#define __devinit __init
#endif
#ifndef __devinitdata
#define __devinitdata
#endif
#ifndef __devexit_p
#define __devexit_p(x) x
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
#define pci_get_drvdata(dev) (dev)->sysdata
#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
struct pci_device_id {
unsigned int vendor, device;
unsigned int subvendor, subdevice;
unsigned int class, class_mask;
unsigned long driver_data;
};
struct pci_driver {
struct list_head node;
char *name;
const struct pci_device_id *id_table;
int (*probe)(struct pci_dev *dev,
const struct pci_device_id *id);
void (*remove)(struct pci_dev *dev);
void (*suspend)(struct pci_dev *dev);
void (*resume)(struct pci_dev *dev);
};
#define MODULE_DEVICE_TABLE(type, name)
#define PCI_ANY_ID (~0)
#define pci_module_init pci_register_driver
extern int pci_register_driver(struct pci_driver *drv);
extern void pci_unregister_driver(struct pci_driver *drv);
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18))
#define pci_module_init pci_register_driver
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
#ifdef MODULE
#define module_init(x) int init_module(void) { return x(); }
#define module_exit(x) void cleanup_module(void) { x(); }
#else
#define module_init(x) __initcall(x);
#define module_exit(x) __exitcall(x);
#endif
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
#define list_for_each(pos, head) \
for (pos = (head)->next; pos != (head); pos = pos->next)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
#define pci_enable_device(dev) do { } while (0)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
#define net_device device
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
#ifndef PCI_DMA_TODEVICE
#define PCI_DMA_TODEVICE 1
#define PCI_DMA_FROMDEVICE 2
#endif
typedef u32 dma_addr_t;
static inline int get_order(unsigned long size)
{
int order;
size = (size-1) >> (PAGE_SHIFT-1);
order = -1;
do {
size >>= 1;
order++;
} while (size);
return order;
}
static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t *dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC | GFP_DMA;
ret = (void *)__get_free_pages(gfp, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
*dma_handle = virt_to_bus(ret);
}
return ret;
}
static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
free_pages((unsigned long)vaddr, get_order(size));
}
#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
#define pci_unmap_single(cookie, address, size, dir)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
#define dev_kfree_skb_any(a) dev_kfree_skb(a)
#define netif_down(dev) do { (dev)->start = 0; } while (0)
#ifndef _COMPAT_NETDEVICE_H
#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
#define netif_wake_queue(dev) \
do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
static inline void netif_start_queue(struct net_device *dev)
{
dev->tbusy = 0;
dev->interrupt = 0;
dev->start = 1;
}
#define netif_queue_stopped(dev) (dev)->tbusy
#define netif_running(dev) (dev)->start
#endif
#define netif_device_attach(dev) netif_start_queue(dev)
#define netif_device_detach(dev) netif_stop_queue(dev)
#define tasklet_struct tq_struct
static inline void tasklet_schedule(struct tasklet_struct *tasklet)
{
queue_task(tasklet, &tq_immediate);
mark_bh(IMMEDIATE_BH);
}
static inline void tasklet_init(struct tasklet_struct *tasklet,
void (*func)(unsigned long),
unsigned long data)
{
tasklet->next = NULL;
tasklet->sync = 0;
tasklet->routine = (void (*)(void *))func;
tasklet->data = (void *)data;
}
#define tasklet_kill(tasklet) { do {} while (0); }
#define del_timer_sync(timer) del_timer(timer)
#else
#define netif_down(dev)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
#define PREPARE_TQUEUE(_tq, _routine, _data) \
do { \
(_tq)->routine = _routine; \
(_tq)->data = _data; \
} while (0)
#define INIT_TQUEUE(_tq, _routine, _data) \
do { \
INIT_LIST_HEAD(&(_tq)->list); \
(_tq)->sync = 0; \
PREPARE_TQUEUE((_tq), (_routine), (_data)); \
} while (0)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
static inline int
pci_save_state(struct pci_dev *dev, u32 *buffer)
{
int i;
if (buffer) {
for (i = 0; i < 16; i++)
pci_read_config_dword(dev, i * 4, &buffer[i]);
}
return 0;
}
static inline int
pci_restore_state(struct pci_dev *dev, u32 *buffer)
{
int i;
if (buffer) {
for (i = 0; i < 16; i++)
pci_write_config_dword(dev, i * 4, buffer[i]);
}
else {
for (i = 0; i < 6; i ++)
pci_write_config_dword(dev,
PCI_BASE_ADDRESS_0 + (i * 4),
pci_resource_start(dev, i));
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
return 0;
}
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
#ifndef SET_MODULE_OWNER
#define SET_MODULE_OWNER(dev) do {} while (0)
#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
#else
#define OLD_MOD_INC_USE_COUNT do {} while (0)
#define OLD_MOD_DEC_USE_COUNT do {} while (0)
#endif
#else
#ifndef SET_MODULE_OWNER
#define SET_MODULE_OWNER(dev) do {} while (0)
#endif
#ifndef MOD_INC_USE_COUNT
#define MOD_INC_USE_COUNT do {} while (0)
#endif
#ifndef MOD_DEC_USE_COUNT
#define MOD_DEC_USE_COUNT do {} while (0)
#endif
#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
#endif
#ifndef SET_NETDEV_DEV
#define SET_NETDEV_DEV(net, pdev) do {} while (0)
#endif
#ifndef HAVE_FREE_NETDEV
#define free_netdev(dev) kfree(dev)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#define af_packet_priv data
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11)
#define DRV_SUSPEND_STATE_TYPE pm_message_t
#else
#define DRV_SUSPEND_STATE_TYPE uint32
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
#define CHECKSUM_HW CHECKSUM_PARTIAL
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
#define KILL_PROC(nr, sig) \
{ \
struct task_struct *tsk; \
struct pid *pid; \
pid = find_get_pid((pid_t)nr); \
tsk = pid_task(pid, PIDTYPE_PID); \
if (tsk) send_sig(sig, tsk, 1); \
}
#else
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && (LINUX_VERSION_CODE <= \
KERNEL_VERSION(2, 6, 30))
#define KILL_PROC(pid, sig) \
{ \
struct task_struct *tsk; \
tsk = find_task_by_vpid(pid); \
if (tsk) send_sig(sig, tsk, 1); \
}
#else
#define KILL_PROC(pid, sig) \
{ \
kill_proc(pid, sig, 1); \
}
#endif
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#define netdev_priv(dev) dev->priv
#endif
#endif

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/*
* Command line options parser.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: miniopt.h,v 1.1.6.2 2009/01/14 23:52:48 Exp $
*/
#ifndef MINI_OPT_H
#define MINI_OPT_H
#ifdef __cplusplus
extern "C" {
#endif
/* ---- Include Files ---------------------------------------------------- */
/* ---- Constants and Types ---------------------------------------------- */
#define MINIOPT_MAXKEY 128 /* Max options */
typedef struct miniopt {
/* These are persistent after miniopt_init() */
const char* name; /* name for prompt in error strings */
const char* flags; /* option chars that take no args */
bool longflags; /* long options may be flags */
bool opt_end; /* at end of options (passed a "--") */
/* These are per-call to miniopt() */
int consumed; /* number of argv entries cosumed in
* the most recent call to miniopt()
*/
bool positional;
bool good_int; /* 'val' member is the result of a sucessful
* strtol conversion of the option value
*/
char opt;
char key[MINIOPT_MAXKEY];
char* valstr; /* positional param, or value for the option,
* or null if the option had
* no accompanying value
*/
uint uval; /* strtol translation of valstr */
int val; /* strtol translation of valstr */
} miniopt_t;
void miniopt_init(miniopt_t *t, const char* name, const char* flags, bool longflags);
int miniopt(miniopt_t *t, char **argv);
/* ---- Variable Externs ------------------------------------------------- */
/* ---- Function Prototypes ---------------------------------------------- */
#ifdef __cplusplus
}
#endif
#endif /* MINI_OPT_H */

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/*
* Trace messages sent over HBUS
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: msgtrace.h,v 1.1.2.4 2009/01/27 04:09:40 Exp $
*/
#ifndef _MSGTRACE_H
#define _MSGTRACE_H
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
#define MSGTRACE_VERSION 1
/* Message trace header */
typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr {
uint8 version;
uint8 spare;
uint16 len; /* Len of the trace */
uint32 seqnum; /* Sequence number of message. Useful if the messsage has been lost
* because of DMA error or a bus reset (ex: SDIO Func2)
*/
uint32 discarded_bytes; /* Number of discarded bytes because of trace overflow */
uint32 discarded_printf; /* Number of discarded printf because of trace overflow */
} BWL_POST_PACKED_STRUCT msgtrace_hdr_t;
#define MSGTRACE_HDRLEN sizeof(msgtrace_hdr_t)
/* The hbus driver generates traces when sending a trace message. This causes endless traces.
* This flag must be set to TRUE in any hbus traces. The flag is reset in the function msgtrace_put.
* This prevents endless traces but generates hasardous lost of traces only in bus device code.
* It is recommendat to set this flag in macro SD_TRACE but not in SD_ERROR for avoiding missing
* hbus error traces. hbus error trace should not generates endless traces.
*/
extern bool msgtrace_hbus_trace;
typedef void (*msgtrace_func_send_t)(void *hdl1, void *hdl2, uint8 *hdr,
uint16 hdrlen, uint8 *buf, uint16 buflen);
extern void msgtrace_sent(void);
extern void msgtrace_put(char *buf, int count);
extern void msgtrace_init(void *hdl1, void *hdl2, msgtrace_func_send_t func_send);
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _MSGTRACE_H */

55
drivers/net/wireless/bcm4329_245/include/osl.h Normal file
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/*
* OS Abstraction Layer
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: osl.h,v 13.37.32.1 2008/11/20 00:51:15 Exp $
*/
#ifndef _osl_h_
#define _osl_h_
typedef struct osl_info osl_t;
typedef struct osl_dmainfo osldma_t;
#define OSL_PKTTAG_SZ 32
typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status);
#include <linux_osl.h>
#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
#ifndef AND_REG
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
#endif
#ifndef OR_REG
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
#endif
#endif

54
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/*
* Declare directives for structure packing. No padding will be provided
* between the members of packed structures, and therefore, there is no
* guarantee that structure members will be aligned.
*
* Declaring packed structures is compiler specific. In order to handle all
* cases, packed structures should be delared as:
*
* #include <packed_section_start.h>
*
* typedef BWL_PRE_PACKED_STRUCT struct foobar_t {
* some_struct_members;
* } BWL_POST_PACKED_STRUCT foobar_t;
*
* #include <packed_section_end.h>
*
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: packed_section_end.h,v 1.1.6.3 2008/12/10 00:27:54 Exp $
*/
#ifdef BWL_PACKED_SECTION
#undef BWL_PACKED_SECTION
#else
#error "BWL_PACKED_SECTION is NOT defined!"
#endif
#undef BWL_PRE_PACKED_STRUCT
#undef BWL_POST_PACKED_STRUCT

61
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/*
* Declare directives for structure packing. No padding will be provided
* between the members of packed structures, and therefore, there is no
* guarantee that structure members will be aligned.
*
* Declaring packed structures is compiler specific. In order to handle all
* cases, packed structures should be delared as:
*
* #include <packed_section_start.h>
*
* typedef BWL_PRE_PACKED_STRUCT struct foobar_t {
* some_struct_members;
* } BWL_POST_PACKED_STRUCT foobar_t;
*
* #include <packed_section_end.h>
*
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: packed_section_start.h,v 1.1.6.3 2008/12/10 00:27:54 Exp $
*/
#ifdef BWL_PACKED_SECTION
#error "BWL_PACKED_SECTION is already defined!"
#else
#define BWL_PACKED_SECTION
#endif
#if defined(__GNUC__)
#define BWL_PRE_PACKED_STRUCT
#define BWL_POST_PACKED_STRUCT __attribute__((packed))
#elif defined(__CC_ARM)
#define BWL_PRE_PACKED_STRUCT __packed
#define BWL_POST_PACKED_STRUCT
#else
#error "Unknown compiler!"
#endif

52
drivers/net/wireless/bcm4329_245/include/pcicfg.h Normal file
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/*
* pcicfg.h: PCI configuration constants and structures.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: pcicfg.h,v 1.41.12.3 2008/06/26 22:49:41 Exp $
*/
#ifndef _h_pcicfg_
#define _h_pcicfg_
#define PCI_CFG_VID 0
#define PCI_CFG_CMD 4
#define PCI_CFG_REV 8
#define PCI_CFG_BAR0 0x10
#define PCI_CFG_BAR1 0x14
#define PCI_BAR0_WIN 0x80
#define PCI_INT_STATUS 0x90
#define PCI_INT_MASK 0x94
#define PCIE_EXTCFG_OFFSET 0x100
#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)
#define PCI_BAR0_PCISBR_OFFSET (4 * 1024)
#define PCI_BAR0_WINSZ (16 * 1024)
#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
#define PCI_16KB0_CCREGS_OFFSET (12 * 1024)
#define PCI_16KBB0_WINSZ (16 * 1024)
#endif

1433
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131
drivers/net/wireless/bcm4329_245/include/proto/802.11e.h Normal file
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/*
* 802.11e protocol header file
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: 802.11e.h,v 1.5.56.1 2008/11/20 00:51:18 Exp $
*/
#ifndef _802_11e_H_
#define _802_11e_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
/* WME Traffic Specification (TSPEC) element */
#define WME_TSPEC_HDR_LEN 2 /* WME TSPEC header length */
#define WME_TSPEC_BODY_OFF 2 /* WME TSPEC body offset */
#define WME_CATEGORY_CODE_OFFSET 0 /* WME Category code offset */
#define WME_ACTION_CODE_OFFSET 1 /* WME Action code offset */
#define WME_TOKEN_CODE_OFFSET 2 /* WME Token code offset */
#define WME_STATUS_CODE_OFFSET 3 /* WME Status code offset */
BWL_PRE_PACKED_STRUCT struct tsinfo {
uint8 octets[3];
} BWL_POST_PACKED_STRUCT;
typedef struct tsinfo tsinfo_t;
/* 802.11e TSPEC IE */
typedef BWL_PRE_PACKED_STRUCT struct tspec {
uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
uint8 type; /* WME_TYPE */
uint8 subtype; /* WME_SUBTYPE_TSPEC */
uint8 version; /* WME_VERSION */
tsinfo_t tsinfo; /* TS Info bit field */
uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
uint32 min_srv_interval; /* Minimum Service Interval (us) */
uint32 max_srv_interval; /* Maximum Service Interval (us) */
uint32 inactivity_interval; /* Inactivity Interval (us) */
uint32 suspension_interval; /* Suspension Interval (us) */
uint32 srv_start_time; /* Service Start Time (us) */
uint32 min_data_rate; /* Minimum Data Rate (bps) */
uint32 mean_data_rate; /* Mean Data Rate (bps) */
uint32 peak_data_rate; /* Peak Data Rate (bps) */
uint32 max_burst_size; /* Maximum Burst Size (bytes) */
uint32 delay_bound; /* Delay Bound (us) */
uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
uint16 surplus_bw; /* Surplus Bandwidth Allowance (range 1.0-8.0) */
uint16 medium_time; /* Medium Time (32 us/s periods) */
} BWL_POST_PACKED_STRUCT tspec_t;
#define WME_TSPEC_LEN (sizeof(tspec_t)) /* not including 2-bytes of header */
/* ts_info */
/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
#define TS_INFO_TID_SHIFT 1 /* TS info. TID shift */
#define TS_INFO_TID_MASK (0xf << TS_INFO_TID_SHIFT) /* TS info. TID mask */
#define TS_INFO_CONTENTION_SHIFT 7 /* TS info. contention shift */
#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT) /* TS info. contention mask */
#define TS_INFO_DIRECTION_SHIFT 5 /* TS info. direction shift */
#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT) /* TS info. direction mask */
#define TS_INFO_PSB_SHIFT 2 /* TS info. PSB bit Shift */
#define TS_INFO_PSB_MASK (1 << TS_INFO_PSB_SHIFT) /* TS info. PSB mask */
#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT) /* TS info. uplink */
#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT) /* TS info. downlink */
#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT) /* TS info. bidirectional */
#define TS_INFO_USER_PRIO_SHIFT 3 /* TS info. user priority shift */
/* TS info. user priority mask */
#define TS_INFO_USER_PRIO_MASK (0x7 << TS_INFO_USER_PRIO_SHIFT)
/* Macro to get/set bit(s) field in TSINFO */
#define WLC_CAC_GET_TID(pt) ((((pt).octets[0]) & TS_INFO_TID_MASK) >> TS_INFO_TID_SHIFT)
#define WLC_CAC_GET_DIR(pt) ((((pt).octets[0]) & \
TS_INFO_DIRECTION_MASK) >> TS_INFO_DIRECTION_SHIFT)
#define WLC_CAC_GET_PSB(pt) ((((pt).octets[1]) & TS_INFO_PSB_MASK) >> TS_INFO_PSB_SHIFT)
#define WLC_CAC_GET_USER_PRIO(pt) ((((pt).octets[1]) & \
TS_INFO_USER_PRIO_MASK) >> TS_INFO_USER_PRIO_SHIFT)
#define WLC_CAC_SET_TID(pt, id) ((((pt).octets[0]) & (~TS_INFO_TID_MASK)) | \
((id) << TS_INFO_TID_SHIFT))
#define WLC_CAC_SET_USER_PRIO(pt, prio) ((((pt).octets[0]) & (~TS_INFO_USER_PRIO_MASK)) | \
((prio) << TS_INFO_USER_PRIO_SHIFT))
/* 802.11e QBSS Load IE */
#define QBSS_LOAD_IE_LEN 5 /* QBSS Load IE length */
#define QBSS_LOAD_AAC_OFF 3 /* AAC offset in IE */
#define CAC_ADDTS_RESP_TIMEOUT 300 /* default ADDTS response timeout in ms */
/* 802.11e ADDTS status code */
#define DOT11E_STATUS_ADMISSION_ACCEPTED 0 /* TSPEC Admission accepted status */
#define DOT11E_STATUS_ADDTS_INVALID_PARAM 1 /* TSPEC invalid parameter status */
#define DOT11E_STATUS_ADDTS_REFUSED_NSBW 3 /* ADDTS refused (non-sufficient BW) */
#define DOT11E_STATUS_ADDTS_REFUSED_AWHILE 47 /* ADDTS refused but could retry later */
/* 802.11e DELTS status code */
#define DOT11E_STATUS_QSTA_LEAVE_QBSS 36 /* STA leave QBSS */
#define DOT11E_STATUS_END_TS 37 /* END TS */
#define DOT11E_STATUS_UNKNOWN_TS 38 /* UNKNOWN TS */
#define DOT11E_STATUS_QSTA_REQ_TIMEOUT 39 /* STA ADDTS request timeout */
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _802_11e_CAC_H_ */

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/*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* Fundamental types and constants relating to 802.1D
*
* $Id: 802.1d.h,v 9.3 2007/04/10 21:33:06 Exp $
*/
#ifndef _802_1_D_
#define _802_1_D_
#define PRIO_8021D_NONE 2
#define PRIO_8021D_BK 1
#define PRIO_8021D_BE 0
#define PRIO_8021D_EE 3
#define PRIO_8021D_CL 4
#define PRIO_8021D_VI 5
#define PRIO_8021D_VO 6
#define PRIO_8021D_NC 7
#define MAXPRIO 7
#define NUMPRIO (MAXPRIO + 1)
#define ALLPRIO -1
#define PRIO2PREC(prio) \
(((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? ((prio^2)) : (prio))
#endif

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/*
* Broadcom Ethernettype protocol definitions
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmeth.h,v 9.9.46.1 2008/11/20 00:51:20 Exp $
*/
#ifndef _BCMETH_H_
#define _BCMETH_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
#include <packed_section_start.h>
#define BCMILCP_SUBTYPE_RATE 1
#define BCMILCP_SUBTYPE_LINK 2
#define BCMILCP_SUBTYPE_CSA 3
#define BCMILCP_SUBTYPE_LARQ 4
#define BCMILCP_SUBTYPE_VENDOR 5
#define BCMILCP_SUBTYPE_FLH 17
#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
#define BCMILCP_SUBTYPE_CERT 32770
#define BCMILCP_SUBTYPE_SES 32771
#define BCMILCP_BCM_SUBTYPE_RESERVED 0
#define BCMILCP_BCM_SUBTYPE_EVENT 1
#define BCMILCP_BCM_SUBTYPE_SES 2
#define BCMILCP_BCM_SUBTYPE_DPT 4
#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
typedef BWL_PRE_PACKED_STRUCT struct bcmeth_hdr
{
uint16 subtype;
uint16 length;
uint8 version;
uint8 oui[3];
uint16 usr_subtype;
} BWL_POST_PACKED_STRUCT bcmeth_hdr_t;
#include <packed_section_end.h>
#endif

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/*
* Broadcom Event protocol definitions
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
*
* Dependencies: proto/bcmeth.h
*
* $Id: bcmevent.h,v 9.34.4.1.20.16 2009/09/25 23:52:38 Exp $
*
*/
#ifndef _BCMEVENT_H_
#define _BCMEVENT_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
#include <packed_section_start.h>
#define BCM_EVENT_MSG_VERSION 1
#define BCM_MSG_IFNAME_MAX 16
#define WLC_EVENT_MSG_LINK 0x01
#define WLC_EVENT_MSG_FLUSHTXQ 0x02
#define WLC_EVENT_MSG_GROUP 0x04
typedef BWL_PRE_PACKED_STRUCT struct
{
uint16 version;
uint16 flags;
uint32 event_type;
uint32 status;
uint32 reason;
uint32 auth_type;
uint32 datalen;
struct ether_addr addr;
char ifname[BCM_MSG_IFNAME_MAX];
} BWL_POST_PACKED_STRUCT wl_event_msg_t;
typedef BWL_PRE_PACKED_STRUCT struct bcm_event {
struct ether_header eth;
bcmeth_hdr_t bcm_hdr;
wl_event_msg_t event;
} BWL_POST_PACKED_STRUCT bcm_event_t;
#define BCM_MSG_LEN (sizeof(bcm_event_t) - sizeof(bcmeth_hdr_t) - sizeof(struct ether_header))
#define WLC_E_SET_SSID 0
#define WLC_E_JOIN 1
#define WLC_E_START 2
#define WLC_E_AUTH 3
#define WLC_E_AUTH_IND 4
#define WLC_E_DEAUTH 5
#define WLC_E_DEAUTH_IND 6
#define WLC_E_ASSOC 7
#define WLC_E_ASSOC_IND 8
#define WLC_E_REASSOC 9
#define WLC_E_REASSOC_IND 10
#define WLC_E_DISASSOC 11
#define WLC_E_DISASSOC_IND 12
#define WLC_E_QUIET_START 13
#define WLC_E_QUIET_END 14
#define WLC_E_BEACON_RX 15
#define WLC_E_LINK 16
#define WLC_E_MIC_ERROR 17
#define WLC_E_NDIS_LINK 18
#define WLC_E_ROAM 19
#define WLC_E_TXFAIL 20
#define WLC_E_PMKID_CACHE 21
#define WLC_E_RETROGRADE_TSF 22
#define WLC_E_PRUNE 23
#define WLC_E_AUTOAUTH 24
#define WLC_E_EAPOL_MSG 25
#define WLC_E_SCAN_COMPLETE 26
#define WLC_E_ADDTS_IND 27
#define WLC_E_DELTS_IND 28
#define WLC_E_BCNSENT_IND 29
#define WLC_E_BCNRX_MSG 30
#define WLC_E_BCNLOST_MSG 31
#define WLC_E_ROAM_PREP 32
#define WLC_E_PFN_NET_FOUND 33
#define WLC_E_PFN_NET_LOST 34
#define WLC_E_RESET_COMPLETE 35
#define WLC_E_JOIN_START 36
#define WLC_E_ROAM_START 37
#define WLC_E_ASSOC_START 38
#define WLC_E_IBSS_ASSOC 39
#define WLC_E_RADIO 40
#define WLC_E_PSM_WATCHDOG 41
#define WLC_E_PROBREQ_MSG 44
#define WLC_E_SCAN_CONFIRM_IND 45
#define WLC_E_PSK_SUP 46
#define WLC_E_COUNTRY_CODE_CHANGED 47
#define WLC_E_EXCEEDED_MEDIUM_TIME 48
#define WLC_E_ICV_ERROR 49
#define WLC_E_UNICAST_DECODE_ERROR 50
#define WLC_E_MULTICAST_DECODE_ERROR 51
#define WLC_E_TRACE 52
#define WLC_E_IF 54
#define WLC_E_RSSI 56
#define WLC_E_PFN_SCAN_COMPLETE 57
#define WLC_E_ACTION_FRAME 58
#define WLC_E_ACTION_FRAME_COMPLETE 59
#define WLC_E_ESCAN_RESULT 69
#define WLC_E_WAKE_EVENT 70
#define WLC_E_LAST 71
#define WLC_E_STATUS_SUCCESS 0
#define WLC_E_STATUS_FAIL 1
#define WLC_E_STATUS_TIMEOUT 2
#define WLC_E_STATUS_NO_NETWORKS 3
#define WLC_E_STATUS_ABORT 4
#define WLC_E_STATUS_NO_ACK 5
#define WLC_E_STATUS_UNSOLICITED 6
#define WLC_E_STATUS_ATTEMPT 7
#define WLC_E_STATUS_PARTIAL 8
#define WLC_E_STATUS_NEWSCAN 9
#define WLC_E_STATUS_NEWASSOC 10
#define WLC_E_STATUS_11HQUIET 11
#define WLC_E_STATUS_SUPPRESS 12
#define WLC_E_STATUS_NOCHANS 13
#define WLC_E_STATUS_CCXFASTRM 14
#define WLC_E_STATUS_CS_ABORT 15
#define WLC_E_REASON_INITIAL_ASSOC 0
#define WLC_E_REASON_LOW_RSSI 1
#define WLC_E_REASON_DEAUTH 2
#define WLC_E_REASON_DISASSOC 3
#define WLC_E_REASON_BCNS_LOST 4
#define WLC_E_REASON_FAST_ROAM_FAILED 5
#define WLC_E_REASON_DIRECTED_ROAM 6
#define WLC_E_REASON_TSPEC_REJECTED 7
#define WLC_E_REASON_BETTER_AP 8
#define WLC_E_PRUNE_ENCR_MISMATCH 1
#define WLC_E_PRUNE_BCAST_BSSID 2
#define WLC_E_PRUNE_MAC_DENY 3
#define WLC_E_PRUNE_MAC_NA 4
#define WLC_E_PRUNE_REG_PASSV 5
#define WLC_E_PRUNE_SPCT_MGMT 6
#define WLC_E_PRUNE_RADAR 7
#define WLC_E_RSN_MISMATCH 8
#define WLC_E_PRUNE_NO_COMMON_RATES 9
#define WLC_E_PRUNE_BASIC_RATES 10
#define WLC_E_PRUNE_CIPHER_NA 12
#define WLC_E_PRUNE_KNOWN_STA 13
#define WLC_E_PRUNE_WDS_PEER 15
#define WLC_E_PRUNE_QBSS_LOAD 16
#define WLC_E_PRUNE_HOME_AP 17
#define WLC_E_SUP_OTHER 0
#define WLC_E_SUP_DECRYPT_KEY_DATA 1
#define WLC_E_SUP_BAD_UCAST_WEP128 2
#define WLC_E_SUP_BAD_UCAST_WEP40 3
#define WLC_E_SUP_UNSUP_KEY_LEN 4
#define WLC_E_SUP_PW_KEY_CIPHER 5
#define WLC_E_SUP_MSG3_TOO_MANY_IE 6
#define WLC_E_SUP_MSG3_IE_MISMATCH 7
#define WLC_E_SUP_NO_INSTALL_FLAG 8
#define WLC_E_SUP_MSG3_NO_GTK 9
#define WLC_E_SUP_GRP_KEY_CIPHER 10
#define WLC_E_SUP_GRP_MSG1_NO_GTK 11
#define WLC_E_SUP_GTK_DECRYPT_FAIL 12
#define WLC_E_SUP_SEND_FAIL 13
#define WLC_E_SUP_DEAUTH 14
#define WLC_E_SUP_WPA_PSK_TMO 15
#define WLC_E_IF_ADD 1
#define WLC_E_IF_DEL 2
#include <packed_section_end.h>
#endif

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/*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* Fundamental constants relating to IP Protocol
*
* $Id: bcmip.h,v 9.16.186.4 2009/01/27 04:25:25 Exp $
*/
#ifndef _bcmip_h_
#define _bcmip_h_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
#include <packed_section_start.h>
#define IP_VER_OFFSET 0x0
#define IP_VER_MASK 0xf0
#define IP_VER_SHIFT 4
#define IP_VER_4 4
#define IP_VER_6 6
#define IP_VER(ip_body) \
((((uint8 *)(ip_body))[IP_VER_OFFSET] & IP_VER_MASK) >> IP_VER_SHIFT)
#define IP_PROT_ICMP 0x1
#define IP_PROT_TCP 0x6
#define IP_PROT_UDP 0x11
#define IPV4_VER_HL_OFFSET 0
#define IPV4_TOS_OFFSET 1
#define IPV4_PKTLEN_OFFSET 2
#define IPV4_PKTFLAG_OFFSET 6
#define IPV4_PROT_OFFSET 9
#define IPV4_CHKSUM_OFFSET 10
#define IPV4_SRC_IP_OFFSET 12
#define IPV4_DEST_IP_OFFSET 16
#define IPV4_OPTIONS_OFFSET 20
#define IPV4_VER_MASK 0xf0
#define IPV4_VER_SHIFT 4
#define IPV4_HLEN_MASK 0x0f
#define IPV4_HLEN(ipv4_body) (4 * (((uint8 *)(ipv4_body))[IPV4_VER_HL_OFFSET] & IPV4_HLEN_MASK))
#define IPV4_ADDR_LEN 4
#define IPV4_ADDR_NULL(a) ((((uint8 *)(a))[0] | ((uint8 *)(a))[1] | \
((uint8 *)(a))[2] | ((uint8 *)(a))[3]) == 0)
#define IPV4_ADDR_BCAST(a) ((((uint8 *)(a))[0] & ((uint8 *)(a))[1] & \
((uint8 *)(a))[2] & ((uint8 *)(a))[3]) == 0xff)
#define IPV4_TOS_DSCP_MASK 0xfc
#define IPV4_TOS_DSCP_SHIFT 2
#define IPV4_TOS(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_TOS_OFFSET])
#define IPV4_TOS_PREC_MASK 0xe0
#define IPV4_TOS_PREC_SHIFT 5
#define IPV4_TOS_LOWDELAY 0x10
#define IPV4_TOS_THROUGHPUT 0x8
#define IPV4_TOS_RELIABILITY 0x4
#define IPV4_PROT(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_PROT_OFFSET])
#define IPV4_FRAG_RESV 0x8000
#define IPV4_FRAG_DONT 0x4000
#define IPV4_FRAG_MORE 0x2000
#define IPV4_FRAG_OFFSET_MASK 0x1fff
#define IPV4_ADDR_STR_LEN 16
BWL_PRE_PACKED_STRUCT struct ipv4_addr {
uint8 addr[IPV4_ADDR_LEN];
} BWL_POST_PACKED_STRUCT;
BWL_PRE_PACKED_STRUCT struct ipv4_hdr {
uint8 version_ihl;
uint8 tos;
uint16 tot_len;
uint16 id;
uint16 frag;
uint8 ttl;
uint8 prot;
uint16 hdr_chksum;
uint8 src_ip[IPV4_ADDR_LEN];
uint8 dst_ip[IPV4_ADDR_LEN];
} BWL_POST_PACKED_STRUCT;
#define IPV6_PAYLOAD_LEN_OFFSET 4
#define IPV6_NEXT_HDR_OFFSET 6
#define IPV6_HOP_LIMIT_OFFSET 7
#define IPV6_SRC_IP_OFFSET 8
#define IPV6_DEST_IP_OFFSET 24
#define IPV6_TRAFFIC_CLASS(ipv6_body) \
(((((uint8 *)(ipv6_body))[0] & 0x0f) << 4) | \
((((uint8 *)(ipv6_body))[1] & 0xf0) >> 4))
#define IPV6_FLOW_LABEL(ipv6_body) \
(((((uint8 *)(ipv6_body))[1] & 0x0f) << 16) | \
(((uint8 *)(ipv6_body))[2] << 8) | \
(((uint8 *)(ipv6_body))[3]))
#define IPV6_PAYLOAD_LEN(ipv6_body) \
((((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 0] << 8) | \
((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 1])
#define IPV6_NEXT_HDR(ipv6_body) \
(((uint8 *)(ipv6_body))[IPV6_NEXT_HDR_OFFSET])
#define IPV6_PROT(ipv6_body) IPV6_NEXT_HDR(ipv6_body)
#define IPV6_ADDR_LEN 16
#ifndef IP_TOS
#define IP_TOS(ip_body) \
(IP_VER(ip_body) == IP_VER_4 ? IPV4_TOS(ip_body) : \
IP_VER(ip_body) == IP_VER_6 ? IPV6_TRAFFIC_CLASS(ip_body) : 0)
#endif
#include <packed_section_end.h>
#endif

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/*
* 802.1x EAPOL definitions
*
* See
* IEEE Std 802.1X-2001
* IEEE 802.1X RADIUS Usage Guidelines
*
* Copyright (C) 2002 Broadcom Corporation
*
* $Id: eapol.h,v 9.18.260.1.2.1.6.6 2009/04/08 05:00:08 Exp $
*/
#ifndef _eapol_h_
#define _eapol_h_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
#define AKW_BLOCK_LEN 8 /* The only def we need here */
/* EAPOL for 802.3/Ethernet */
typedef struct {
struct ether_header eth; /* 802.3/Ethernet header */
unsigned char version; /* EAPOL protocol version */
unsigned char type; /* EAPOL type */
unsigned short length; /* Length of body */
unsigned char body[1]; /* Body (optional) */
} eapol_header_t;
#define EAPOL_HEADER_LEN 18
/* EAPOL version */
#define WPA2_EAPOL_VERSION 2
#define WPA_EAPOL_VERSION 1
#define LEAP_EAPOL_VERSION 1
#define SES_EAPOL_VERSION 1
/* EAPOL types */
#define EAP_PACKET 0
#define EAPOL_START 1
#define EAPOL_LOGOFF 2
#define EAPOL_KEY 3
#define EAPOL_ASF 4
/* EAPOL-Key types */
#define EAPOL_RC4_KEY 1
#define EAPOL_WPA2_KEY 2 /* 802.11i/WPA2 */
#define EAPOL_WPA_KEY 254 /* WPA */
/* RC4 EAPOL-Key header field sizes */
#define EAPOL_KEY_REPLAY_LEN 8
#define EAPOL_KEY_IV_LEN 16
#define EAPOL_KEY_SIG_LEN 16
/* RC4 EAPOL-Key */
typedef BWL_PRE_PACKED_STRUCT struct {
unsigned char type; /* Key Descriptor Type */
unsigned short length; /* Key Length (unaligned) */
unsigned char replay[EAPOL_KEY_REPLAY_LEN]; /* Replay Counter */
unsigned char iv[EAPOL_KEY_IV_LEN]; /* Key IV */
unsigned char index; /* Key Flags & Index */
unsigned char signature[EAPOL_KEY_SIG_LEN]; /* Key Signature */
unsigned char key[1]; /* Key (optional) */
} BWL_POST_PACKED_STRUCT eapol_key_header_t;
#define EAPOL_KEY_HEADER_LEN 44
/* RC4 EAPOL-Key flags */
#define EAPOL_KEY_FLAGS_MASK 0x80
#define EAPOL_KEY_BROADCAST 0
#define EAPOL_KEY_UNICAST 0x80
/* RC4 EAPOL-Key index */
#define EAPOL_KEY_INDEX_MASK 0x7f
/* WPA/802.11i/WPA2 EAPOL-Key header field sizes */
#define EAPOL_WPA_KEY_REPLAY_LEN 8
#define EAPOL_WPA_KEY_NONCE_LEN 32
#define EAPOL_WPA_KEY_IV_LEN 16
#define EAPOL_WPA_KEY_ID_LEN 8
#define EAPOL_WPA_KEY_RSC_LEN 8
#define EAPOL_WPA_KEY_MIC_LEN 16
#define EAPOL_WPA_KEY_DATA_LEN (EAPOL_WPA_MAX_KEY_SIZE + AKW_BLOCK_LEN)
#define EAPOL_WPA_MAX_KEY_SIZE 32
/* WPA EAPOL-Key */
typedef BWL_PRE_PACKED_STRUCT struct {
unsigned char type; /* Key Descriptor Type */
unsigned short key_info; /* Key Information (unaligned) */
unsigned short key_len; /* Key Length (unaligned) */
unsigned char replay[EAPOL_WPA_KEY_REPLAY_LEN]; /* Replay Counter */
unsigned char nonce[EAPOL_WPA_KEY_NONCE_LEN]; /* Nonce */
unsigned char iv[EAPOL_WPA_KEY_IV_LEN]; /* Key IV */
unsigned char rsc[EAPOL_WPA_KEY_RSC_LEN]; /* Key RSC */
unsigned char id[EAPOL_WPA_KEY_ID_LEN]; /* WPA:Key ID, 802.11i/WPA2: Reserved */
unsigned char mic[EAPOL_WPA_KEY_MIC_LEN]; /* Key MIC */
unsigned short data_len; /* Key Data Length */
unsigned char data[EAPOL_WPA_KEY_DATA_LEN]; /* Key data */
} BWL_POST_PACKED_STRUCT eapol_wpa_key_header_t;
#define EAPOL_WPA_KEY_LEN 95
/* WPA/802.11i/WPA2 KEY KEY_INFO bits */
#define WPA_KEY_DESC_V1 0x01
#define WPA_KEY_DESC_V2 0x02
#define WPA_KEY_PAIRWISE 0x08
#define WPA_KEY_INSTALL 0x40
#define WPA_KEY_ACK 0x80
#define WPA_KEY_MIC 0x100
#define WPA_KEY_SECURE 0x200
#define WPA_KEY_ERROR 0x400
#define WPA_KEY_REQ 0x800
/* WPA-only KEY KEY_INFO bits */
#define WPA_KEY_INDEX_0 0x00
#define WPA_KEY_INDEX_1 0x10
#define WPA_KEY_INDEX_2 0x20
#define WPA_KEY_INDEX_3 0x30
#define WPA_KEY_INDEX_MASK 0x30
#define WPA_KEY_INDEX_SHIFT 0x04
/* 802.11i/WPA2-only KEY KEY_INFO bits */
#define WPA_KEY_ENCRYPTED_DATA 0x1000
/* Key Data encapsulation */
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 type;
uint8 length;
uint8 oui[3];
uint8 subtype;
uint8 data[1];
} BWL_POST_PACKED_STRUCT eapol_wpa2_encap_data_t;
#define EAPOL_WPA2_ENCAP_DATA_HDR_LEN 6
#define WPA2_KEY_DATA_SUBTYPE_GTK 1
#define WPA2_KEY_DATA_SUBTYPE_STAKEY 2
#define WPA2_KEY_DATA_SUBTYPE_MAC 3
#define WPA2_KEY_DATA_SUBTYPE_PMKID 4
/* GTK encapsulation */
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 flags;
uint8 reserved;
uint8 gtk[EAPOL_WPA_MAX_KEY_SIZE];
} BWL_POST_PACKED_STRUCT eapol_wpa2_key_gtk_encap_t;
#define EAPOL_WPA2_KEY_GTK_ENCAP_HDR_LEN 2
#define WPA2_GTK_INDEX_MASK 0x03
#define WPA2_GTK_INDEX_SHIFT 0x00
#define WPA2_GTK_TRANSMIT 0x04
/* STAKey encapsulation */
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 reserved[2];
uint8 mac[ETHER_ADDR_LEN];
uint8 stakey[EAPOL_WPA_MAX_KEY_SIZE];
} BWL_POST_PACKED_STRUCT eapol_wpa2_key_stakey_encap_t;
#define WPA2_KEY_DATA_PAD 0xdd
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _eapol_h_ */

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/*
* From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: ethernet.h,v 9.45.56.5 2010/02/22 22:04:36 Exp $
*/
#ifndef _NET_ETHERNET_H_
#define _NET_ETHERNET_H_
#ifndef _TYPEDEFS_H_
#include "typedefs.h"
#endif
#include <packed_section_start.h>
#define ETHER_ADDR_LEN 6
#define ETHER_TYPE_LEN 2
#define ETHER_CRC_LEN 4
#define ETHER_HDR_LEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
#define ETHER_MIN_LEN 64
#define ETHER_MIN_DATA 46
#define ETHER_MAX_LEN 1518
#define ETHER_MAX_DATA 1500
#define ETHER_TYPE_MIN 0x0600
#define ETHER_TYPE_IP 0x0800
#define ETHER_TYPE_ARP 0x0806
#define ETHER_TYPE_8021Q 0x8100
#define ETHER_TYPE_BRCM 0x886c
#define ETHER_TYPE_802_1X 0x888e
#define ETHER_TYPE_WAI 0x88b4
#ifdef BCMWPA2
#define ETHER_TYPE_802_1X_PREAUTH 0x88c7
#endif
#define ETHER_BRCM_SUBTYPE_LEN 4
#define ETHER_BRCM_CRAM 1
#define ETHER_DEST_OFFSET (0 * ETHER_ADDR_LEN)
#define ETHER_SRC_OFFSET (1 * ETHER_ADDR_LEN)
#define ETHER_TYPE_OFFSET (2 * ETHER_ADDR_LEN)
#define ETHER_IS_VALID_LEN(foo) \
((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
#ifndef __INCif_etherh
BWL_PRE_PACKED_STRUCT struct ether_header {
uint8 ether_dhost[ETHER_ADDR_LEN];
uint8 ether_shost[ETHER_ADDR_LEN];
uint16 ether_type;
} BWL_POST_PACKED_STRUCT;
BWL_PRE_PACKED_STRUCT struct ether_addr {
uint8 octet[ETHER_ADDR_LEN];
} BWL_POST_PACKED_STRUCT;
#endif
#define ETHER_SET_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] | 2))
#define ETHER_IS_LOCALADDR(ea) (((uint8 *)(ea))[0] & 2)
#define ETHER_CLR_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & 0xd))
#define ETHER_TOGGLE_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] ^ 2))
#define ETHER_SET_UNICAST(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & ~1))
#define ETHER_ISMULTI(ea) (((const uint8 *)(ea))[0] & 1)
#define ether_cmp(a, b) (!(((short*)a)[0] == ((short*)b)[0]) | \
!(((short*)a)[1] == ((short*)b)[1]) | \
!(((short*)a)[2] == ((short*)b)[2]))
#define ether_copy(s, d) { \
((short*)d)[0] = ((short*)s)[0]; \
((short*)d)[1] = ((short*)s)[1]; \
((short*)d)[2] = ((short*)s)[2]; }
static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
static const struct ether_addr ether_null = {{0, 0, 0, 0, 0, 0}};
#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
((uint8 *)(ea))[1] & \
((uint8 *)(ea))[2] & \
((uint8 *)(ea))[3] & \
((uint8 *)(ea))[4] & \
((uint8 *)(ea))[5]) == 0xff)
#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
((uint8 *)(ea))[1] | \
((uint8 *)(ea))[2] | \
((uint8 *)(ea))[3] | \
((uint8 *)(ea))[4] | \
((uint8 *)(ea))[5]) == 0)
#include <packed_section_end.h>
#endif

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/*
* SD-SPI Protocol Standard
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sdspi.h,v 9.1.20.1 2008/05/06 22:59:19 Exp $
*/
#define SPI_START_M BITFIELD_MASK(1) /* Bit [31] - Start Bit */
#define SPI_START_S 31
#define SPI_DIR_M BITFIELD_MASK(1) /* Bit [30] - Direction */
#define SPI_DIR_S 30
#define SPI_CMD_INDEX_M BITFIELD_MASK(6) /* Bits [29:24] - Command number */
#define SPI_CMD_INDEX_S 24
#define SPI_RW_M BITFIELD_MASK(1) /* Bit [23] - Read=0, Write=1 */
#define SPI_RW_S 23
#define SPI_FUNC_M BITFIELD_MASK(3) /* Bits [22:20] - Function Number */
#define SPI_FUNC_S 20
#define SPI_RAW_M BITFIELD_MASK(1) /* Bit [19] - Read After Wr */
#define SPI_RAW_S 19
#define SPI_STUFF_M BITFIELD_MASK(1) /* Bit [18] - Stuff bit */
#define SPI_STUFF_S 18
#define SPI_BLKMODE_M BITFIELD_MASK(1) /* Bit [19] - Blockmode 1=blk */
#define SPI_BLKMODE_S 19
#define SPI_OPCODE_M BITFIELD_MASK(1) /* Bit [18] - OP Code */
#define SPI_OPCODE_S 18
#define SPI_ADDR_M BITFIELD_MASK(17) /* Bits [17:1] - Address */
#define SPI_ADDR_S 1
#define SPI_STUFF0_M BITFIELD_MASK(1) /* Bit [0] - Stuff bit */
#define SPI_STUFF0_S 0
#define SPI_RSP_START_M BITFIELD_MASK(1) /* Bit [7] - Start Bit (always 0) */
#define SPI_RSP_START_S 7
#define SPI_RSP_PARAM_ERR_M BITFIELD_MASK(1) /* Bit [6] - Parameter Error */
#define SPI_RSP_PARAM_ERR_S 6
#define SPI_RSP_RFU5_M BITFIELD_MASK(1) /* Bit [5] - RFU (Always 0) */
#define SPI_RSP_RFU5_S 5
#define SPI_RSP_FUNC_ERR_M BITFIELD_MASK(1) /* Bit [4] - Function number error */
#define SPI_RSP_FUNC_ERR_S 4
#define SPI_RSP_CRC_ERR_M BITFIELD_MASK(1) /* Bit [3] - COM CRC Error */
#define SPI_RSP_CRC_ERR_S 3
#define SPI_RSP_ILL_CMD_M BITFIELD_MASK(1) /* Bit [2] - Illegal Command error */
#define SPI_RSP_ILL_CMD_S 2
#define SPI_RSP_RFU1_M BITFIELD_MASK(1) /* Bit [1] - RFU (Always 0) */
#define SPI_RSP_RFU1_S 1
#define SPI_RSP_IDLE_M BITFIELD_MASK(1) /* Bit [0] - In idle state */
#define SPI_RSP_IDLE_S 0
/* SD-SPI Protocol Definitions */
#define SDSPI_COMMAND_LEN 6 /* Number of bytes in an SD command */
#define SDSPI_START_BLOCK 0xFE /* SD Start Block Token */
#define SDSPI_IDLE_PAD 0xFF /* SD-SPI idle value for MOSI */
#define SDSPI_START_BIT_MASK 0x80

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/*
* 802.1Q VLAN protocol definitions
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: vlan.h,v 9.4.196.2 2008/12/07 21:19:20 Exp $
*/
#ifndef _vlan_h_
#define _vlan_h_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
#include <packed_section_start.h>
#define VLAN_VID_MASK 0xfff
#define VLAN_CFI_SHIFT 12
#define VLAN_PRI_SHIFT 13
#define VLAN_PRI_MASK 7
#define VLAN_TAG_LEN 4
#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN)
#define VLAN_TPID 0x8100
struct ethervlan_header {
uint8 ether_dhost[ETHER_ADDR_LEN];
uint8 ether_shost[ETHER_ADDR_LEN];
uint16 vlan_type;
uint16 vlan_tag;
uint16 ether_type;
};
#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
#include <packed_section_end.h>
#endif

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/*
* Fundamental types and constants relating to WPA
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: wpa.h,v 1.16.166.1.20.1 2008/11/20 00:51:31 Exp $
*/
#ifndef _proto_wpa_h_
#define _proto_wpa_h_
#include <typedefs.h>
#include <proto/ethernet.h>
#include <packed_section_start.h>
#define DOT11_RC_INVALID_WPA_IE 13
#define DOT11_RC_MIC_FAILURE 14
#define DOT11_RC_4WH_TIMEOUT 15
#define DOT11_RC_GTK_UPDATE_TIMEOUT 16
#define DOT11_RC_WPA_IE_MISMATCH 17
#define DOT11_RC_INVALID_MC_CIPHER 18
#define DOT11_RC_INVALID_UC_CIPHER 19
#define DOT11_RC_INVALID_AKMP 20
#define DOT11_RC_BAD_WPA_VERSION 21
#define DOT11_RC_INVALID_WPA_CAP 22
#define DOT11_RC_8021X_AUTH_FAIL 23
#define WPA2_PMKID_LEN 16
typedef BWL_PRE_PACKED_STRUCT struct
{
uint8 tag;
uint8 length;
uint8 oui[3];
uint8 oui_type;
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT version;
} BWL_POST_PACKED_STRUCT wpa_ie_fixed_t;
#define WPA_IE_OUITYPE_LEN 4
#define WPA_IE_FIXED_LEN 8
#define WPA_IE_TAG_FIXED_LEN 6
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 tag;
uint8 length;
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT version;
} BWL_POST_PACKED_STRUCT wpa_rsn_ie_fixed_t;
#define WPA_RSN_IE_FIXED_LEN 4
#define WPA_RSN_IE_TAG_FIXED_LEN 2
typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
typedef BWL_PRE_PACKED_STRUCT struct
{
uint8 oui[3];
uint8 type;
} BWL_POST_PACKED_STRUCT wpa_suite_t, wpa_suite_mcast_t;
#define WPA_SUITE_LEN 4
typedef BWL_PRE_PACKED_STRUCT struct
{
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT count;
wpa_suite_t list[1];
} BWL_POST_PACKED_STRUCT wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
#define WPA_IE_SUITE_COUNT_LEN 2
typedef BWL_PRE_PACKED_STRUCT struct
{
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT count;
wpa_pmkid_t list[1];
} BWL_POST_PACKED_STRUCT wpa_pmkid_list_t;
#define WPA_CIPHER_NONE 0
#define WPA_CIPHER_WEP_40 1
#define WPA_CIPHER_TKIP 2
#define WPA_CIPHER_AES_OCB 3
#define WPA_CIPHER_AES_CCM 4
#define WPA_CIPHER_WEP_104 5
#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
(cipher) == WPA_CIPHER_WEP_40 || \
(cipher) == WPA_CIPHER_WEP_104 || \
(cipher) == WPA_CIPHER_TKIP || \
(cipher) == WPA_CIPHER_AES_OCB || \
(cipher) == WPA_CIPHER_AES_CCM)
#define WPA_TKIP_CM_DETECT 60
#define WPA_TKIP_CM_BLOCK 60
#define RSN_CAP_LEN 2
#define RSN_CAP_PREAUTH 0x0001
#define RSN_CAP_NOPAIRWISE 0x0002
#define RSN_CAP_PTK_REPLAY_CNTR_MASK 0x000C
#define RSN_CAP_PTK_REPLAY_CNTR_SHIFT 2
#define RSN_CAP_GTK_REPLAY_CNTR_MASK 0x0030
#define RSN_CAP_GTK_REPLAY_CNTR_SHIFT 4
#define RSN_CAP_1_REPLAY_CNTR 0
#define RSN_CAP_2_REPLAY_CNTRS 1
#define RSN_CAP_4_REPLAY_CNTRS 2
#define RSN_CAP_16_REPLAY_CNTRS 3
#define WPA_CAP_4_REPLAY_CNTRS RSN_CAP_4_REPLAY_CNTRS
#define WPA_CAP_16_REPLAY_CNTRS RSN_CAP_16_REPLAY_CNTRS
#define WPA_CAP_REPLAY_CNTR_SHIFT RSN_CAP_PTK_REPLAY_CNTR_SHIFT
#define WPA_CAP_REPLAY_CNTR_MASK RSN_CAP_PTK_REPLAY_CNTR_MASK
#define WPA_CAP_LEN RSN_CAP_LEN
#define WPA_CAP_WPA2_PREAUTH RSN_CAP_PREAUTH
#include <packed_section_end.h>
#endif

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/*
* Broadcom SiliconBackplane hardware register definitions.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sbconfig.h,v 13.67.30.1 2008/05/07 20:17:27 Exp $
*/
#ifndef _SBCONFIG_H
#define _SBCONFIG_H
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
#define SB_BUS_SIZE 0x10000
#define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
#define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE)
#define SBCONFIGOFF 0xf00
#define SBCONFIGSIZE 256
#define SBIPSFLAG 0x08
#define SBTPSFLAG 0x18
#define SBTMERRLOGA 0x48
#define SBTMERRLOG 0x50
#define SBADMATCH3 0x60
#define SBADMATCH2 0x68
#define SBADMATCH1 0x70
#define SBIMSTATE 0x90
#define SBINTVEC 0x94
#define SBTMSTATELOW 0x98
#define SBTMSTATEHIGH 0x9c
#define SBBWA0 0xa0
#define SBIMCONFIGLOW 0xa8
#define SBIMCONFIGHIGH 0xac
#define SBADMATCH0 0xb0
#define SBTMCONFIGLOW 0xb8
#define SBTMCONFIGHIGH 0xbc
#define SBBCONFIG 0xc0
#define SBBSTATE 0xc8
#define SBACTCNFG 0xd8
#define SBFLAGST 0xe8
#define SBIDLOW 0xf8
#define SBIDHIGH 0xfc
#define SBIMERRLOGA 0xea8
#define SBIMERRLOG 0xeb0
#define SBTMPORTCONNID0 0xed8
#define SBTMPORTLOCK0 0xef8
#ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _sbconfig {
uint32 PAD[2];
uint32 sbipsflag;
uint32 PAD[3];
uint32 sbtpsflag;
uint32 PAD[11];
uint32 sbtmerrloga;
uint32 PAD;
uint32 sbtmerrlog;
uint32 PAD[3];
uint32 sbadmatch3;
uint32 PAD;
uint32 sbadmatch2;
uint32 PAD;
uint32 sbadmatch1;
uint32 PAD[7];
uint32 sbimstate;
uint32 sbintvec;
uint32 sbtmstatelow;
uint32 sbtmstatehigh;
uint32 sbbwa0;
uint32 PAD;
uint32 sbimconfiglow;
uint32 sbimconfighigh;
uint32 sbadmatch0;
uint32 PAD;
uint32 sbtmconfiglow;
uint32 sbtmconfighigh;
uint32 sbbconfig;
uint32 PAD;
uint32 sbbstate;
uint32 PAD[3];
uint32 sbactcnfg;
uint32 PAD[3];
uint32 sbflagst;
uint32 PAD[3];
uint32 sbidlow;
uint32 sbidhigh;
} sbconfig_t;
#endif
#define SBIPS_INT1_MASK 0x3f
#define SBIPS_INT1_SHIFT 0
#define SBIPS_INT2_MASK 0x3f00
#define SBIPS_INT2_SHIFT 8
#define SBIPS_INT3_MASK 0x3f0000
#define SBIPS_INT3_SHIFT 16
#define SBIPS_INT4_MASK 0x3f000000
#define SBIPS_INT4_SHIFT 24
#define SBTPS_NUM0_MASK 0x3f
#define SBTPS_F0EN0 0x40
#define SBTMEL_CM 0x00000007
#define SBTMEL_CI 0x0000ff00
#define SBTMEL_EC 0x0f000000
#define SBTMEL_ME 0x80000000
#define SBIM_PC 0xf
#define SBIM_AP_MASK 0x30
#define SBIM_AP_BOTH 0x00
#define SBIM_AP_TS 0x10
#define SBIM_AP_TK 0x20
#define SBIM_AP_RSV 0x30
#define SBIM_IBE 0x20000
#define SBIM_TO 0x40000
#define SBIM_BY 0x01800000
#define SBIM_RJ 0x02000000
#define SBTML_RESET 0x0001
#define SBTML_REJ_MASK 0x0006
#define SBTML_REJ 0x0002
#define SBTML_TMPREJ 0x0004
#define SBTML_SICF_SHIFT 16
#define SBTMH_SERR 0x0001
#define SBTMH_INT 0x0002
#define SBTMH_BUSY 0x0004
#define SBTMH_TO 0x0020
#define SBTMH_SISF_SHIFT 16
#define SBBWA_TAB0_MASK 0xffff
#define SBBWA_TAB1_MASK 0xffff
#define SBBWA_TAB1_SHIFT 16
#define SBIMCL_STO_MASK 0x7
#define SBIMCL_RTO_MASK 0x70
#define SBIMCL_RTO_SHIFT 4
#define SBIMCL_CID_MASK 0xff0000
#define SBIMCL_CID_SHIFT 16
#define SBIMCH_IEM_MASK 0xc
#define SBIMCH_TEM_MASK 0x30
#define SBIMCH_TEM_SHIFT 4
#define SBIMCH_BEM_MASK 0xc0
#define SBIMCH_BEM_SHIFT 6
#define SBAM_TYPE_MASK 0x3
#define SBAM_AD64 0x4
#define SBAM_ADINT0_MASK 0xf8
#define SBAM_ADINT0_SHIFT 3
#define SBAM_ADINT1_MASK 0x1f8
#define SBAM_ADINT1_SHIFT 3
#define SBAM_ADINT2_MASK 0x1f8
#define SBAM_ADINT2_SHIFT 3
#define SBAM_ADEN 0x400
#define SBAM_ADNEG 0x800
#define SBAM_BASE0_MASK 0xffffff00
#define SBAM_BASE0_SHIFT 8
#define SBAM_BASE1_MASK 0xfffff000
#define SBAM_BASE1_SHIFT 12
#define SBAM_BASE2_MASK 0xffff0000
#define SBAM_BASE2_SHIFT 16
#define SBTMCL_CD_MASK 0xff
#define SBTMCL_CO_MASK 0xf800
#define SBTMCL_CO_SHIFT 11
#define SBTMCL_IF_MASK 0xfc0000
#define SBTMCL_IF_SHIFT 18
#define SBTMCL_IM_MASK 0x3000000
#define SBTMCL_IM_SHIFT 24
#define SBTMCH_BM_MASK 0x3
#define SBTMCH_RM_MASK 0x3
#define SBTMCH_RM_SHIFT 2
#define SBTMCH_SM_MASK 0x30
#define SBTMCH_SM_SHIFT 4
#define SBTMCH_EM_MASK 0x300
#define SBTMCH_EM_SHIFT 8
#define SBTMCH_IM_MASK 0xc00
#define SBTMCH_IM_SHIFT 10
#define SBBC_LAT_MASK 0x3
#define SBBC_MAX0_MASK 0xf0000
#define SBBC_MAX0_SHIFT 16
#define SBBC_MAX1_MASK 0xf00000
#define SBBC_MAX1_SHIFT 20
#define SBBS_SRD 0x1
#define SBBS_HRD 0x2
#define SBIDL_CS_MASK 0x3
#define SBIDL_AR_MASK 0x38
#define SBIDL_AR_SHIFT 3
#define SBIDL_SYNCH 0x40
#define SBIDL_INIT 0x80
#define SBIDL_MINLAT_MASK 0xf00
#define SBIDL_MINLAT_SHIFT 8
#define SBIDL_MAXLAT 0xf000
#define SBIDL_MAXLAT_SHIFT 12
#define SBIDL_FIRST 0x10000
#define SBIDL_CW_MASK 0xc0000
#define SBIDL_CW_SHIFT 18
#define SBIDL_TP_MASK 0xf00000
#define SBIDL_TP_SHIFT 20
#define SBIDL_IP_MASK 0xf000000
#define SBIDL_IP_SHIFT 24
#define SBIDL_RV_MASK 0xf0000000
#define SBIDL_RV_SHIFT 28
#define SBIDL_RV_2_2 0x00000000
#define SBIDL_RV_2_3 0x10000000
#define SBIDH_RC_MASK 0x000f
#define SBIDH_RCE_MASK 0x7000
#define SBIDH_RCE_SHIFT 8
#define SBCOREREV(sbidh) \
((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
#define SBIDH_CC_MASK 0x8ff0
#define SBIDH_CC_SHIFT 4
#define SBIDH_VC_MASK 0xffff0000
#define SBIDH_VC_SHIFT 16
#define SB_COMMIT 0xfd8
#define SB_VEND_BCM 0x4243
#endif

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/*
* Generic Broadcom Home Networking Division (HND) DMA engine HW interface
* This supports the following chips: BCM42xx, 44xx, 47xx .
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sbhnddma.h,v 13.11.250.5.16.1 2009/07/21 14:04:51 Exp $
*/
#ifndef _sbhnddma_h_
#define _sbhnddma_h_
typedef volatile struct {
uint32 control;
uint32 addr;
uint32 ptr;
uint32 status;
} dma32regs_t;
typedef volatile struct {
dma32regs_t xmt;
dma32regs_t rcv;
} dma32regp_t;
typedef volatile struct {
uint32 fifoaddr;
uint32 fifodatalow;
uint32 fifodatahigh;
uint32 pad;
} dma32diag_t;
typedef volatile struct {
uint32 ctrl;
uint32 addr;
} dma32dd_t;
#define D32RINGALIGN_BITS 12
#define D32MAXRINGSZ (1 << D32RINGALIGN_BITS)
#define D32RINGALIGN (1 << D32RINGALIGN_BITS)
#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
#define XC_XE ((uint32)1 << 0)
#define XC_SE ((uint32)1 << 1)
#define XC_LE ((uint32)1 << 2)
#define XC_FL ((uint32)1 << 4)
#define XC_PD ((uint32)1 << 11)
#define XC_AE ((uint32)3 << 16)
#define XC_AE_SHIFT 16
#define XP_LD_MASK 0xfff
#define XS_CD_MASK 0x0fff
#define XS_XS_MASK 0xf000
#define XS_XS_SHIFT 12
#define XS_XS_DISABLED 0x0000
#define XS_XS_ACTIVE 0x1000
#define XS_XS_IDLE 0x2000
#define XS_XS_STOPPED 0x3000
#define XS_XS_SUSP 0x4000
#define XS_XE_MASK 0xf0000
#define XS_XE_SHIFT 16
#define XS_XE_NOERR 0x00000
#define XS_XE_DPE 0x10000
#define XS_XE_DFU 0x20000
#define XS_XE_BEBR 0x30000
#define XS_XE_BEDA 0x40000
#define XS_AD_MASK 0xfff00000
#define XS_AD_SHIFT 20
#define RC_RE ((uint32)1 << 0)
#define RC_RO_MASK 0xfe
#define RC_RO_SHIFT 1
#define RC_FM ((uint32)1 << 8)
#define RC_SH ((uint32)1 << 9)
#define RC_OC ((uint32)1 << 10)
#define RC_PD ((uint32)1 << 11)
#define RC_AE ((uint32)3 << 16)
#define RC_AE_SHIFT 16
#define RP_LD_MASK 0xfff
#define RS_CD_MASK 0x0fff
#define RS_RS_MASK 0xf000
#define RS_RS_SHIFT 12
#define RS_RS_DISABLED 0x0000
#define RS_RS_ACTIVE 0x1000
#define RS_RS_IDLE 0x2000
#define RS_RS_STOPPED 0x3000
#define RS_RE_MASK 0xf0000
#define RS_RE_SHIFT 16
#define RS_RE_NOERR 0x00000
#define RS_RE_DPE 0x10000
#define RS_RE_DFO 0x20000
#define RS_RE_BEBW 0x30000
#define RS_RE_BEDA 0x40000
#define RS_AD_MASK 0xfff00000
#define RS_AD_SHIFT 20
#define FA_OFF_MASK 0xffff
#define FA_SEL_MASK 0xf0000
#define FA_SEL_SHIFT 16
#define FA_SEL_XDD 0x00000
#define FA_SEL_XDP 0x10000
#define FA_SEL_RDD 0x40000
#define FA_SEL_RDP 0x50000
#define FA_SEL_XFD 0x80000
#define FA_SEL_XFP 0x90000
#define FA_SEL_RFD 0xc0000
#define FA_SEL_RFP 0xd0000
#define FA_SEL_RSD 0xe0000
#define FA_SEL_RSP 0xf0000
#define CTRL_BC_MASK 0x1fff
#define CTRL_AE ((uint32)3 << 16)
#define CTRL_AE_SHIFT 16
#define CTRL_EOT ((uint32)1 << 28)
#define CTRL_IOC ((uint32)1 << 29)
#define CTRL_EOF ((uint32)1 << 30)
#define CTRL_SOF ((uint32)1 << 31)
#define CTRL_CORE_MASK 0x0ff00000
typedef volatile struct {
uint32 control;
uint32 ptr;
uint32 addrlow;
uint32 addrhigh;
uint32 status0;
uint32 status1;
} dma64regs_t;
typedef volatile struct {
dma64regs_t tx;
dma64regs_t rx;
} dma64regp_t;
typedef volatile struct {
uint32 fifoaddr;
uint32 fifodatalow;
uint32 fifodatahigh;
uint32 pad;
} dma64diag_t;
typedef volatile struct {
uint32 ctrl1;
uint32 ctrl2;
uint32 addrlow;
uint32 addrhigh;
} dma64dd_t;
#define D64RINGALIGN_BITS 13
#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
#define D64RINGALIGN (1 << D64RINGALIGN_BITS)
#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
#define D64_XC_XE 0x00000001
#define D64_XC_SE 0x00000002
#define D64_XC_LE 0x00000004
#define D64_XC_FL 0x00000010
#define D64_XC_PD 0x00000800
#define D64_XC_AE 0x00030000
#define D64_XC_AE_SHIFT 16
#define D64_XP_LD_MASK 0x00000fff
#define D64_XS0_CD_MASK 0x00001fff
#define D64_XS0_XS_MASK 0xf0000000
#define D64_XS0_XS_SHIFT 28
#define D64_XS0_XS_DISABLED 0x00000000
#define D64_XS0_XS_ACTIVE 0x10000000
#define D64_XS0_XS_IDLE 0x20000000
#define D64_XS0_XS_STOPPED 0x30000000
#define D64_XS0_XS_SUSP 0x40000000
#define D64_XS1_AD_MASK 0x0001ffff
#define D64_XS1_XE_MASK 0xf0000000
#define D64_XS1_XE_SHIFT 28
#define D64_XS1_XE_NOERR 0x00000000
#define D64_XS1_XE_DPE 0x10000000
#define D64_XS1_XE_DFU 0x20000000
#define D64_XS1_XE_DTE 0x30000000
#define D64_XS1_XE_DESRE 0x40000000
#define D64_XS1_XE_COREE 0x50000000
#define D64_RC_RE 0x00000001
#define D64_RC_RO_MASK 0x000000fe
#define D64_RC_RO_SHIFT 1
#define D64_RC_FM 0x00000100
#define D64_RC_SH 0x00000200
#define D64_RC_OC 0x00000400
#define D64_RC_PD 0x00000800
#define D64_RC_AE 0x00030000
#define D64_RC_AE_SHIFT 16
#define D64_RP_LD_MASK 0x00000fff
#define D64_RS0_CD_MASK 0x00001fff
#define D64_RS0_RS_MASK 0xf0000000
#define D64_RS0_RS_SHIFT 28
#define D64_RS0_RS_DISABLED 0x00000000
#define D64_RS0_RS_ACTIVE 0x10000000
#define D64_RS0_RS_IDLE 0x20000000
#define D64_RS0_RS_STOPPED 0x30000000
#define D64_RS0_RS_SUSP 0x40000000
#define D64_RS1_AD_MASK 0x0001ffff
#define D64_RS1_RE_MASK 0xf0000000
#define D64_RS1_RE_SHIFT 28
#define D64_RS1_RE_NOERR 0x00000000
#define D64_RS1_RE_DPO 0x10000000
#define D64_RS1_RE_DFU 0x20000000
#define D64_RS1_RE_DTE 0x30000000
#define D64_RS1_RE_DESRE 0x40000000
#define D64_RS1_RE_COREE 0x50000000
#define D64_FA_OFF_MASK 0xffff
#define D64_FA_SEL_MASK 0xf0000
#define D64_FA_SEL_SHIFT 16
#define D64_FA_SEL_XDD 0x00000
#define D64_FA_SEL_XDP 0x10000
#define D64_FA_SEL_RDD 0x40000
#define D64_FA_SEL_RDP 0x50000
#define D64_FA_SEL_XFD 0x80000
#define D64_FA_SEL_XFP 0x90000
#define D64_FA_SEL_RFD 0xc0000
#define D64_FA_SEL_RFP 0xd0000
#define D64_FA_SEL_RSD 0xe0000
#define D64_FA_SEL_RSP 0xf0000
#define D64_CTRL1_EOT ((uint32)1 << 28)
#define D64_CTRL1_IOC ((uint32)1 << 29)
#define D64_CTRL1_EOF ((uint32)1 << 30)
#define D64_CTRL1_SOF ((uint32)1 << 31)
#define D64_CTRL2_BC_MASK 0x00007fff
#define D64_CTRL2_AE 0x00030000
#define D64_CTRL2_AE_SHIFT 16
#define D64_CTRL2_PARITY 0x00040000
#define D64_CTRL_CORE_MASK 0x0ff00000
#endif

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/*
* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sbpcmcia.h,v 13.31.4.1.2.3.8.7 2009/06/22 05:14:24 Exp $
*/
#ifndef _SBPCMCIA_H
#define _SBPCMCIA_H
#define PCMCIA_FCR (0x700 / 2)
#define FCR0_OFF 0
#define FCR1_OFF (0x40 / 2)
#define FCR2_OFF (0x80 / 2)
#define FCR3_OFF (0xc0 / 2)
#define PCMCIA_FCR0 (0x700 / 2)
#define PCMCIA_FCR1 (0x740 / 2)
#define PCMCIA_FCR2 (0x780 / 2)
#define PCMCIA_FCR3 (0x7c0 / 2)
#define PCMCIA_COR 0
#define COR_RST 0x80
#define COR_LEV 0x40
#define COR_IRQEN 0x04
#define COR_BLREN 0x01
#define COR_FUNEN 0x01
#define PCICIA_FCSR (2 / 2)
#define PCICIA_PRR (4 / 2)
#define PCICIA_SCR (6 / 2)
#define PCICIA_ESR (8 / 2)
#define PCM_MEMOFF 0x0000
#define F0_MEMOFF 0x1000
#define F1_MEMOFF 0x2000
#define F2_MEMOFF 0x3000
#define F3_MEMOFF 0x4000
#define MEM_ADDR0 (0x728 / 2)
#define MEM_ADDR1 (0x72a / 2)
#define MEM_ADDR2 (0x72c / 2)
#define PCMCIA_ADDR0 (0x072e / 2)
#define PCMCIA_ADDR1 (0x0730 / 2)
#define PCMCIA_ADDR2 (0x0732 / 2)
#define MEM_SEG (0x0734 / 2)
#define SROM_CS (0x0736 / 2)
#define SROM_DATAL (0x0738 / 2)
#define SROM_DATAH (0x073a / 2)
#define SROM_ADDRL (0x073c / 2)
#define SROM_ADDRH (0x073e / 2)
#define SROM_INFO2 (0x0772 / 2)
#define SROM_INFO (0x07be / 2)
#define SROM_IDLE 0
#define SROM_WRITE 1
#define SROM_READ 2
#define SROM_WEN 4
#define SROM_WDS 7
#define SROM_DONE 8
#define SRI_SZ_MASK 0x03
#define SRI_BLANK 0x04
#define SRI_OTP 0x80
#define SBTML_INT_ACK 0x40000
#define SBTML_INT_EN 0x20000
#define SBTMH_INT_STATUS 0x40000
#endif

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/*
* SDIO device core hardware definitions.
* sdio is a portion of the pcmcia core in core rev 3 - rev 8
*
* SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sbsdio.h,v 13.29.4.1.22.3 2009/03/11 20:26:57 Exp $
*/
#ifndef _SBSDIO_H
#define _SBSDIO_H
#define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */
/* function 1 miscellaneous registers */
#define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */
#define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */
#define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */
#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */
#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */
#define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */
#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
#define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */
#define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */
#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */
#define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */
#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
/* SBSDIO_SPROM_CS */
#define SBSDIO_SPROM_IDLE 0
#define SBSDIO_SPROM_WRITE 1
#define SBSDIO_SPROM_READ 2
#define SBSDIO_SPROM_WEN 4
#define SBSDIO_SPROM_WDS 7
#define SBSDIO_SPROM_DONE 8
/* SBSDIO_SPROM_INFO */
#define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
#define SROM_BLANK 0x04 /* depreciated in corerev 6 */
#define SROM_OTP 0x80 /* OTP present */
/* SBSDIO_CHIP_CTRL */
#define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu,
* 1: power on oscillator
* (for 4318 only)
*/
/* SBSDIO_WATERMARK */
#define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device
* to wait before sending data to host
*/
/* SBSDIO_DEVICE_CTL */
#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
* receiving CMD53
*/
#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
* synchronous to the sdio clock
*/
#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
* except the chipActive (rev 8)
*/
#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
* external pads in tri-state; requires
* sdio bus power cycle to clear (rev 9)
*/
#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */
#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */
#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */
#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */
/* SBSDIO_FUNC1_CHIPCLKCSR */
#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
/* In rev8, actual avail bits followed original docs */
#define SBSDIO_Rev8_HT_AVAIL 0x40
#define SBSDIO_Rev8_ALP_AVAIL 0x80
#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
(alponly ? 1 : SBSDIO_HTAV(regval)))
/* SBSDIO_FUNC1_SDIOPULLUP */
#define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */
#define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */
#define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */
#define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */
#define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */
/* function 1 OCP space */
#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */
/* some duplication with sbsdpcmdev.h here */
/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
#define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */
/* direct(mapped) cis space */
#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
#define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */
#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
* link bytes
*/
/* indirect cis access (in sprom) */
#define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from
* 8th byte
*/
#define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one
* data comamnd
*/
#define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */
#endif /* _SBSDIO_H */

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/*
* Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific device core support
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sbsdpcmdev.h,v 13.29.4.1.4.6.6.2 2008/12/31 21:16:51 Exp $
*/
#ifndef _sbsdpcmdev_h_
#define _sbsdpcmdev_h_
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
typedef volatile struct {
dma64regs_t xmt; /* dma tx */
uint32 PAD[2];
dma64regs_t rcv; /* dma rx */
uint32 PAD[2];
} dma64p_t;
/* dma64 sdiod corerev >= 1 */
typedef volatile struct {
dma64p_t dma64regs[2];
dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */
uint32 PAD[92];
} sdiodma64_t;
/* dma32 sdiod corerev == 0 */
typedef volatile struct {
dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */
dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */
uint32 PAD[108];
} sdiodma32_t;
/* dma32 regs for pcmcia core */
typedef volatile struct {
dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */
dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */
uint32 PAD[116];
} pcmdma32_t;
/* core registers */
typedef volatile struct {
uint32 corecontrol; /* CoreControl, 0x000, rev8 */
uint32 corestatus; /* CoreStatus, 0x004, rev8 */
uint32 PAD[1];
uint32 biststatus; /* BistStatus, 0x00c, rev8 */
/* PCMCIA access */
uint16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */
uint16 PAD[1];
uint16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */
uint16 PAD[1];
uint16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */
uint16 PAD[1];
uint16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */
uint16 PAD[1];
/* interrupt */
uint32 intstatus; /* IntStatus, 0x020, rev8 */
uint32 hostintmask; /* IntHostMask, 0x024, rev8 */
uint32 intmask; /* IntSbMask, 0x028, rev8 */
uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */
uint32 sbintmask; /* SBIntMask, 0x030, rev8 */
uint32 PAD[3];
uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */
uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */
uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */
uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */
/* synchronized access to registers in SDIO clock domain */
uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */
uint32 PAD[3];
/* PCMCIA frame control */
uint8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */
uint8 PAD[3];
uint8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */
uint8 PAD[155];
/* interrupt batching control */
uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */
uint32 PAD[3];
/* counters */
uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */
uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
uint32 PAD[40];
uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */
uint32 PAD[7];
/* DMA engines */
volatile union {
pcmdma32_t pcm32;
sdiodma32_t sdiod32;
sdiodma64_t sdiod64;
} dma;
/* SDIO/PCMCIA CIS region */
char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */
/* PCMCIA function control registers */
char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */
uint16 PAD[55];
/* PCMCIA backplane access */
uint16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */
uint16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */
uint16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */
uint16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */
uint16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */
uint16 backplanedata0; /* BackplaneData0, 0x778, rev6 */
uint16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */
uint16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */
uint16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */
uint16 PAD[31];
/* sprom "size" & "blank" info */
uint16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */
uint32 PAD[464];
/* Sonics SiliconBackplane registers */
sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */
} sdpcmd_regs_t;
/* corecontrol */
#define CC_CISRDY (1 << 0) /* CIS Ready */
#define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */
#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */
/* corestatus */
#define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
#define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */
#define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */
#define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */
#define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */
#define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */
#define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */
/* intstatus */
#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
#define I_PC (1 << 10) /* descriptor error */
#define I_PD (1 << 11) /* data error */
#define I_DE (1 << 12) /* Descriptor protocol Error */
#define I_RU (1 << 13) /* Receive descriptor Underflow */
#define I_RO (1 << 14) /* Receive fifo Overflow */
#define I_XU (1 << 15) /* Transmit fifo Underflow */
#define I_RI (1 << 16) /* Receive Interrupt */
#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
#define I_XI (1 << 24) /* Transmit Interrupt */
#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
#define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */
#define I_SRESET (1 << 30) /* CCCR RES interrupt */
#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */
#define I_DMA (I_RI | I_XI | I_ERRORS)
/* sbintstatus */
#define I_SB_SERR (1 << 8) /* Backplane SError (write) */
#define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */
#define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */
/* sdioaccess */
#define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */
#define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */
#define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */
#define SDA_WRITE 0x01000000 /* Write bit */
#define SDA_READ 0x00000000 /* Write bit cleared for Read */
#define SDA_BUSY 0x80000000 /* Busy bit */
/* sdioaccess-accessible register address spaces */
#define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */
#define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */
#define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */
#define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */
/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
#define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */
#define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */
#define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */
#define SDA_DEVICECONTROL 0x009 /* DeviceControl */
#define SDA_SBADDRLOW 0x00a /* SbAddrLow */
#define SDA_SBADDRMID 0x00b /* SbAddrMid */
#define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */
#define SDA_FRAMECTRL 0x00d /* FrameCtrl */
#define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */
#define SDA_SDIOPULLUP 0x00f /* SdioPullUp */
#define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */
#define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */
#define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */
#define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */
/* SDA_F2WATERMARK */
#define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */
/* SDA_SBADDRLOW */
#define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */
/* SDA_SBADDRMID */
#define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */
/* SDA_SBADDRHIGH */
#define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */
/* SDA_FRAMECTRL */
#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
#define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */
#define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */
/* pcmciaframectrl */
#define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */
#define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */
/* intrcvlazy */
#define IRL_TO_MASK 0x00ffffff /* timeout */
#define IRL_FC_MASK 0xff000000 /* frame count */
#define IRL_FC_SHIFT 24 /* frame count */
/* rx header */
typedef volatile struct {
uint16 len;
uint16 flags;
} sdpcmd_rxh_t;
/* rx header flags */
#define RXF_CRC 0x0001 /* CRC error detected */
#define RXF_WOOS 0x0002 /* write frame out of sync */
#define RXF_WF_TERM 0x0004 /* write frame terminated */
#define RXF_ABORT 0x0008 /* write frame aborted */
#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */
/* HW frame tag */
#define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */
#endif /* _sbsdpcmdev_h_ */

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/*
* BCM47XX Sonics SiliconBackplane embedded ram core
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sbsocram.h,v 13.9.162.2 2008/12/12 14:13:27 Exp $
*/
#ifndef _SBSOCRAM_H
#define _SBSOCRAM_H
#ifndef _LANGUAGE_ASSEMBLY
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
typedef volatile struct sbsocramregs {
uint32 coreinfo;
uint32 bwalloc;
uint32 extracoreinfo;
uint32 biststat;
uint32 bankidx;
uint32 standbyctrl;
uint32 errlogstatus;
uint32 errlogaddr;
uint32 cambankidx;
uint32 cambankstandbyctrl;
uint32 cambankpatchctrl;
uint32 cambankpatchtblbaseaddr;
uint32 cambankcmdreg;
uint32 cambankdatareg;
uint32 cambankmaskreg;
uint32 PAD[17];
uint32 extmemconfig;
uint32 extmemparitycsr;
uint32 extmemparityerrdata;
uint32 extmemparityerrcnt;
uint32 extmemwrctrlandsize;
uint32 PAD[84];
uint32 workaround;
uint32 pwrctl;
} sbsocramregs_t;
#endif
#define SR_COREINFO 0x00
#define SR_BWALLOC 0x04
#define SR_BISTSTAT 0x0c
#define SR_BANKINDEX 0x10
#define SR_BANKSTBYCTL 0x14
#define SR_PWRCTL 0x1e8
#define SRCI_PT_MASK 0x00070000
#define SRCI_PT_SHIFT 16
#define SRCI_PT_OCP_OCP 0
#define SRCI_PT_AXI_OCP 1
#define SRCI_PT_ARM7AHB_OCP 2
#define SRCI_PT_CM3AHB_OCP 3
#define SRCI_PT_AXI_AXI 4
#define SRCI_PT_AHB_AXI 5
#define SRCI_LSS_MASK 0x00f00000
#define SRCI_LSS_SHIFT 20
#define SRCI_LRS_MASK 0x0f000000
#define SRCI_LRS_SHIFT 24
#define SRCI_MS0_MASK 0xf
#define SR_MS0_BASE 16
#define SRCI_ROMNB_MASK 0xf000
#define SRCI_ROMNB_SHIFT 12
#define SRCI_ROMBSZ_MASK 0xf00
#define SRCI_ROMBSZ_SHIFT 8
#define SRCI_SRNB_MASK 0xf0
#define SRCI_SRNB_SHIFT 4
#define SRCI_SRBSZ_MASK 0xf
#define SRCI_SRBSZ_SHIFT 0
#define SR_BSZ_BASE 14
#define SRSC_SBYOVR_MASK 0x80000000
#define SRSC_SBYOVR_SHIFT 31
#define SRSC_SBYOVRVAL_MASK 0x60000000
#define SRSC_SBYOVRVAL_SHIFT 29
#define SRSC_SBYEN_MASK 0x01000000
#define SRSC_SBYEN_SHIFT 24
#define SRPC_PMU_STBYDIS_MASK 0x00000010
#define SRPC_PMU_STBYDIS_SHIFT 4
#define SRPC_STBYOVRVAL_MASK 0x00000008
#define SRPC_STBYOVRVAL_SHIFT 3
#define SRPC_STBYOVR_MASK 0x00000007
#define SRPC_STBYOVR_SHIFT 0
#define SRECC_NUM_BANKS_MASK 0x000000F0
#define SRECC_NUM_BANKS_SHIFT 4
#define SRECC_BANKSIZE_MASK 0x0000000F
#define SRECC_BANKSIZE_SHIFT 0
#define SRECC_BANKSIZE(value) (1 << (value))
#define SRCBPC_PATCHENABLE 0x80000000
#define SRP_ADDRESS 0x0001FFFC
#define SRP_VALID 0x8000
#define SRCMD_WRITE 0x00020000
#define SRCMD_READ 0x00010000
#define SRCMD_DONE 0x80000000
#define SRCMD_DONE_DLY 1000
#endif

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/*
* SDIO spec header file
* Protocol and standard (common) device definitions
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sdio.h,v 13.24.4.1.4.1.16.1 2009/08/12 01:08:02 Exp $
*/
#ifndef _SDIO_H
#define _SDIO_H
/* CCCR structure for function 0 */
typedef volatile struct {
uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */
uint8 sd_rev; /* RO, sd spec revision */
uint8 io_en; /* I/O enable */
uint8 io_rdy; /* I/O ready reg */
uint8 intr_ctl; /* Master and per function interrupt enable control */
uint8 intr_status; /* RO, interrupt pending status */
uint8 io_abort; /* read/write abort or reset all functions */
uint8 bus_inter; /* bus interface control */
uint8 capability; /* RO, card capability */
uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */
uint8 cis_base_mid;
uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */
/* suspend/resume registers */
uint8 bus_suspend; /* 0xC */
uint8 func_select; /* 0xD */
uint8 exec_flag; /* 0xE */
uint8 ready_flag; /* 0xF */
uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */
uint8 power_control; /* 0x12 (SDIO version 1.10) */
uint8 speed_control; /* 0x13 */
} sdio_regs_t;
/* SDIO Device CCCR offsets */
#define SDIOD_CCCR_REV 0x00
#define SDIOD_CCCR_SDREV 0x01
#define SDIOD_CCCR_IOEN 0x02
#define SDIOD_CCCR_IORDY 0x03
#define SDIOD_CCCR_INTEN 0x04
#define SDIOD_CCCR_INTPEND 0x05
#define SDIOD_CCCR_IOABORT 0x06
#define SDIOD_CCCR_BICTRL 0x07
#define SDIOD_CCCR_CAPABLITIES 0x08
#define SDIOD_CCCR_CISPTR_0 0x09
#define SDIOD_CCCR_CISPTR_1 0x0A
#define SDIOD_CCCR_CISPTR_2 0x0B
#define SDIOD_CCCR_BUSSUSP 0x0C
#define SDIOD_CCCR_FUNCSEL 0x0D
#define SDIOD_CCCR_EXECFLAGS 0x0E
#define SDIOD_CCCR_RDYFLAGS 0x0F
#define SDIOD_CCCR_BLKSIZE_0 0x10
#define SDIOD_CCCR_BLKSIZE_1 0x11
#define SDIOD_CCCR_POWER_CONTROL 0x12
#define SDIOD_CCCR_SPEED_CONTROL 0x13
/* Broadcom extensions (corerev >= 1) */
#define SDIOD_CCCR_BRCM_SEPINT 0xf2
/* cccr_sdio_rev */
#define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */
#define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */
/* sd_rev */
#define SD_REV_PHY_MASK 0x0f /* SD format version number */
/* io_en */
#define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */
#define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */
/* io_rdys */
#define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */
#define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */
/* intr_ctl */
#define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */
#define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */
#define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */
/* intr_status */
#define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */
#define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */
/* io_abort */
#define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */
#define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */
/* bus_inter */
#define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */
#define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */
#define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */
#define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */
#define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */
#define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */
/* capability */
#define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */
#define SDIO_CAP_LSC 0x40 /* low speed card */
#define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */
#define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */
#define SDIO_CAP_SBS 0x08 /* support suspend/resume */
#define SDIO_CAP_SRW 0x04 /* support read wait */
#define SDIO_CAP_SMB 0x02 /* support multi-block transfer */
#define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */
/* power_control */
#define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */
#define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */
/* speed_control (control device entry into high-speed clocking mode) */
#define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */
#define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */
/* brcm sepint */
#define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */
#define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */
#define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */
/* FBR structure for function 1-7, FBR addresses and register offsets */
typedef volatile struct {
uint8 devctr; /* device interface, CSA control */
uint8 ext_dev; /* extended standard I/O device type code */
uint8 pwr_sel; /* power selection support */
uint8 PAD[6]; /* reserved */
uint8 cis_low; /* CIS LSB */
uint8 cis_mid;
uint8 cis_high; /* CIS MSB */
uint8 csa_low; /* code storage area, LSB */
uint8 csa_mid;
uint8 csa_high; /* code storage area, MSB */
uint8 csa_dat_win; /* data access window to function */
uint8 fnx_blk_size[2]; /* block size, little endian */
} sdio_fbr_t;
/* Maximum number of I/O funcs */
#define SDIOD_MAX_IOFUNCS 7
/* SDIO Device FBR Start Address */
#define SDIOD_FBR_STARTADDR 0x100
/* SDIO Device FBR Size */
#define SDIOD_FBR_SIZE 0x100
/* Macro to calculate FBR register base */
#define SDIOD_FBR_BASE(n) ((n) * 0x100)
/* Function register offsets */
#define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */
#define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */
#define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */
/* SDIO Function CIS ptr offset */
#define SDIOD_FBR_CISPTR_0 0x09
#define SDIOD_FBR_CISPTR_1 0x0A
#define SDIOD_FBR_CISPTR_2 0x0B
/* Code Storage Area pointer */
#define SDIOD_FBR_CSA_ADDR_0 0x0C
#define SDIOD_FBR_CSA_ADDR_1 0x0D
#define SDIOD_FBR_CSA_ADDR_2 0x0E
#define SDIOD_FBR_CSA_DATA 0x0F
/* SDIO Function I/O Block Size */
#define SDIOD_FBR_BLKSIZE_0 0x10
#define SDIOD_FBR_BLKSIZE_1 0x11
/* devctr */
#define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */
#define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */
#define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */
/* interface codes */
#define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */
#define SDIOD_DIC_UART 1
#define SDIOD_DIC_BLUETOOTH_A 2
#define SDIOD_DIC_BLUETOOTH_B 3
#define SDIOD_DIC_GPS 4
#define SDIOD_DIC_CAMERA 5
#define SDIOD_DIC_PHS 6
#define SDIOD_DIC_WLAN 7
#define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */
/* pwr_sel */
#define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */
#define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */
/* misc defines */
#define SDIO_FUNC_0 0
#define SDIO_FUNC_1 1
#define SDIO_FUNC_2 2
#define SDIO_FUNC_3 3
#define SDIO_FUNC_4 4
#define SDIO_FUNC_5 5
#define SDIO_FUNC_6 6
#define SDIO_FUNC_7 7
#define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */
#define SD_CARD_TYPE_IO 1 /* IO only card */
#define SD_CARD_TYPE_MEMORY 2 /* memory only card */
#define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */
#define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */
#define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */
/* Card registers: status bit position */
#define CARDREG_STATUS_BIT_OUTOFRANGE 31
#define CARDREG_STATUS_BIT_COMCRCERROR 23
#define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22
#define CARDREG_STATUS_BIT_ERROR 19
#define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12
#define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11
#define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10
#define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9
#define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4
#define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */
#define SD_CMD_SEND_OPCOND 1
#define SD_CMD_MMC_SET_RCA 3
#define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */
#define SD_CMD_SELECT_DESELECT_CARD 7
#define SD_CMD_SEND_CSD 9
#define SD_CMD_SEND_CID 10
#define SD_CMD_STOP_TRANSMISSION 12
#define SD_CMD_SEND_STATUS 13
#define SD_CMD_GO_INACTIVE_STATE 15
#define SD_CMD_SET_BLOCKLEN 16
#define SD_CMD_READ_SINGLE_BLOCK 17
#define SD_CMD_READ_MULTIPLE_BLOCK 18
#define SD_CMD_WRITE_BLOCK 24
#define SD_CMD_WRITE_MULTIPLE_BLOCK 25
#define SD_CMD_PROGRAM_CSD 27
#define SD_CMD_SET_WRITE_PROT 28
#define SD_CMD_CLR_WRITE_PROT 29
#define SD_CMD_SEND_WRITE_PROT 30
#define SD_CMD_ERASE_WR_BLK_START 32
#define SD_CMD_ERASE_WR_BLK_END 33
#define SD_CMD_ERASE 38
#define SD_CMD_LOCK_UNLOCK 42
#define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */
#define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */
#define SD_CMD_APP_CMD 55
#define SD_CMD_GEN_CMD 56
#define SD_CMD_READ_OCR 58
#define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */
#define SD_ACMD_SD_STATUS 13
#define SD_ACMD_SEND_NUM_WR_BLOCKS 22
#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23
#define SD_ACMD_SD_SEND_OP_COND 41
#define SD_ACMD_SET_CLR_CARD_DETECT 42
#define SD_ACMD_SEND_SCR 51
/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
#define SD_IO_OP_READ 0 /* Read_Write: Read */
#define SD_IO_OP_WRITE 1 /* Read_Write: Write */
#define SD_IO_RW_NORMAL 0 /* no RAW */
#define SD_IO_RW_RAW 1 /* RAW */
#define SD_IO_BYTE_MODE 0 /* Byte Mode */
#define SD_IO_BLOCK_MODE 1 /* BlockMode */
#define SD_IO_FIXED_ADDRESS 0 /* fix Address */
#define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */
/* build SD_CMD_IO_RW_DIRECT Argument */
#define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \
((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \
(((addr) & 0x1FFFF) << 9) | ((data) & 0xFF))
/* build SD_CMD_IO_RW_EXTENDED Argument */
#define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \
((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \
(((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF))
/* SDIO response parameters */
#define SD_RSP_NO_NONE 0
#define SD_RSP_NO_1 1
#define SD_RSP_NO_2 2
#define SD_RSP_NO_3 3
#define SD_RSP_NO_4 4
#define SD_RSP_NO_5 5
#define SD_RSP_NO_6 6
/* Modified R6 response (to CMD3) */
#define SD_RSP_MR6_COM_CRC_ERROR 0x8000
#define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000
#define SD_RSP_MR6_ERROR 0x2000
/* Modified R1 in R4 Response (to CMD5) */
#define SD_RSP_MR1_SBIT 0x80
#define SD_RSP_MR1_PARAMETER_ERROR 0x40
#define SD_RSP_MR1_RFU5 0x20
#define SD_RSP_MR1_FUNC_NUM_ERROR 0x10
#define SD_RSP_MR1_COM_CRC_ERROR 0x08
#define SD_RSP_MR1_ILLEGAL_COMMAND 0x04
#define SD_RSP_MR1_RFU1 0x02
#define SD_RSP_MR1_IDLE_STATE 0x01
/* R5 response (to CMD52 and CMD53) */
#define SD_RSP_R5_COM_CRC_ERROR 0x80
#define SD_RSP_R5_ILLEGAL_COMMAND 0x40
#define SD_RSP_R5_IO_CURRENTSTATE1 0x20
#define SD_RSP_R5_IO_CURRENTSTATE0 0x10
#define SD_RSP_R5_ERROR 0x08
#define SD_RSP_R5_RFU 0x04
#define SD_RSP_R5_FUNC_NUM_ERROR 0x02
#define SD_RSP_R5_OUT_OF_RANGE 0x01
#define SD_RSP_R5_ERRBITS 0xCB
/* ------------------------------------------------
* SDIO Commands and responses
*
* I/O only commands are:
* CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
* ------------------------------------------------
*/
/* SDIO Commands */
#define SDIOH_CMD_0 0
#define SDIOH_CMD_3 3
#define SDIOH_CMD_5 5
#define SDIOH_CMD_7 7
#define SDIOH_CMD_15 15
#define SDIOH_CMD_52 52
#define SDIOH_CMD_53 53
#define SDIOH_CMD_59 59
/* SDIO Command Responses */
#define SDIOH_RSP_NONE 0
#define SDIOH_RSP_R1 1
#define SDIOH_RSP_R2 2
#define SDIOH_RSP_R3 3
#define SDIOH_RSP_R4 4
#define SDIOH_RSP_R5 5
#define SDIOH_RSP_R6 6
/*
* SDIO Response Error flags
*/
#define SDIOH_RSP5_ERROR_FLAGS 0xCB
/* ------------------------------------------------
* SDIO Command structures. I/O only commands are:
*
* CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
* ------------------------------------------------
*/
#define CMD5_OCR_M BITFIELD_MASK(24)
#define CMD5_OCR_S 0
#define CMD7_RCA_M BITFIELD_MASK(16)
#define CMD7_RCA_S 16
#define CMD_15_RCA_M BITFIELD_MASK(16)
#define CMD_15_RCA_S 16
#define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52
*/
#define CMD52_DATA_S 0
#define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
#define CMD52_REG_ADDR_S 9
#define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */
#define CMD52_RAW_S 27
#define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
#define CMD52_FUNCTION_S 28
#define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
#define CMD52_RW_FLAG_S 31
#define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */
#define CMD53_BYTE_BLK_CNT_S 0
#define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
#define CMD53_REG_ADDR_S 9
#define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */
#define CMD53_OP_CODE_S 26
#define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */
#define CMD53_BLK_MODE_S 27
#define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
#define CMD53_FUNCTION_S 28
#define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
#define CMD53_RW_FLAG_S 31
/* ------------------------------------------------------
* SDIO Command Response structures for SD1 and SD4 modes
* -----------------------------------------------------
*/
#define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */
#define RSP4_IO_OCR_S 0
#define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */
#define RSP4_STUFF_S 24
#define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */
#define RSP4_MEM_PRESENT_S 27
#define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */
#define RSP4_NUM_FUNCS_S 28
#define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */
#define RSP4_CARD_READY_S 31
#define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0]
*/
#define RSP6_STATUS_S 0
#define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */
#define RSP6_IO_RCA_S 16
#define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */
#define RSP1_AKE_SEQ_ERROR_S 3
#define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
#define RSP1_APP_CMD_S 5
#define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */
#define RSP1_READY_FOR_DATA_S 8
#define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card
* when Cmd was received
*/
#define RSP1_CURR_STATE_S 9
#define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */
#define RSP1_EARSE_RESET_S 13
#define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */
#define RSP1_CARD_ECC_DISABLE_S 14
#define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */
#define RSP1_WP_ERASE_SKIP_S 15
#define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits
* of CSD
*/
#define RSP1_CID_CSD_OVERW_S 16
#define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */
#define RSP1_ERROR_S 19
#define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */
#define RSP1_CC_ERROR_S 20
#define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed
* to correct data
*/
#define RSP1_CARD_ECC_FAILED_S 21
#define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */
#define RSP1_ILLEGAL_CMD_S 22
#define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed
*/
#define RSP1_COM_CRC_ERROR_S 23
#define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */
#define RSP1_LOCK_UNLOCK_FAIL_S 24
#define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */
#define RSP1_CARD_LOCKED_S 25
#define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program
* write-protected blocks
*/
#define RSP1_WP_VIOLATION_S 26
#define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */
#define RSP1_ERASE_PARAM_S 27
#define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */
#define RSP1_ERASE_SEQ_ERR_S 28
#define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */
#define RSP1_BLK_LEN_ERR_S 29
#define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */
#define RSP1_ADDR_ERR_S 30
#define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */
#define RSP1_OUT_OF_RANGE_S 31
#define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */
#define RSP5_DATA_S 0
#define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */
#define RSP5_FLAGS_S 8
#define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */
#define RSP5_STUFF_S 16
/* ----------------------------------------------
* SDIO Command Response structures for SPI mode
* ----------------------------------------------
*/
#define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */
#define SPIRSP4_IO_OCR_S 0
#define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */
#define SPIRSP4_STUFF_S 16
#define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */
#define SPIRSP4_MEM_PRESENT_S 19
#define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */
#define SPIRSP4_NUM_FUNCS_S 20
#define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */
#define SPIRSP4_CARD_READY_S 23
#define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */
#define SPIRSP4_IDLE_STATE_S 24
#define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
#define SPIRSP4_ILLEGAL_CMD_S 26
#define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
#define SPIRSP4_COM_CRC_ERROR_S 27
#define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
*/
#define SPIRSP4_FUNC_NUM_ERROR_S 28
#define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
#define SPIRSP4_PARAM_ERROR_S 30
#define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
#define SPIRSP4_START_BIT_S 31
#define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */
#define SPIRSP5_DATA_S 16
#define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */
#define SPIRSP5_IDLE_STATE_S 24
#define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
#define SPIRSP5_ILLEGAL_CMD_S 26
#define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
#define SPIRSP5_COM_CRC_ERROR_S 27
#define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
*/
#define SPIRSP5_FUNC_NUM_ERROR_S 28
#define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
#define SPIRSP5_PARAM_ERROR_S 30
#define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
#define SPIRSP5_START_BIT_S 31
/* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */
#define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error
*/
#define RSP6STAT_AKE_SEQ_ERROR_S 3
#define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
#define RSP6STAT_APP_CMD_S 5
#define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data
* (buff empty)
*/
#define RSP6STAT_READY_FOR_DATA_S 8
#define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at
* Cmd reception
*/
#define RSP6STAT_CURR_STATE_S 9
#define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19
*/
#define RSP6STAT_ERROR_S 13
#define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for
* card state Bit 22
*/
#define RSP6STAT_ILLEGAL_CMD_S 14
#define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command
* failed Bit 23
*/
#define RSP6STAT_COM_CRC_ERROR_S 15
#define SDIOH_XFER_TYPE_READ SD_IO_OP_READ
#define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE
#endif /* _SDIO_H */

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drivers/net/wireless/bcm4329_245/include/sdioh.h Normal file
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/*
* SDIO Host Controller Spec header file
* Register map and definitions for the Standard Host Controller
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sdioh.h,v 13.13.18.1.16.3 2009/12/08 22:34:21 Exp $
*/
#ifndef _SDIOH_H
#define _SDIOH_H
#define SD_SysAddr 0x000
#define SD_BlockSize 0x004
#define SD_BlockCount 0x006
#define SD_Arg0 0x008
#define SD_Arg1 0x00A
#define SD_TransferMode 0x00C
#define SD_Command 0x00E
#define SD_Response0 0x010
#define SD_Response1 0x012
#define SD_Response2 0x014
#define SD_Response3 0x016
#define SD_Response4 0x018
#define SD_Response5 0x01A
#define SD_Response6 0x01C
#define SD_Response7 0x01E
#define SD_BufferDataPort0 0x020
#define SD_BufferDataPort1 0x022
#define SD_PresentState 0x024
#define SD_HostCntrl 0x028
#define SD_PwrCntrl 0x029
#define SD_BlockGapCntrl 0x02A
#define SD_WakeupCntrl 0x02B
#define SD_ClockCntrl 0x02C
#define SD_TimeoutCntrl 0x02E
#define SD_SoftwareReset 0x02F
#define SD_IntrStatus 0x030
#define SD_ErrorIntrStatus 0x032
#define SD_IntrStatusEnable 0x034
#define SD_ErrorIntrStatusEnable 0x036
#define SD_IntrSignalEnable 0x038
#define SD_ErrorIntrSignalEnable 0x03A
#define SD_CMD12ErrorStatus 0x03C
#define SD_Capabilities 0x040
#define SD_Capabilities_Reserved 0x044
#define SD_MaxCurCap 0x048
#define SD_MaxCurCap_Reserved 0x04C
#define SD_ADMA_SysAddr 0x58
#define SD_SlotInterruptStatus 0x0FC
#define SD_HostControllerVersion 0x0FE
/* SD specific registers in PCI config space */
#define SD_SlotInfo 0x40
/* SD_Capabilities reg (0x040) */
#define CAP_TO_CLKFREQ_M BITFIELD_MASK(6)
#define CAP_TO_CLKFREQ_S 0
#define CAP_TO_CLKUNIT_M BITFIELD_MASK(1)
#define CAP_TO_CLKUNIT_S 7
#define CAP_BASECLK_M BITFIELD_MASK(6)
#define CAP_BASECLK_S 8
#define CAP_MAXBLOCK_M BITFIELD_MASK(2)
#define CAP_MAXBLOCK_S 16
#define CAP_ADMA2_M BITFIELD_MASK(1)
#define CAP_ADMA2_S 19
#define CAP_ADMA1_M BITFIELD_MASK(1)
#define CAP_ADMA1_S 20
#define CAP_HIGHSPEED_M BITFIELD_MASK(1)
#define CAP_HIGHSPEED_S 21
#define CAP_DMA_M BITFIELD_MASK(1)
#define CAP_DMA_S 22
#define CAP_SUSPEND_M BITFIELD_MASK(1)
#define CAP_SUSPEND_S 23
#define CAP_VOLT_3_3_M BITFIELD_MASK(1)
#define CAP_VOLT_3_3_S 24
#define CAP_VOLT_3_0_M BITFIELD_MASK(1)
#define CAP_VOLT_3_0_S 25
#define CAP_VOLT_1_8_M BITFIELD_MASK(1)
#define CAP_VOLT_1_8_S 26
#define CAP_64BIT_HOST_M BITFIELD_MASK(1)
#define CAP_64BIT_HOST_S 28
/* SD_MaxCurCap reg (0x048) */
#define CAP_CURR_3_3_M BITFIELD_MASK(8)
#define CAP_CURR_3_3_S 0
#define CAP_CURR_3_0_M BITFIELD_MASK(8)
#define CAP_CURR_3_0_S 8
#define CAP_CURR_1_8_M BITFIELD_MASK(8)
#define CAP_CURR_1_8_S 16
/* SD_SysAddr: Offset 0x0000, Size 4 bytes */
/* SD_BlockSize: Offset 0x004, Size 2 bytes */
#define BLKSZ_BLKSZ_M BITFIELD_MASK(12)
#define BLKSZ_BLKSZ_S 0
#define BLKSZ_BNDRY_M BITFIELD_MASK(3)
#define BLKSZ_BNDRY_S 12
/* SD_BlockCount: Offset 0x006, size 2 bytes */
/* SD_Arg0: Offset 0x008, size = 4 bytes */
/* SD_TransferMode Offset 0x00C, size = 2 bytes */
#define XFER_DMA_ENABLE_M BITFIELD_MASK(1)
#define XFER_DMA_ENABLE_S 0
#define XFER_BLK_COUNT_EN_M BITFIELD_MASK(1)
#define XFER_BLK_COUNT_EN_S 1
#define XFER_CMD_12_EN_M BITFIELD_MASK(1)
#define XFER_CMD_12_EN_S 2
#define XFER_DATA_DIRECTION_M BITFIELD_MASK(1)
#define XFER_DATA_DIRECTION_S 4
#define XFER_MULTI_BLOCK_M BITFIELD_MASK(1)
#define XFER_MULTI_BLOCK_S 5
/* SD_Command: Offset 0x00E, size = 2 bytes */
/* resp_type field */
#define RESP_TYPE_NONE 0
#define RESP_TYPE_136 1
#define RESP_TYPE_48 2
#define RESP_TYPE_48_BUSY 3
/* type field */
#define CMD_TYPE_NORMAL 0
#define CMD_TYPE_SUSPEND 1
#define CMD_TYPE_RESUME 2
#define CMD_TYPE_ABORT 3
#define CMD_RESP_TYPE_M BITFIELD_MASK(2) /* Bits [0-1] - Response type */
#define CMD_RESP_TYPE_S 0
#define CMD_CRC_EN_M BITFIELD_MASK(1) /* Bit 3 - CRC enable */
#define CMD_CRC_EN_S 3
#define CMD_INDEX_EN_M BITFIELD_MASK(1) /* Bit 4 - Enable index checking */
#define CMD_INDEX_EN_S 4
#define CMD_DATA_EN_M BITFIELD_MASK(1) /* Bit 5 - Using DAT line */
#define CMD_DATA_EN_S 5
#define CMD_TYPE_M BITFIELD_MASK(2) /* Bit [6-7] - Normal, abort, resume, etc
*/
#define CMD_TYPE_S 6
#define CMD_INDEX_M BITFIELD_MASK(6) /* Bits [8-13] - Command number */
#define CMD_INDEX_S 8
/* SD_BufferDataPort0 : Offset 0x020, size = 2 or 4 bytes */
/* SD_BufferDataPort1 : Offset 0x022, size = 2 bytes */
/* SD_PresentState : Offset 0x024, size = 4 bytes */
#define PRES_CMD_INHIBIT_M BITFIELD_MASK(1) /* Bit 0 May use CMD */
#define PRES_CMD_INHIBIT_S 0
#define PRES_DAT_INHIBIT_M BITFIELD_MASK(1) /* Bit 1 May use DAT */
#define PRES_DAT_INHIBIT_S 1
#define PRES_DAT_BUSY_M BITFIELD_MASK(1) /* Bit 2 DAT is busy */
#define PRES_DAT_BUSY_S 2
#define PRES_PRESENT_RSVD_M BITFIELD_MASK(5) /* Bit [3-7] rsvd */
#define PRES_PRESENT_RSVD_S 3
#define PRES_WRITE_ACTIVE_M BITFIELD_MASK(1) /* Bit 8 Write is active */
#define PRES_WRITE_ACTIVE_S 8
#define PRES_READ_ACTIVE_M BITFIELD_MASK(1) /* Bit 9 Read is active */
#define PRES_READ_ACTIVE_S 9
#define PRES_WRITE_DATA_RDY_M BITFIELD_MASK(1) /* Bit 10 Write buf is avail */
#define PRES_WRITE_DATA_RDY_S 10
#define PRES_READ_DATA_RDY_M BITFIELD_MASK(1) /* Bit 11 Read buf data avail */
#define PRES_READ_DATA_RDY_S 11
#define PRES_CARD_PRESENT_M BITFIELD_MASK(1) /* Bit 16 Card present - debounced */
#define PRES_CARD_PRESENT_S 16
#define PRES_CARD_STABLE_M BITFIELD_MASK(1) /* Bit 17 Debugging */
#define PRES_CARD_STABLE_S 17
#define PRES_CARD_PRESENT_RAW_M BITFIELD_MASK(1) /* Bit 18 Not debounced */
#define PRES_CARD_PRESENT_RAW_S 18
#define PRES_WRITE_ENABLED_M BITFIELD_MASK(1) /* Bit 19 Write protected? */
#define PRES_WRITE_ENABLED_S 19
#define PRES_DAT_SIGNAL_M BITFIELD_MASK(4) /* Bit [20-23] Debugging */
#define PRES_DAT_SIGNAL_S 20
#define PRES_CMD_SIGNAL_M BITFIELD_MASK(1) /* Bit 24 Debugging */
#define PRES_CMD_SIGNAL_S 24
/* SD_HostCntrl: Offset 0x028, size = 1 bytes */
#define HOST_LED_M BITFIELD_MASK(1) /* Bit 0 LED On/Off */
#define HOST_LED_S 0
#define HOST_DATA_WIDTH_M BITFIELD_MASK(1) /* Bit 1 4 bit enable */
#define HOST_DATA_WIDTH_S 1
#define HOST_HI_SPEED_EN_M BITFIELD_MASK(1) /* Bit 2 High speed vs low speed */
#define HOST_DMA_SEL_S 3
#define HOST_DMA_SEL_M BITFIELD_MASK(2) /* Bit 4:3 DMA Select */
#define HOST_HI_SPEED_EN_S 2
/* misc defines */
#define SD1_MODE 0x1 /* SD Host Cntrlr Spec */
#define SD4_MODE 0x2 /* SD Host Cntrlr Spec */
/* SD_PwrCntrl: Offset 0x029, size = 1 bytes */
#define PWR_BUS_EN_M BITFIELD_MASK(1) /* Bit 0 Power the bus */
#define PWR_BUS_EN_S 0
#define PWR_VOLTS_M BITFIELD_MASK(3) /* Bit [1-3] Voltage Select */
#define PWR_VOLTS_S 1
/* SD_SoftwareReset: Offset 0x02F, size = 1 byte */
#define SW_RESET_ALL_M BITFIELD_MASK(1) /* Bit 0 Reset All */
#define SW_RESET_ALL_S 0
#define SW_RESET_CMD_M BITFIELD_MASK(1) /* Bit 1 CMD Line Reset */
#define SW_RESET_CMD_S 1
#define SW_RESET_DAT_M BITFIELD_MASK(1) /* Bit 2 DAT Line Reset */
#define SW_RESET_DAT_S 2
/* SD_IntrStatus: Offset 0x030, size = 2 bytes */
/* Defs also serve SD_IntrStatusEnable and SD_IntrSignalEnable */
#define INTSTAT_CMD_COMPLETE_M BITFIELD_MASK(1) /* Bit 0 */
#define INTSTAT_CMD_COMPLETE_S 0
#define INTSTAT_XFER_COMPLETE_M BITFIELD_MASK(1)
#define INTSTAT_XFER_COMPLETE_S 1
#define INTSTAT_BLOCK_GAP_EVENT_M BITFIELD_MASK(1)
#define INTSTAT_BLOCK_GAP_EVENT_S 2
#define INTSTAT_DMA_INT_M BITFIELD_MASK(1)
#define INTSTAT_DMA_INT_S 3
#define INTSTAT_BUF_WRITE_READY_M BITFIELD_MASK(1)
#define INTSTAT_BUF_WRITE_READY_S 4
#define INTSTAT_BUF_READ_READY_M BITFIELD_MASK(1)
#define INTSTAT_BUF_READ_READY_S 5
#define INTSTAT_CARD_INSERTION_M BITFIELD_MASK(1)
#define INTSTAT_CARD_INSERTION_S 6
#define INTSTAT_CARD_REMOVAL_M BITFIELD_MASK(1)
#define INTSTAT_CARD_REMOVAL_S 7
#define INTSTAT_CARD_INT_M BITFIELD_MASK(1)
#define INTSTAT_CARD_INT_S 8
#define INTSTAT_ERROR_INT_M BITFIELD_MASK(1) /* Bit 15 */
#define INTSTAT_ERROR_INT_S 15
/* SD_ErrorIntrStatus: Offset 0x032, size = 2 bytes */
/* Defs also serve SD_ErrorIntrStatusEnable and SD_ErrorIntrSignalEnable */
#define ERRINT_CMD_TIMEOUT_M BITFIELD_MASK(1)
#define ERRINT_CMD_TIMEOUT_S 0
#define ERRINT_CMD_CRC_M BITFIELD_MASK(1)
#define ERRINT_CMD_CRC_S 1
#define ERRINT_CMD_ENDBIT_M BITFIELD_MASK(1)
#define ERRINT_CMD_ENDBIT_S 2
#define ERRINT_CMD_INDEX_M BITFIELD_MASK(1)
#define ERRINT_CMD_INDEX_S 3
#define ERRINT_DATA_TIMEOUT_M BITFIELD_MASK(1)
#define ERRINT_DATA_TIMEOUT_S 4
#define ERRINT_DATA_CRC_M BITFIELD_MASK(1)
#define ERRINT_DATA_CRC_S 5
#define ERRINT_DATA_ENDBIT_M BITFIELD_MASK(1)
#define ERRINT_DATA_ENDBIT_S 6
#define ERRINT_CURRENT_LIMIT_M BITFIELD_MASK(1)
#define ERRINT_CURRENT_LIMIT_S 7
#define ERRINT_AUTO_CMD12_M BITFIELD_MASK(1)
#define ERRINT_AUTO_CMD12_S 8
#define ERRINT_VENDOR_M BITFIELD_MASK(4)
#define ERRINT_VENDOR_S 12
/* Also provide definitions in "normal" form to allow combined masks */
#define ERRINT_CMD_TIMEOUT_BIT 0x0001
#define ERRINT_CMD_CRC_BIT 0x0002
#define ERRINT_CMD_ENDBIT_BIT 0x0004
#define ERRINT_CMD_INDEX_BIT 0x0008
#define ERRINT_DATA_TIMEOUT_BIT 0x0010
#define ERRINT_DATA_CRC_BIT 0x0020
#define ERRINT_DATA_ENDBIT_BIT 0x0040
#define ERRINT_CURRENT_LIMIT_BIT 0x0080
#define ERRINT_AUTO_CMD12_BIT 0x0100
/* Masks to select CMD vs. DATA errors */
#define ERRINT_CMD_ERRS (ERRINT_CMD_TIMEOUT_BIT | ERRINT_CMD_CRC_BIT |\
ERRINT_CMD_ENDBIT_BIT | ERRINT_CMD_INDEX_BIT)
#define ERRINT_DATA_ERRS (ERRINT_DATA_TIMEOUT_BIT | ERRINT_DATA_CRC_BIT |\
ERRINT_DATA_ENDBIT_BIT)
#define ERRINT_TRANSFER_ERRS (ERRINT_CMD_ERRS | ERRINT_DATA_ERRS)
/* SD_WakeupCntr_BlockGapCntrl : Offset 0x02A , size = bytes */
/* SD_ClockCntrl : Offset 0x02C , size = bytes */
/* SD_SoftwareReset_TimeoutCntrl : Offset 0x02E , size = bytes */
/* SD_IntrStatus : Offset 0x030 , size = bytes */
/* SD_ErrorIntrStatus : Offset 0x032 , size = bytes */
/* SD_IntrStatusEnable : Offset 0x034 , size = bytes */
/* SD_ErrorIntrStatusEnable : Offset 0x036 , size = bytes */
/* SD_IntrSignalEnable : Offset 0x038 , size = bytes */
/* SD_ErrorIntrSignalEnable : Offset 0x03A , size = bytes */
/* SD_CMD12ErrorStatus : Offset 0x03C , size = bytes */
/* SD_Capabilities : Offset 0x040 , size = bytes */
/* SD_MaxCurCap : Offset 0x048 , size = bytes */
/* SD_MaxCurCap_Reserved: Offset 0x04C , size = bytes */
/* SD_SlotInterruptStatus: Offset 0x0FC , size = bytes */
/* SD_HostControllerVersion : Offset 0x0FE , size = bytes */
#endif /* _SDIOH_H */

58
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/*
* Structure used by apps whose drivers access SDIO drivers.
* Pulled out separately so dhdu and wlu can both use it.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sdiovar.h,v 13.5.14.2.16.2 2009/12/08 22:34:21 Exp $
*/
#ifndef _sdiovar_h_
#define _sdiovar_h_
#include <typedefs.h>
/* require default structure packing */
#define BWL_DEFAULT_PACKING
#include <packed_section_start.h>
typedef struct sdreg {
int func;
int offset;
int value;
} sdreg_t;
/* Common msglevel constants */
#define SDH_ERROR_VAL 0x0001 /* Error */
#define SDH_TRACE_VAL 0x0002 /* Trace */
#define SDH_INFO_VAL 0x0004 /* Info */
#define SDH_DEBUG_VAL 0x0008 /* Debug */
#define SDH_DATA_VAL 0x0010 /* Data */
#define SDH_CTRL_VAL 0x0020 /* Control Regs */
#define SDH_LOG_VAL 0x0040 /* Enable bcmlog */
#define SDH_DMA_VAL 0x0080 /* DMA */
#define NUM_PREV_TRANSACTIONS 16
#include <packed_section_end.h>
#endif /* _sdiovar_h_ */

235
drivers/net/wireless/bcm4329_245/include/siutils.h Normal file
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/*
* Misc utility routines for accessing the SOC Interconnects
* of Broadcom HNBU chips.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: siutils.h,v 13.197.4.2.4.3.8.16 2010/06/23 21:36:05 Exp $
*/
#ifndef _siutils_h_
#define _siutils_h_
struct si_pub {
uint socitype;
uint bustype;
uint buscoretype;
uint buscorerev;
uint buscoreidx;
int ccrev;
uint32 cccaps;
int pmurev;
uint32 pmucaps;
uint boardtype;
uint boardvendor;
uint boardflags;
uint chip;
uint chiprev;
uint chippkg;
uint32 chipst;
bool issim;
uint socirev;
bool pci_pr32414;
};
#if defined(WLC_HIGH) && !defined(WLC_LOW)
typedef struct si_pub si_t;
#else
typedef const struct si_pub si_t;
#endif
#define SI_OSH NULL
#define XTAL 0x1
#define PLL 0x2
#define CLK_FAST 0
#define CLK_DYNAMIC 2
#define GPIO_DRV_PRIORITY 0
#define GPIO_APP_PRIORITY 1
#define GPIO_HI_PRIORITY 2
#define GPIO_PULLUP 0
#define GPIO_PULLDN 1
#define GPIO_REGEVT 0
#define GPIO_REGEVT_INTMSK 1
#define GPIO_REGEVT_INTPOL 2
#define SI_DEVPATH_BUFSZ 16
#define SI_DOATTACH 1
#define SI_PCIDOWN 2
#define SI_PCIUP 3
#define ISSIM_ENAB(sih) 0
#if defined(BCMPMUCTL)
#define PMUCTL_ENAB(sih) (BCMPMUCTL)
#else
#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
#endif
#if defined(BCMPMUCTL) && BCMPMUCTL
#define CCCTL_ENAB(sih) (0)
#define CCPLL_ENAB(sih) (0)
#else
#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
#endif
typedef void (*gpio_handler_t)(uint32 stat, void *arg);
extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
void *sdh, char **vars, uint *varsz);
extern si_t *si_kattach(osl_t *osh);
extern void si_detach(si_t *sih);
extern bool si_pci_war16165(si_t *sih);
extern uint si_corelist(si_t *sih, uint coreid[]);
extern uint si_coreid(si_t *sih);
extern uint si_flag(si_t *sih);
extern uint si_intflag(si_t *sih);
extern uint si_coreidx(si_t *sih);
extern uint si_coreunit(si_t *sih);
extern uint si_corevendor(si_t *sih);
extern uint si_corerev(si_t *sih);
extern void *si_osh(si_t *sih);
extern void si_setosh(si_t *sih, osl_t *osh);
extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
extern void *si_coreregs(si_t *sih);
extern void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val);
extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
extern bool si_iscoreup(si_t *sih);
extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
extern void *si_setcoreidx(si_t *sih, uint coreidx);
extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
extern int si_numaddrspaces(si_t *sih);
extern uint32 si_addrspace(si_t *sih, uint asidx);
extern uint32 si_addrspacesize(si_t *sih, uint asidx);
extern int si_corebist(si_t *sih);
extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
extern void si_core_tofixup(si_t *sih);
extern void si_core_disable(si_t *sih, uint32 bits);
extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
extern uint32 si_clock(si_t *sih);
extern void si_clock_pmu_spuravoid(si_t *sih, bool spuravoid);
extern uint32 si_alp_clock(si_t *sih);
extern uint32 si_ilp_clock(si_t *sih);
extern void si_pci_setup(si_t *sih, uint coremask);
extern void si_pcmcia_init(si_t *sih);
extern void si_setint(si_t *sih, int siflag);
extern bool si_backplane64(si_t *sih);
extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
void *intrsenabled_fn, void *intr_arg);
extern void si_deregister_intr_callback(si_t *sih);
extern void si_clkctl_init(si_t *sih);
extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
extern bool si_clkctl_cc(si_t *sih, uint mode);
extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
extern bool si_backplane64(si_t *sih);
extern void si_btcgpiowar(si_t *sih);
extern bool si_deviceremoved(si_t *sih);
extern uint32 si_socram_size(si_t *sih);
extern void si_watchdog(si_t *sih, uint ticks);
extern void si_watchdog_ms(si_t *sih, uint32 ms);
extern void *si_gpiosetcore(si_t *sih);
extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioin(si_t *sih);
extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg);
extern void si_gpio_handler_unregister(si_t *sih, void* gpioh);
extern void si_gpio_handler_process(si_t *sih);
extern bool si_pci_pmecap(si_t *sih);
struct osl_info;
extern bool si_pci_fastpmecap(struct osl_info *osh);
extern bool si_pci_pmeclr(si_t *sih);
extern void si_pci_pmeen(si_t *sih);
extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
extern void si_sdio_init(si_t *sih);
extern uint16 si_d11_devid(si_t *sih);
extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
#define si_eci_init(sih) (0)
#define si_eci_notify_bt(sih, type, val, interrupt) (0)
extern int si_devpath(si_t *sih, char *path, int size);
extern char *si_getdevpathvar(si_t *sih, const char *name);
extern int si_getdevpathintvar(si_t *sih, const char *name);
extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
extern void si_war42780_clkreq(si_t *sih, bool clkreq);
extern void si_pci_sleep(si_t *sih);
extern void si_pci_down(si_t *sih);
extern void si_pci_up(si_t *sih);
extern void si_pcie_war_ovr_disable(si_t *sih);
extern void si_pcie_extendL1timer(si_t *sih, bool extend);
extern int si_pci_fixcfg(si_t *sih);
#endif

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/*
* TRX image file header format.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: trxhdr.h,v 13.11.310.1 2008/08/17 12:58:58 Exp $
*/
#include <typedefs.h>
#define TRX_MAGIC 0x30524448 /* "HDR0" */
#define TRX_VERSION 1 /* Version 1 */
#define TRX_MAX_LEN 0x3A0000 /* Max length */
#define TRX_NO_HEADER 1 /* Do not write TRX header */
#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
#define TRX_MAX_OFFSET 3 /* Max number of individual files */
#define TRX_UNCOMP_IMAGE 0x20 /* Trx contains uncompressed rtecdc.bin image */
struct trx_header {
uint32 magic; /* "HDR0" */
uint32 len; /* Length of file including header */
uint32 crc32; /* 32-bit CRC from flag_version to end of file */
uint32 flag_version; /* 0:15 flags, 16:31 version */
uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
};
/* Compatibility */
typedef struct trx_header TRXHDR, *PTRXHDR;

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drivers/net/wireless/bcm4329_245/include/typedefs.h Normal file
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/*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: typedefs.h,v 1.85.34.1.2.5 2009/01/27 04:09:40 Exp $
*/
#ifndef _TYPEDEFS_H_
#define _TYPEDEFS_H_
#ifdef SITE_TYPEDEFS
#include "site_typedefs.h"
#else
#ifdef __cplusplus
#define TYPEDEF_BOOL
#ifndef FALSE
#define FALSE false
#endif
#ifndef TRUE
#define TRUE true
#endif
#else
#endif
#if defined(__x86_64__)
#define TYPEDEF_UINTPTR
typedef unsigned long long int uintptr;
#endif
#if defined(TARGETOS_nucleus)
#include <stddef.h>
#define TYPEDEF_FLOAT_T
#endif
#if defined(_NEED_SIZE_T_)
typedef long unsigned int size_t;
#endif
#ifdef __DJGPP__
typedef long unsigned int size_t;
#endif
#define TYPEDEF_UINT
#ifndef TARGETENV_android
#define TYPEDEF_USHORT
#define TYPEDEF_ULONG
#endif
#ifdef __KERNEL__
#include <linux/version.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
#define TYPEDEF_BOOL
#endif
#endif
#if defined(__GNUC__) && defined(__STRICT_ANSI__)
#define TYPEDEF_INT64
#define TYPEDEF_UINT64
#endif
#if defined(__ICL)
#define TYPEDEF_INT64
#if defined(__STDC__)
#define TYPEDEF_UINT64
#endif
#endif
#if !defined(__DJGPP__) && !defined(TARGETOS_nucleus)
#if defined(__KERNEL__)
#include <linux/types.h>
#else
#include <sys/types.h>
#endif
#endif
#define USE_TYPEDEF_DEFAULTS
#endif
#ifdef USE_TYPEDEF_DEFAULTS
#undef USE_TYPEDEF_DEFAULTS
#ifndef TYPEDEF_BOOL
typedef unsigned char bool;
#endif
#ifndef TYPEDEF_UCHAR
typedef unsigned char uchar;
#endif
#ifndef TYPEDEF_USHORT
typedef unsigned short ushort;
#endif
#ifndef TYPEDEF_UINT
typedef unsigned int uint;
#endif
#ifndef TYPEDEF_ULONG
typedef unsigned long ulong;
#endif
#ifndef TYPEDEF_UINT8
typedef unsigned char uint8;
#endif
#ifndef TYPEDEF_UINT16
typedef unsigned short uint16;
#endif
#ifndef TYPEDEF_UINT32
typedef unsigned int uint32;
#endif
#ifndef TYPEDEF_UINT64
typedef unsigned long long uint64;
#endif
#ifndef TYPEDEF_UINTPTR
typedef unsigned int uintptr;
#endif
#ifndef TYPEDEF_INT8
typedef signed char int8;
#endif
#ifndef TYPEDEF_INT16
typedef signed short int16;
#endif
#ifndef TYPEDEF_INT32
typedef signed int int32;
#endif
#ifndef TYPEDEF_INT64
typedef signed long long int64;
#endif
#ifndef TYPEDEF_FLOAT32
typedef float float32;
#endif
#ifndef TYPEDEF_FLOAT64
typedef double float64;
#endif
#ifndef TYPEDEF_FLOAT_T
#if defined(FLOAT32)
typedef float32 float_t;
#else
typedef float64 float_t;
#endif
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef NULL
#define NULL 0
#endif
#ifndef OFF
#define OFF 0
#endif
#ifndef ON
#define ON 1
#endif
#define AUTO (-1)
#ifndef PTRSZ
#define PTRSZ sizeof(char*)
#endif
#if defined(__GNUC__)
#define BWL_COMPILER_GNU
#elif defined(__CC_ARM)
#define BWL_COMPILER_ARMCC
#else
#error "Unknown compiler!"
#endif
#ifndef INLINE
#if defined(BWL_COMPILER_MICROSOFT)
#define INLINE __inline
#elif defined(BWL_COMPILER_GNU)
#define INLINE __inline__
#elif defined(BWL_COMPILER_ARMCC)
#define INLINE __inline
#else
#define INLINE
#endif
#endif
#undef TYPEDEF_BOOL
#undef TYPEDEF_UCHAR
#undef TYPEDEF_USHORT
#undef TYPEDEF_UINT
#undef TYPEDEF_ULONG
#undef TYPEDEF_UINT8
#undef TYPEDEF_UINT16
#undef TYPEDEF_UINT32
#undef TYPEDEF_UINT64
#undef TYPEDEF_UINTPTR
#undef TYPEDEF_INT8
#undef TYPEDEF_INT16
#undef TYPEDEF_INT32
#undef TYPEDEF_INT64
#undef TYPEDEF_FLOAT32
#undef TYPEDEF_FLOAT64
#undef TYPEDEF_FLOAT_T
#endif
#define UNUSED_PARAMETER(x) (void)(x)
#include <bcmdefs.h>
#endif

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drivers/net/wireless/bcm4329_245/include/wlioctl.h Normal file
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drivers/net/wireless/bcm4329_245/linux_osl.c Normal file
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/*
* Linux OS Independent Layer
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: linux_osl.c,v 1.125.12.3.8.7 2010/05/04 21:10:04 Exp $
*/
#define LINUX_OSL
#if defined(CHROMIUMOS_COMPAT_WIRELESS)
#include <linux/sched.h>
#endif
#include <typedefs.h>
#include <bcmendian.h>
#include <linuxver.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <linux/delay.h>
#include <pcicfg.h>
#define PCI_CFG_RETRY 10
#define OS_HANDLE_MAGIC 0x1234abcd
#define BCM_MEM_FILENAME_LEN 24
#ifdef DHD_USE_STATIC_BUF
#define MAX_STATIC_BUF_NUM 16
#define STATIC_BUF_SIZE (PAGE_SIZE*2)
#define STATIC_BUF_TOTAL_LEN (MAX_STATIC_BUF_NUM*STATIC_BUF_SIZE)
typedef struct bcm_static_buf {
struct semaphore static_sem;
unsigned char *buf_ptr;
unsigned char buf_use[MAX_STATIC_BUF_NUM];
} bcm_static_buf_t;
static bcm_static_buf_t *bcm_static_buf = 0;
#define MAX_STATIC_PKT_NUM 8
typedef struct bcm_static_pkt {
struct sk_buff *skb_4k[MAX_STATIC_PKT_NUM];
struct sk_buff *skb_8k[MAX_STATIC_PKT_NUM];
struct semaphore osl_pkt_sem;
unsigned char pkt_use[MAX_STATIC_PKT_NUM*2];
} bcm_static_pkt_t;
static bcm_static_pkt_t *bcm_static_skb = 0;
#endif
typedef struct bcm_mem_link {
struct bcm_mem_link *prev;
struct bcm_mem_link *next;
uint size;
int line;
char file[BCM_MEM_FILENAME_LEN];
} bcm_mem_link_t;
struct osl_info {
osl_pubinfo_t pub;
uint magic;
void *pdev;
uint malloced;
uint failed;
uint bustype;
bcm_mem_link_t *dbgmem_list;
};
static int16 linuxbcmerrormap[] =
{ 0,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-E2BIG,
-E2BIG,
-EBUSY,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EFAULT,
-ENOMEM,
-EOPNOTSUPP,
-EMSGSIZE,
-EINVAL,
-EPERM,
-ENOMEM,
-EINVAL,
-ERANGE,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EINVAL,
-EIO,
-ENODEV,
-EINVAL,
-EIO,
-EIO,
-EINVAL,
-EINVAL,
#if BCME_LAST != -41
#error "You need to add a OS error translation in the linuxbcmerrormap \
for new error code defined in bcmutils.h"
#endif
};
int
osl_error(int bcmerror)
{
if (bcmerror > 0)
bcmerror = 0;
else if (bcmerror < BCME_LAST)
bcmerror = BCME_ERROR;
return linuxbcmerrormap[-bcmerror];
}
void * dhd_os_prealloc(int section, unsigned long size);
osl_t *
osl_attach(void *pdev, uint bustype, bool pkttag)
{
osl_t *osh;
osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
ASSERT(osh);
bzero(osh, sizeof(osl_t));
ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
osh->magic = OS_HANDLE_MAGIC;
osh->malloced = 0;
osh->failed = 0;
osh->dbgmem_list = NULL;
osh->pdev = pdev;
osh->pub.pkttag = pkttag;
osh->bustype = bustype;
switch (bustype) {
case PCI_BUS:
case SI_BUS:
case PCMCIA_BUS:
osh->pub.mmbus = TRUE;
break;
case JTAG_BUS:
case SDIO_BUS:
case USB_BUS:
case SPI_BUS:
osh->pub.mmbus = FALSE;
break;
default:
ASSERT(FALSE);
break;
}
#ifdef DHD_USE_STATIC_BUF
if (!bcm_static_buf) {
if (!(bcm_static_buf = (bcm_static_buf_t *)dhd_os_prealloc(3, STATIC_BUF_SIZE+
STATIC_BUF_TOTAL_LEN))) {
printk("can not alloc static buf!\n");
}
else
printk("alloc static buf at %x!\n", (unsigned int)bcm_static_buf);
init_MUTEX(&bcm_static_buf->static_sem);
bcm_static_buf->buf_ptr = (unsigned char *)bcm_static_buf + STATIC_BUF_SIZE;
}
if (!bcm_static_skb)
{
int i;
void *skb_buff_ptr = 0;
bcm_static_skb = (bcm_static_pkt_t *)((char *)bcm_static_buf + 2048);
skb_buff_ptr = dhd_os_prealloc(4, 0);
bcopy(skb_buff_ptr, bcm_static_skb, sizeof(struct sk_buff *)*16);
for (i = 0; i < MAX_STATIC_PKT_NUM*2; i++)
bcm_static_skb->pkt_use[i] = 0;
init_MUTEX(&bcm_static_skb->osl_pkt_sem);
}
#endif
return osh;
}
void
osl_detach(osl_t *osh)
{
if (osh == NULL)
return;
#ifdef DHD_USE_STATIC_BUF
if (bcm_static_buf) {
bcm_static_buf = 0;
}
if (bcm_static_skb) {
bcm_static_skb = 0;
}
#endif
ASSERT(osh->magic == OS_HANDLE_MAGIC);
kfree(osh);
}
void*
osl_pktget(osl_t *osh, uint len)
{
struct sk_buff *skb;
if ((skb = dev_alloc_skb(len))) {
skb_put(skb, len);
skb->priority = 0;
osh->pub.pktalloced++;
}
return ((void*) skb);
}
void
osl_pktfree(osl_t *osh, void *p, bool send)
{
struct sk_buff *skb, *nskb;
skb = (struct sk_buff*) p;
if (send && osh->pub.tx_fn)
osh->pub.tx_fn(osh->pub.tx_ctx, p, 0);
while (skb) {
nskb = skb->next;
skb->next = NULL;
if (skb->destructor) {
dev_kfree_skb_any(skb);
} else {
dev_kfree_skb(skb);
}
osh->pub.pktalloced--;
skb = nskb;
}
}
#ifdef DHD_USE_STATIC_BUF
void*
osl_pktget_static(osl_t *osh, uint len)
{
int i = 0;
struct sk_buff *skb;
if (len > (PAGE_SIZE*2))
{
printk("Do we really need this big skb??\n");
return osl_pktget(osh, len);
}
down(&bcm_static_skb->osl_pkt_sem);
if (len <= PAGE_SIZE)
{
for (i = 0; i < MAX_STATIC_PKT_NUM; i++)
{
if (bcm_static_skb->pkt_use[i] == 0)
break;
}
if (i != MAX_STATIC_PKT_NUM)
{
bcm_static_skb->pkt_use[i] = 1;
up(&bcm_static_skb->osl_pkt_sem);
skb = bcm_static_skb->skb_4k[i];
skb->tail = skb->data + len;
skb->len = len;
return skb;
}
}
for (i = 0; i < MAX_STATIC_PKT_NUM; i++)
{
if (bcm_static_skb->pkt_use[i+MAX_STATIC_PKT_NUM] == 0)
break;
}
if (i != MAX_STATIC_PKT_NUM)
{
bcm_static_skb->pkt_use[i+MAX_STATIC_PKT_NUM] = 1;
up(&bcm_static_skb->osl_pkt_sem);
skb = bcm_static_skb->skb_8k[i];
skb->tail = skb->data + len;
skb->len = len;
return skb;
}
up(&bcm_static_skb->osl_pkt_sem);
printk("all static pkt in use!\n");
return osl_pktget(osh, len);
}
void
osl_pktfree_static(osl_t *osh, void *p, bool send)
{
int i;
for (i = 0; i < MAX_STATIC_PKT_NUM*2; i++)
{
if (p == bcm_static_skb->skb_4k[i])
{
down(&bcm_static_skb->osl_pkt_sem);
bcm_static_skb->pkt_use[i] = 0;
up(&bcm_static_skb->osl_pkt_sem);
return;
}
}
return osl_pktfree(osh, p, send);
}
#endif
uint32
osl_pci_read_config(osl_t *osh, uint offset, uint size)
{
uint val = 0;
uint retry = PCI_CFG_RETRY;
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
ASSERT(size == 4);
do {
pci_read_config_dword(osh->pdev, offset, &val);
if (val != 0xffffffff)
break;
} while (retry--);
return (val);
}
void
osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
{
uint retry = PCI_CFG_RETRY;
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
ASSERT(size == 4);
do {
pci_write_config_dword(osh->pdev, offset, val);
if (offset != PCI_BAR0_WIN)
break;
if (osl_pci_read_config(osh, offset, size) == val)
break;
} while (retry--);
}
uint
osl_pci_bus(osl_t *osh)
{
ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
return ((struct pci_dev *)osh->pdev)->bus->number;
}
uint
osl_pci_slot(osl_t *osh)
{
ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
}
static void
osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
{
}
void
osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
{
osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
}
void
osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
{
osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
}
void*
osl_malloc(osl_t *osh, uint size)
{
void *addr;
if (osh)
ASSERT(osh->magic == OS_HANDLE_MAGIC);
#ifdef DHD_USE_STATIC_BUF
if (bcm_static_buf)
{
int i = 0;
if ((size >= PAGE_SIZE)&&(size <= STATIC_BUF_SIZE))
{
down(&bcm_static_buf->static_sem);
for (i = 0; i < MAX_STATIC_BUF_NUM; i++)
{
if (bcm_static_buf->buf_use[i] == 0)
break;
}
if (i == MAX_STATIC_BUF_NUM)
{
up(&bcm_static_buf->static_sem);
printk("all static buff in use!\n");
goto original;
}
bcm_static_buf->buf_use[i] = 1;
up(&bcm_static_buf->static_sem);
bzero(bcm_static_buf->buf_ptr+STATIC_BUF_SIZE*i, size);
if (osh)
osh->malloced += size;
return ((void *)(bcm_static_buf->buf_ptr+STATIC_BUF_SIZE*i));
}
}
original:
#endif
if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
if (osh)
osh->failed++;
return (NULL);
}
if (osh)
osh->malloced += size;
return (addr);
}
void
osl_mfree(osl_t *osh, void *addr, uint size)
{
#ifdef DHD_USE_STATIC_BUF
if (bcm_static_buf)
{
if ((addr > (void *)bcm_static_buf) && ((unsigned char *)addr
<= ((unsigned char *)bcm_static_buf + STATIC_BUF_TOTAL_LEN)))
{
int buf_idx = 0;
buf_idx = ((unsigned char *)addr - bcm_static_buf->buf_ptr)/STATIC_BUF_SIZE;
down(&bcm_static_buf->static_sem);
bcm_static_buf->buf_use[buf_idx] = 0;
up(&bcm_static_buf->static_sem);
if (osh) {
ASSERT(osh->magic == OS_HANDLE_MAGIC);
osh->malloced -= size;
}
return;
}
}
#endif
if (osh) {
ASSERT(osh->magic == OS_HANDLE_MAGIC);
osh->malloced -= size;
}
kfree(addr);
}
uint
osl_malloced(osl_t *osh)
{
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
return (osh->malloced);
}
uint
osl_malloc_failed(osl_t *osh)
{
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
return (osh->failed);
}
void*
osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
{
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
}
void
osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
{
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
}
uint
osl_dma_map(osl_t *osh, void *va, uint size, int direction)
{
int dir;
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
return (pci_map_single(osh->pdev, va, size, dir));
}
void
osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
{
int dir;
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
}
void
osl_delay(uint usec)
{
uint d;
while (usec > 0) {
d = MIN(usec, 1000);
udelay(d);
usec -= d;
}
}
void *
osl_pktdup(osl_t *osh, void *skb)
{
void * p;
if ((p = skb_clone((struct sk_buff*)skb, GFP_ATOMIC)) == NULL)
return NULL;
if (osh->pub.pkttag)
bzero((void*)((struct sk_buff *)p)->cb, OSL_PKTTAG_SZ);
osh->pub.pktalloced++;
return (p);
}

163
drivers/net/wireless/bcm4329_245/miniopt.c Normal file
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@ -0,0 +1,163 @@
/*
* Description.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
* $Id: miniopt.c,v 1.1.6.4 2009/09/25 00:32:01 Exp $
*/
/* ---- Include Files ---------------------------------------------------- */
#include <typedefs.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "miniopt.h"
/* ---- Public Variables ------------------------------------------------- */
/* ---- Private Constants and Types -------------------------------------- */
/* ---- Private Variables ------------------------------------------------ */
/* ---- Private Function Prototypes -------------------------------------- */
/* ---- Functions -------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
void
miniopt_init(miniopt_t *t, const char* name, const char* flags, bool longflags)
{
static const char *null_flags = "";
memset(t, 0, sizeof(miniopt_t));
t->name = name;
if (flags == NULL)
t->flags = null_flags;
else
t->flags = flags;
t->longflags = longflags;
}
/* ----------------------------------------------------------------------- */
int
miniopt(miniopt_t *t, char **argv)
{
int keylen;
char *p, *eq, *valstr, *endptr = NULL;
int err = 0;
t->consumed = 0;
t->positional = FALSE;
memset(t->key, 0, MINIOPT_MAXKEY);
t->opt = '\0';
t->valstr = NULL;
t->good_int = FALSE;
valstr = NULL;
if (*argv == NULL) {
err = -1;
goto exit;
}
p = *argv++;
t->consumed++;
if (!t->opt_end && !strcmp(p, "--")) {
t->opt_end = TRUE;
if (*argv == NULL) {
err = -1;
goto exit;
}
p = *argv++;
t->consumed++;
}
if (t->opt_end) {
t->positional = TRUE;
valstr = p;
}
else if (!strncmp(p, "--", 2)) {
eq = strchr(p, '=');
if (eq == NULL && !t->longflags) {
fprintf(stderr,
"%s: missing \" = \" in long param \"%s\"\n", t->name, p);
err = 1;
goto exit;
}
keylen = eq ? (eq - (p + 2)) : (int)strlen(p) - 2;
if (keylen > 63) keylen = 63;
memcpy(t->key, p + 2, keylen);
if (eq) {
valstr = eq + 1;
if (*valstr == '\0') {
fprintf(stderr,
"%s: missing value after \" = \" in long param \"%s\"\n",
t->name, p);
err = 1;
goto exit;
}
}
}
else if (!strncmp(p, "-", 1)) {
t->opt = p[1];
if (strlen(p) > 2) {
fprintf(stderr,
"%s: only single char options, error on param \"%s\"\n",
t->name, p);
err = 1;
goto exit;
}
if (strchr(t->flags, t->opt)) {
/* this is a flag option, no value expected */
valstr = NULL;
} else {
if (*argv == NULL) {
fprintf(stderr,
"%s: missing value parameter after \"%s\"\n", t->name, p);
err = 1;
goto exit;
}
valstr = *argv;
argv++;
t->consumed++;
}
} else {
t->positional = TRUE;
valstr = p;
}
/* parse valstr as int just in case */
if (valstr) {
t->uval = (uint)strtoul(valstr, &endptr, 0);
t->val = (int)t->uval;
t->good_int = (*endptr == '\0');
}
t->valstr = valstr;
exit:
if (err == 1)
t->opt = '?';
return err;
}

1004
drivers/net/wireless/bcm4329_245/sbutils.c Normal file
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File diff suppressed because it is too large Load Diff

1527
drivers/net/wireless/bcm4329_245/siutils.c Normal file
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File diff suppressed because it is too large Load Diff

213
drivers/net/wireless/bcm4329_245/siutils_priv.h Normal file
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@ -0,0 +1,213 @@
/*
* Include file private to the SOC Interconnect support files.
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: siutils_priv.h,v 1.3.10.5.4.2 2009/09/22 13:28:16 Exp $
*/
#ifndef _siutils_priv_h_
#define _siutils_priv_h_
/* debug/trace */
#define SI_ERROR(args)
#define SI_MSG(args)
#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
typedef uint32 (*si_intrsoff_t)(void *intr_arg);
typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
typedef bool (*si_intrsenabled_t)(void *intr_arg);
typedef struct gpioh_item {
void *arg;
bool level;
gpio_handler_t handler;
uint32 event;
struct gpioh_item *next;
} gpioh_item_t;
/* misc si info needed by some of the routines */
typedef struct si_common_info {
void *regs[SI_MAXCORES]; /* other regs va */
void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
uint coreid[SI_MAXCORES]; /* id of each core */
uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
uint32 oob_router; /* oob router registers for axi */
uint8 attach_count;
} si_common_info_t;
typedef struct si_info {
struct si_pub pub; /* back plane public state (must be first field) */
void *osh; /* osl os handle */
void *sdh; /* bcmsdh handle */
void *pch; /* PCI/E core handle */
uint dev_coreid; /* the core provides driver functions */
void *intr_arg; /* interrupt callback function arg */
si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
gpioh_item_t *gpioh_head; /* GPIO event handlers list */
bool memseg; /* flag to toggle MEM_SEG register */
char *vars;
uint varsz;
void *curmap; /* current regs va */
uint curidx; /* current core index */
uint numcores; /* # discovered cores */
void *curwrap; /* current wrapper va */
si_common_info_t *common_info; /* Common information for all the cores in a chip */
} si_info_t;
#define SI_INFO(sih) (si_info_t *)(uintptr)sih
#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
ISALIGNED((x), SI_CORE_SIZE))
#define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
#define BADCOREADDR 0
#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
#define BADIDX (SI_MAXCORES + 1)
#define NOREV -1 /* Invalid rev */
#define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
((si)->pub.buscoretype == PCI_CORE_ID))
#define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
((si)->pub.buscoretype == PCIE_CORE_ID))
#define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
/* Newer chips can access PCI/PCIE and CC core without requiring to change
* PCI BAR0 WIN
*/
#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
(((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
/*
* Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
* after core switching to avoid invalid register accesss inside ISR.
*/
#define INTR_OFF(si, intr_val) \
if ((si)->intrsoff_fn && (si)->common_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
#define INTR_RESTORE(si, intr_val) \
if ((si)->intrsrestore_fn && (si)->common_info->coreid[(si)->curidx] == (si)->dev_coreid) {\
(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
/* dynamic clock control defines */
#define LPOMINFREQ 25000 /* low power oscillator min */
#define LPOMAXFREQ 43000 /* low power oscillator max */
#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
#define PCIMINFREQ 25000000 /* 25 MHz */
#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
#define PCI_FORCEHT(si) \
(((PCIE(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \
((PCI(si) || PCIE(si)) && (si->pub.chip == BCM4321_CHIP_ID)))
/* GPIO Based LED powersave defines */
#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
#ifndef DEFAULT_GPIOTIMERVAL
#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
#endif
/* Silicon Backplane externs */
extern void sb_scan(si_t *sih, void *regs, uint devid);
extern uint sb_coreid(si_t *sih);
extern uint sb_flag(si_t *sih);
extern void sb_setint(si_t *sih, int siflag);
extern uint sb_corevendor(si_t *sih);
extern uint sb_corerev(si_t *sih);
extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
extern bool sb_iscoreup(si_t *sih);
extern void *sb_setcoreidx(si_t *sih, uint coreidx);
extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
extern void sb_commit(si_t *sih);
extern uint32 sb_base(uint32 admatch);
extern uint32 sb_size(uint32 admatch);
extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
extern void sb_core_tofixup(si_t *sih);
extern void sb_core_disable(si_t *sih, uint32 bits);
extern uint32 sb_addrspace(si_t *sih, uint asidx);
extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
extern int sb_numaddrspaces(si_t *sih);
extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
/* Wake-on-wireless-LAN (WOWL) */
extern bool sb_pci_pmecap(si_t *sih);
struct osl_info;
extern bool sb_pci_fastpmecap(struct osl_info *osh);
extern bool sb_pci_pmeclr(si_t *sih);
extern void sb_pci_pmeen(si_t *sih);
extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
/* AMBA Interconnect exported externs */
extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
void *sdh, char **vars, uint *varsz);
extern si_t *ai_kattach(osl_t *osh);
extern void ai_scan(si_t *sih, void *regs, uint devid);
extern uint ai_flag(si_t *sih);
extern void ai_setint(si_t *sih, int siflag);
extern uint ai_coreidx(si_t *sih);
extern uint ai_corevendor(si_t *sih);
extern uint ai_corerev(si_t *sih);
extern bool ai_iscoreup(si_t *sih);
extern void *ai_setcoreidx(si_t *sih, uint coreidx);
extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
extern void ai_core_disable(si_t *sih, uint32 bits);
extern int ai_numaddrspaces(si_t *sih);
extern uint32 ai_addrspace(si_t *sih, uint asidx);
extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val);
#endif /* _siutils_priv_h_ */

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/*
* Linux Cfg80211 support
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: wl_cfg80211.h,v 1.1.2.19 2010/05/04 21:21:00 Exp $
*/
#ifndef _wl_cfg80211_h_
#define _wl_cfg80211_h_
#include <linux/wireless.h>
#include <typedefs.h>
#include <proto/ethernet.h>
#include <wlioctl.h>
#include <linux/wireless.h>
#include <net/cfg80211.h>
struct wl_conf;
struct wl_iface;
struct wl_priv;
struct wl_security;
struct wl_ibss;
#if defined(IL_BIGENDIAN)
#include <bcmendian.h>
#define htod32(i) (bcmswap32(i))
#define htod16(i) (bcmswap16(i))
#define dtoh32(i) (bcmswap32(i))
#define dtoh16(i) (bcmswap16(i))
#define htodchanspec(i) htod16(i)
#define dtohchanspec(i) dtoh16(i)
#else
#define htod32(i) i
#define htod16(i) i
#define dtoh32(i) i
#define dtoh16(i) i
#define htodchanspec(i) i
#define dtohchanspec(i) i
#endif
#define WL_DBG_NONE 0
#define WL_DBG_DBG (1 << 2)
#define WL_DBG_INFO (1 << 1)
#define WL_DBG_ERR (1 << 0)
#define WL_DBG_MASK ((WL_DBG_DBG | WL_DBG_INFO | WL_DBG_ERR) << 1)
#define WL_DBG_LEVEL 1 /* 0 invalidates all debug messages. default is 1 */
#define WL_ERR(args) \
do { \
if (wl_dbg_level & WL_DBG_ERR) { \
if (net_ratelimit()) { \
printk("ERROR @%s : ", __FUNCTION__); \
printk args; \
} \
} \
} while (0)
#define WL_INFO(args) \
do { \
if (wl_dbg_level & WL_DBG_INFO) { \
if (net_ratelimit()) { \
printk("INFO @%s : ", __FUNCTION__); \
printk args; \
} \
} \
} while (0)
#if (WL_DBG_LEVEL > 0)
#define WL_DBG(args) \
do { \
if (wl_dbg_level & WL_DBG_DBG) { \
printk("DEBUG @%s :", __FUNCTION__); \
printk args; \
} \
} while (0)
#else /* !(WL_DBG_LEVEL > 0) */
#define WL_DBG(args)
#endif /* (WL_DBG_LEVEL > 0) */
#define WL_SCAN_RETRY_MAX 3 /* used for ibss scan */
#define WL_NUM_SCAN_MAX 1
#define WL_NUM_PMKIDS_MAX MAXPMKID /* will be used for 2.6.33 kernel
* or later
*/
#define WL_SCAN_BUF_MAX (1024 * 8)
#define WL_TLV_INFO_MAX 1024
#define WL_BSS_INFO_MAX 2048
#define WL_ASSOC_INFO_MAX 512 /*
* needs to grab assoc info from dongle to
* report it to cfg80211 through "connect"
* event
*/
#define WL_IOCTL_LEN_MAX 1024
#define WL_EXTRA_BUF_MAX 2048
#define WL_ISCAN_BUF_MAX 2048 /* the buf lengh can be WLC_IOCTL_MAXLEN (8K)
* to reduce iteration
*/
#define WL_ISCAN_TIMER_INTERVAL_MS 3000
#define WL_SCAN_ERSULTS_LAST (WL_SCAN_RESULTS_NO_MEM+1)
#define WL_AP_MAX 256 /* virtually unlimitted as long
* as kernel memory allows
*/
#define WL_FILE_NAME_MAX 256
/* dongle status */
enum wl_status {
WL_STATUS_READY,
WL_STATUS_SCANNING,
WL_STATUS_SCAN_ABORTING,
WL_STATUS_CONNECTING,
WL_STATUS_CONNECTED
};
/* wi-fi mode */
enum wl_mode {
WL_MODE_BSS,
WL_MODE_IBSS,
WL_MODE_AP
};
/* dongle profile list */
enum wl_prof_list {
WL_PROF_MODE,
WL_PROF_SSID,
WL_PROF_SEC,
WL_PROF_IBSS,
WL_PROF_BAND,
WL_PROF_BSSID,
WL_PROF_ACT
};
/* dongle iscan state */
enum wl_iscan_state {
WL_ISCAN_STATE_IDLE,
WL_ISCAN_STATE_SCANING
};
/* fw downloading status */
enum wl_fw_status {
WL_FW_LOADING_DONE,
WL_NVRAM_LOADING_DONE
};
/* dongle configuration */
struct wl_conf {
uint32 mode; /* adhoc , infrastructure or ap */
uint32 frag_threshold;
uint32 rts_threshold;
uint32 retry_short;
uint32 retry_long;
int32 tx_power;
struct ieee80211_channel channel;
};
/* cfg80211 main event loop */
struct wl_event_loop {
int32 (*handler[WLC_E_LAST])(struct wl_priv *wl, struct net_device *ndev,
const wl_event_msg_t *e, void *data);
};
/* representing interface of cfg80211 plane */
struct wl_iface {
struct wl_priv *wl;
};
struct wl_dev {
void *driver_data; /* to store cfg80211 object information */
};
/* bss inform structure for cfg80211 interface */
struct wl_cfg80211_bss_info {
uint16 band;
uint16 channel;
int16 rssi;
uint16 frame_len;
uint8 frame_buf[1];
};
/* basic structure of scan request */
struct wl_scan_req {
struct wlc_ssid ssid;
};
/* basic structure of information element */
struct wl_ie {
uint16 offset;
uint8 buf[WL_TLV_INFO_MAX];
};
/* event queue for cfg80211 main event */
struct wl_event_q {
struct list_head eq_list;
uint32 etype;
wl_event_msg_t emsg;
int8 edata[1];
};
/* security information with currently associated ap */
struct wl_security {
uint32 wpa_versions;
uint32 auth_type;
uint32 cipher_pairwise;
uint32 cipher_group;
uint32 wpa_auth;
};
/* ibss information for currently joined ibss network */
struct wl_ibss {
uint8 beacon_interval; /* in millisecond */
uint8 atim; /* in millisecond */
int8 join_only;
uint8 band;
uint8 channel;
};
/* dongle profile */
struct wl_profile {
uint32 mode;
struct wlc_ssid ssid;
uint8 bssid[ETHER_ADDR_LEN];
struct wl_security sec;
struct wl_ibss ibss;
int32 band;
bool active;
};
/* dongle iscan event loop */
struct wl_iscan_eloop {
int32 (*handler[WL_SCAN_ERSULTS_LAST])(struct wl_priv *wl);
};
/* dongle iscan controller */
struct wl_iscan_ctrl {
struct net_device *dev;
struct timer_list timer;
uint32 timer_ms;
uint32 timer_on;
int32 state;
int32 pid;
struct semaphore sync;
struct completion exited;
struct wl_iscan_eloop el;
void *data;
int8 ioctl_buf[WLC_IOCTL_SMLEN];
int8 scan_buf[WL_ISCAN_BUF_MAX];
};
/* association inform */
struct wl_connect_info {
uint8 *req_ie;
int32 req_ie_len;
uint8 *resp_ie;
int32 resp_ie_len;
};
/* firmware /nvram downloading controller */
struct wl_fw_ctrl {
const struct firmware *fw_entry;
ulong status;
uint32 ptr;
int8 fw_name[WL_FILE_NAME_MAX];
int8 nvram_name[WL_FILE_NAME_MAX];
};
/* assoc ie length */
struct wl_assoc_ielen {
uint32 req_len;
uint32 resp_len;
};
/* wpa2 pmk list */
struct wl_pmk_list {
pmkid_list_t pmkids;
pmkid_t foo[MAXPMKID-1];
};
/* dongle private data of cfg80211 interface */
struct wl_priv {
struct wireless_dev *wdev; /* representing wl cfg80211 device */
struct wl_conf *conf; /* dongle configuration */
struct cfg80211_scan_request *scan_request; /* scan request object */
struct wl_event_loop el; /* main event loop */
struct list_head eq_list; /* used for event queue */
spinlock_t eq_lock; /* for event queue synchronization */
struct mutex usr_sync; /* maily for dongle up/down synchronization */
struct wl_scan_results *bss_list; /* bss_list holding scanned ap information */
struct wl_scan_results *scan_results;
struct wl_scan_req *scan_req_int; /* scan request object for internal purpose */
struct wl_cfg80211_bss_info *bss_info; /* bss information for cfg80211 layer */
struct wl_ie ie; /* information element object for internal purpose */
struct ether_addr bssid; /* bssid of currently engaged network */
struct semaphore event_sync; /* for synchronization of main event thread */
struct completion event_exit;
struct wl_profile *profile; /* holding dongle profile */
struct wl_iscan_ctrl *iscan; /* iscan controller */
struct wl_connect_info conn_info; /* association information container */
struct wl_fw_ctrl *fw; /* control firwmare / nvram paramter downloading */
struct wl_pmk_list *pmk_list; /* wpa2 pmk list */
int32 event_pid; /* pid of main event handler thread */
ulong status; /* current dongle status */
void * pub;
uint32 channel; /* current channel */
bool iscan_on; /* iscan on/off switch */
bool iscan_kickstart; /* indicate iscan already started */
bool active_scan; /* current scan mode */
bool ibss_starter; /* indicates this sta is ibss starter */
bool link_up; /* link/connection up flag */
bool pwr_save; /* indicate whether dongle to support power save mode */
bool dongle_up; /* indicate whether dongle up or not */
bool roam_on; /* on/off switch for dongle self-roaming */
bool scan_tried; /* indicates if first scan attempted */
uint8 *ioctl_buf; /* ioctl buffer */
uint8 *extra_buf; /* maily to grab assoc information */
uint8 ci[0] __attribute__((__aligned__(NETDEV_ALIGN)));
};
#define wl_to_dev(w) (wiphy_dev(wl->wdev->wiphy))
#define wl_to_wiphy(w) (w->wdev->wiphy)
#define wiphy_to_wl(w) ((struct wl_priv *)(wiphy_priv(w)))
#define wl_to_wdev(w) (w->wdev)
#define wdev_to_wl(w) ((struct wl_priv *)(wdev_priv(w)))
#define wl_to_ndev(w) (w->wdev->netdev)
#define ndev_to_wl(n) (wdev_to_wl(n->ieee80211_ptr))
#define ci_to_wl(c) (ci->wl)
#define wl_to_ci(w) (&w->ci)
#define wl_to_sr(w) (w->scan_req_int)
#define wl_to_ie(w) (&w->ie)
#define iscan_to_wl(i) ((struct wl_priv *)(i->data))
#define wl_to_iscan(w) (w->iscan)
#define wl_to_conn(w) (&w->conn_info)
inline static struct wl_bss_info * next_bss(struct wl_scan_results *list,
struct wl_bss_info *bss) {
return (bss = bss ?
(struct wl_bss_info *)((uintptr)bss + dtoh32(bss->length)) : list->bss_info);
}
#define for_each_bss(list, bss, __i) \
for (__i = 0; __i < list->count && __i < WL_AP_MAX; __i++, bss = next_bss(list, bss))
extern int32 wl_cfg80211_attach(struct net_device *ndev, void *data);
extern void wl_cfg80211_detach(void);
/* event handler from dongle */
extern void wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t *e, void* data);
extern void wl_cfg80211_sdio_func(void *func); /* set sdio function info */
extern int32 wl_cfg80211_up(void); /* dongle up */
extern int32 wl_cfg80211_down(void); /* dongle down */
extern void wl_cfg80211_dbg_level(uint32 level); /* set dongle debugging level */
extern void * wl_cfg80211_request_fw(int8 *file_name); /* request fw /nvram downloading */
extern int32 wl_cfg80211_read_fw(int8 *buf, uint32 size); /* read fw image */
extern void wl_cfg80211_release_fw(void); /* release fw */
extern int8 * wl_cfg80211_get_fwname(void); /* get firmware name for the dongle */
extern int8 * wl_cfg80211_get_nvramname(void); /* get nvram name for the dongle */
#endif /* _wl_cfg80211_h_ */

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/*
* Linux Wireless Extensions support
*
* Copyright (C) 1999-2010, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: wl_iw.h,v 1.5.34.1.6.25 2010/07/29 22:46:56 Exp $
*/
#ifndef _wl_iw_h_
#define _wl_iw_h_
#include <linux/wireless.h>
#include <typedefs.h>
#include <proto/ethernet.h>
#include <wlioctl.h>
#define WL_SCAN_PARAMS_SSID_MAX 10
#define GET_SSID "SSID="
#define GET_CHANNEL "CH="
#define GET_NPROBE "NPROBE="
#define GET_ACTIVE_ASSOC_DWELL "ACTIVE="
#define GET_PASSIVE_ASSOC_DWELL "PASSIVE="
#define GET_HOME_DWELL "HOME="
#define GET_SCAN_TYPE "TYPE="
#define BAND_GET_CMD "BANDGET"
#define BAND_SET_CMD "BANDSET"
#define SOFTAP 1
#define WL_IW_RSSI_MINVAL -200
#define WL_IW_RSSI_NO_SIGNAL -91
#define WL_IW_RSSI_VERY_LOW -80
#define WL_IW_RSSI_LOW -70
#define WL_IW_RSSI_GOOD -68
#define WL_IW_RSSI_VERY_GOOD -58
#define WL_IW_RSSI_EXCELLENT -57
#define WL_IW_RSSI_INVALID 0
#define MAX_WX_STRING 80
#define isprint(c) bcm_isprint(c)
#define WL_IW_SET_ACTIVE_SCAN (SIOCIWFIRSTPRIV+1)
#define WL_IW_GET_RSSI (SIOCIWFIRSTPRIV+3)
#define WL_IW_SET_PASSIVE_SCAN (SIOCIWFIRSTPRIV+5)
#define WL_IW_GET_LINK_SPEED (SIOCIWFIRSTPRIV+7)
#define WL_IW_GET_CURR_MACADDR (SIOCIWFIRSTPRIV+9)
#define WL_IW_SET_STOP (SIOCIWFIRSTPRIV+11)
#define WL_IW_SET_START (SIOCIWFIRSTPRIV+13)
#define WL_SET_AP_CFG (SIOCIWFIRSTPRIV+15)
#define WL_AP_STA_LIST (SIOCIWFIRSTPRIV+17)
#define WL_AP_MAC_FLTR (SIOCIWFIRSTPRIV+19)
#define WL_AP_BSS_START (SIOCIWFIRSTPRIV+21)
#define AP_LPB_CMD (SIOCIWFIRSTPRIV+23)
#define WL_AP_STOP (SIOCIWFIRSTPRIV+25)
#define WL_FW_RELOAD (SIOCIWFIRSTPRIV+27)
#define WL_COMBO_SCAN (SIOCIWFIRSTPRIV+29)
#define WL_AP_SPARE3 (SIOCIWFIRSTPRIV+31)
#define G_SCAN_RESULTS 8*1024
#define WE_ADD_EVENT_FIX 0x80
#define G_WLAN_SET_ON 0
#define G_WLAN_SET_OFF 1
#define CHECK_EXTRA_FOR_NULL(extra) \
if (!extra) { \
WL_ERROR(("%s: error : extra is null pointer\n", __FUNCTION__)); \
return -EINVAL; \
}
typedef struct wl_iw {
char nickname[IW_ESSID_MAX_SIZE];
struct iw_statistics wstats;
int spy_num;
uint32 pwsec;
uint32 gwsec;
bool privacy_invoked;
struct ether_addr spy_addr[IW_MAX_SPY];
struct iw_quality spy_qual[IW_MAX_SPY];
void *wlinfo;
dhd_pub_t * pub;
} wl_iw_t;
int wl_control_wl_start(struct net_device *dev);
#define WLC_IW_SS_CACHE_MAXLEN 512
#define WLC_IW_SS_CACHE_CTRL_FIELD_MAXLEN 32
#define WLC_IW_BSS_INFO_MAXLEN \
(WLC_IW_SS_CACHE_MAXLEN - WLC_IW_SS_CACHE_CTRL_FIELD_MAXLEN)
typedef struct wl_iw_ss_cache{
uint32 buflen;
uint32 version;
uint32 count;
wl_bss_info_t bss_info[1];
char dummy[WLC_IW_BSS_INFO_MAXLEN - sizeof(wl_bss_info_t)];
int dirty;
struct wl_iw_ss_cache *next;
} wl_iw_ss_cache_t;
typedef struct wl_iw_ss_cache_ctrl {
wl_iw_ss_cache_t *m_cache_head;
int m_link_down;
int m_timer_expired;
char m_active_bssid[ETHER_ADDR_LEN];
uint m_prev_scan_mode;
uint m_cons_br_scan_cnt;
struct timer_list *m_timer;
} wl_iw_ss_cache_ctrl_t;
typedef enum broadcast_first_scan {
BROADCAST_SCAN_FIRST_IDLE = 0,
BROADCAST_SCAN_FIRST_STARTED,
BROADCAST_SCAN_FIRST_RESULT_READY,
BROADCAST_SCAN_FIRST_RESULT_CONSUMED
} broadcast_first_scan_t;
#ifdef SOFTAP
#define SSID_LEN 33
#define SEC_LEN 16
#define KEY_LEN 65
#define PROFILE_OFFSET 32
struct ap_profile {
uint8 ssid[SSID_LEN];
uint8 sec[SEC_LEN];
uint8 key[KEY_LEN];
uint32 channel;
uint32 preamble;
uint32 max_scb;
};
#define MACLIST_MODE_DISABLED 0
#define MACLIST_MODE_ENABLED 1
#define MACLIST_MODE_ALLOW 2
struct mflist {
uint count;
struct ether_addr ea[16];
};
struct mac_list_set {
uint32 mode;
struct mflist white_list;
struct mflist black_list;
};
#endif
#if WIRELESS_EXT > 12
#include <net/iw_handler.h>
extern const struct iw_handler_def wl_iw_handler_def;
#endif
extern int wl_iw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
extern void wl_iw_event(struct net_device *dev, wl_event_msg_t *e, void* data);
extern int wl_iw_get_wireless_stats(struct net_device *dev, struct iw_statistics *wstats);
int wl_iw_attach(struct net_device *dev, void * dhdp);
void wl_iw_detach(void);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
#define IWE_STREAM_ADD_EVENT(info, stream, ends, iwe, extra) \
iwe_stream_add_event(info, stream, ends, iwe, extra)
#define IWE_STREAM_ADD_VALUE(info, event, value, ends, iwe, event_len) \
iwe_stream_add_value(info, event, value, ends, iwe, event_len)
#define IWE_STREAM_ADD_POINT(info, stream, ends, iwe, extra) \
iwe_stream_add_point(info, stream, ends, iwe, extra)
#else
#define IWE_STREAM_ADD_EVENT(info, stream, ends, iwe, extra) \
iwe_stream_add_event(stream, ends, iwe, extra)
#define IWE_STREAM_ADD_VALUE(info, event, value, ends, iwe, event_len) \
iwe_stream_add_value(event, value, ends, iwe, event_len)
#define IWE_STREAM_ADD_POINT(info, stream, ends, iwe, extra) \
iwe_stream_add_point(stream, ends, iwe, extra)
#endif
#if defined(CSCAN)
typedef struct cscan_tlv {
char prefix;
char version;
char subver;
char reserved;
} cscan_tlv_t;
#define CSCAN_COMMAND "CSCAN "
#define CSCAN_TLV_PREFIX 'S'
#define CSCAN_TLV_VERSION 1
#define CSCAN_TLV_SUBVERSION 0
#define CSCAN_TLV_TYPE_SSID_IE 'S'
#define CSCAN_TLV_TYPE_CHANNEL_IE 'C'
#define CSCAN_TLV_TYPE_NPROBE_IE 'N'
#define CSCAN_TLV_TYPE_ACTIVE_IE 'A'
#define CSCAN_TLV_TYPE_PASSIVE_IE 'P'
#define CSCAN_TLV_TYPE_HOME_IE 'H'
#define CSCAN_TLV_TYPE_STYPE_IE 'T'
extern int wl_iw_parse_channel_list_tlv(char** list_str, uint16* channel_list, \
int channel_num, int *bytes_left);
extern int wl_iw_parse_data_tlv(char** list_str, void *dst, int dst_size, \
const char token, int input_size, int *bytes_left);
extern int wl_iw_parse_ssid_list_tlv(char** list_str, wlc_ssid_t* ssid, \
int max, int *bytes_left);
extern int wl_iw_parse_ssid_list(char** list_str, wlc_ssid_t* ssid, int idx, int max);
extern int wl_iw_parse_channel_list(char** list_str, uint16* channel_list, int channel_num);
#endif
#endif