397 lines
14 KiB
C
397 lines
14 KiB
C
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/*
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* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* Initial development of this code was funded by
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* Phytec Messtechnik GmbH, http://www.phytec.de
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __LINUX_MFD_MC13783_PRIV_H
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#define __LINUX_MFD_MC13783_PRIV_H
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#include <linux/platform_device.h>
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#include <linux/mfd/mc13783.h>
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#include <linux/workqueue.h>
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#include <linux/mutex.h>
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struct mc13783_irq {
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void (*handler)(int, void *);
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void *data;
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};
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#define MC13783_NUM_IRQ 2
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#define MC13783_IRQ_TS 0
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#define MC13783_IRQ_REGULATOR 1
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#define MC13783_ADC_MODE_TS 1
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#define MC13783_ADC_MODE_SINGLE_CHAN 2
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#define MC13783_ADC_MODE_MULT_CHAN 3
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struct mc13783 {
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int revision;
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struct device *dev;
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struct spi_device *spi_device;
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int (*read_dev)(void *data, char reg, int count, u32 *dst);
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int (*write_dev)(void *data, char reg, int count, const u32 *src);
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struct mutex io_lock;
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void *io_data;
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int irq;
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unsigned int flags;
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struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
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struct work_struct work;
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struct completion adc_done;
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unsigned int ts_active;
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struct mutex adc_conv_lock;
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struct mc13783_regulator_init_data *regulators;
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int num_regulators;
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};
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int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
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int mc13783_reg_write(struct mc13783 *, int, u32);
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int mc13783_set_bits(struct mc13783 *, int, u32, u32);
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int mc13783_free_irq(struct mc13783 *mc13783, int irq);
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int mc13783_register_irq(struct mc13783 *mc13783, int irq,
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void (*handler) (int, void *), void *data);
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#define MC13783_REG_INTERRUPT_STATUS_0 0
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#define MC13783_REG_INTERRUPT_MASK_0 1
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#define MC13783_REG_INTERRUPT_SENSE_0 2
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#define MC13783_REG_INTERRUPT_STATUS_1 3
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#define MC13783_REG_INTERRUPT_MASK_1 4
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#define MC13783_REG_INTERRUPT_SENSE_1 5
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#define MC13783_REG_POWER_UP_MODE_SENSE 6
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#define MC13783_REG_REVISION 7
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#define MC13783_REG_SEMAPHORE 8
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#define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
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#define MC13783_REG_ARBITRATION_SWITCHERS 10
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#define MC13783_REG_ARBITRATION_REGULATORS_0 11
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#define MC13783_REG_ARBITRATION_REGULATORS_1 12
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#define MC13783_REG_POWER_CONTROL_0 13
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#define MC13783_REG_POWER_CONTROL_1 14
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#define MC13783_REG_POWER_CONTROL_2 15
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#define MC13783_REG_REGEN_ASSIGNMENT 16
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#define MC13783_REG_CONTROL_SPARE 17
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#define MC13783_REG_MEMORY_A 18
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#define MC13783_REG_MEMORY_B 19
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#define MC13783_REG_RTC_TIME 20
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#define MC13783_REG_RTC_ALARM 21
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#define MC13783_REG_RTC_DAY 22
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#define MC13783_REG_RTC_DAY_ALARM 23
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#define MC13783_REG_SWITCHERS_0 24
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#define MC13783_REG_SWITCHERS_1 25
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#define MC13783_REG_SWITCHERS_2 26
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#define MC13783_REG_SWITCHERS_3 27
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#define MC13783_REG_SWITCHERS_4 28
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#define MC13783_REG_SWITCHERS_5 29
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#define MC13783_REG_REGULATOR_SETTING_0 30
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#define MC13783_REG_REGULATOR_SETTING_1 31
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#define MC13783_REG_REGULATOR_MODE_0 32
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#define MC13783_REG_REGULATOR_MODE_1 33
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#define MC13783_REG_POWER_MISCELLANEOUS 34
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#define MC13783_REG_POWER_SPARE 35
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#define MC13783_REG_AUDIO_RX_0 36
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#define MC13783_REG_AUDIO_RX_1 37
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#define MC13783_REG_AUDIO_TX 38
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#define MC13783_REG_AUDIO_SSI_NETWORK 39
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#define MC13783_REG_AUDIO_CODEC 40
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#define MC13783_REG_AUDIO_STEREO_DAC 41
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#define MC13783_REG_AUDIO_SPARE 42
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#define MC13783_REG_ADC_0 43
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#define MC13783_REG_ADC_1 44
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#define MC13783_REG_ADC_2 45
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#define MC13783_REG_ADC_3 46
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#define MC13783_REG_ADC_4 47
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#define MC13783_REG_CHARGER 48
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#define MC13783_REG_USB 49
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#define MC13783_REG_CHARGE_USB_SPARE 50
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#define MC13783_REG_LED_CONTROL_0 51
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#define MC13783_REG_LED_CONTROL_1 52
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#define MC13783_REG_LED_CONTROL_2 53
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#define MC13783_REG_LED_CONTROL_3 54
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#define MC13783_REG_LED_CONTROL_4 55
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#define MC13783_REG_LED_CONTROL_5 56
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#define MC13783_REG_SPARE 57
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#define MC13783_REG_TRIM_0 58
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#define MC13783_REG_TRIM_1 59
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#define MC13783_REG_TEST_0 60
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#define MC13783_REG_TEST_1 61
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#define MC13783_REG_TEST_2 62
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#define MC13783_REG_TEST_3 63
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#define MC13783_REG_NB 64
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/*
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* Interrupt Status
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*/
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#define MC13783_INT_STAT_ADCDONEI (1 << 0)
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#define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
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#define MC13783_INT_STAT_TSI (1 << 2)
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#define MC13783_INT_STAT_WHIGHI (1 << 3)
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#define MC13783_INT_STAT_WLOWI (1 << 4)
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#define MC13783_INT_STAT_CHGDETI (1 << 6)
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#define MC13783_INT_STAT_CHGOVI (1 << 7)
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#define MC13783_INT_STAT_CHGREVI (1 << 8)
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#define MC13783_INT_STAT_CHGSHORTI (1 << 9)
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#define MC13783_INT_STAT_CCCVI (1 << 10)
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#define MC13783_INT_STAT_CHGCURRI (1 << 11)
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#define MC13783_INT_STAT_BPONI (1 << 12)
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#define MC13783_INT_STAT_LOBATLI (1 << 13)
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#define MC13783_INT_STAT_LOBATHI (1 << 14)
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#define MC13783_INT_STAT_UDPI (1 << 15)
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#define MC13783_INT_STAT_USBI (1 << 16)
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#define MC13783_INT_STAT_IDI (1 << 19)
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#define MC13783_INT_STAT_Unused (1 << 20)
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#define MC13783_INT_STAT_SE1I (1 << 21)
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#define MC13783_INT_STAT_CKDETI (1 << 22)
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#define MC13783_INT_STAT_UDMI (1 << 23)
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/*
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* Interrupt Mask
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*/
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#define MC13783_INT_MASK_ADCDONEM (1 << 0)
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#define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
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#define MC13783_INT_MASK_TSM (1 << 2)
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#define MC13783_INT_MASK_WHIGHM (1 << 3)
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#define MC13783_INT_MASK_WLOWM (1 << 4)
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#define MC13783_INT_MASK_CHGDETM (1 << 6)
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#define MC13783_INT_MASK_CHGOVM (1 << 7)
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#define MC13783_INT_MASK_CHGREVM (1 << 8)
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#define MC13783_INT_MASK_CHGSHORTM (1 << 9)
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#define MC13783_INT_MASK_CCCVM (1 << 10)
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#define MC13783_INT_MASK_CHGCURRM (1 << 11)
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#define MC13783_INT_MASK_BPONM (1 << 12)
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#define MC13783_INT_MASK_LOBATLM (1 << 13)
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#define MC13783_INT_MASK_LOBATHM (1 << 14)
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#define MC13783_INT_MASK_UDPM (1 << 15)
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#define MC13783_INT_MASK_USBM (1 << 16)
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#define MC13783_INT_MASK_IDM (1 << 19)
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#define MC13783_INT_MASK_SE1M (1 << 21)
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#define MC13783_INT_MASK_CKDETM (1 << 22)
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/*
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* Reg Regulator Mode 0
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*/
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#define MC13783_REGCTRL_VAUDIO_EN (1 << 0)
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#define MC13783_REGCTRL_VAUDIO_STBY (1 << 1)
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#define MC13783_REGCTRL_VAUDIO_MODE (1 << 2)
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#define MC13783_REGCTRL_VIOHI_EN (1 << 3)
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#define MC13783_REGCTRL_VIOHI_STBY (1 << 4)
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#define MC13783_REGCTRL_VIOHI_MODE (1 << 5)
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#define MC13783_REGCTRL_VIOLO_EN (1 << 6)
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#define MC13783_REGCTRL_VIOLO_STBY (1 << 7)
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#define MC13783_REGCTRL_VIOLO_MODE (1 << 8)
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#define MC13783_REGCTRL_VDIG_EN (1 << 9)
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#define MC13783_REGCTRL_VDIG_STBY (1 << 10)
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#define MC13783_REGCTRL_VDIG_MODE (1 << 11)
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#define MC13783_REGCTRL_VGEN_EN (1 << 12)
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#define MC13783_REGCTRL_VGEN_STBY (1 << 13)
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#define MC13783_REGCTRL_VGEN_MODE (1 << 14)
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#define MC13783_REGCTRL_VRFDIG_EN (1 << 15)
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#define MC13783_REGCTRL_VRFDIG_STBY (1 << 16)
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#define MC13783_REGCTRL_VRFDIG_MODE (1 << 17)
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#define MC13783_REGCTRL_VRFREF_EN (1 << 18)
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#define MC13783_REGCTRL_VRFREF_STBY (1 << 19)
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#define MC13783_REGCTRL_VRFREF_MODE (1 << 20)
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#define MC13783_REGCTRL_VRFCP_EN (1 << 21)
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#define MC13783_REGCTRL_VRFCP_STBY (1 << 22)
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#define MC13783_REGCTRL_VRFCP_MODE (1 << 23)
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/*
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* Reg Regulator Mode 1
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*/
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#define MC13783_REGCTRL_VSIM_EN (1 << 0)
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#define MC13783_REGCTRL_VSIM_STBY (1 << 1)
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#define MC13783_REGCTRL_VSIM_MODE (1 << 2)
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#define MC13783_REGCTRL_VESIM_EN (1 << 3)
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#define MC13783_REGCTRL_VESIM_STBY (1 << 4)
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#define MC13783_REGCTRL_VESIM_MODE (1 << 5)
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#define MC13783_REGCTRL_VCAM_EN (1 << 6)
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#define MC13783_REGCTRL_VCAM_STBY (1 << 7)
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#define MC13783_REGCTRL_VCAM_MODE (1 << 8)
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#define MC13783_REGCTRL_VRFBG_EN (1 << 9)
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#define MC13783_REGCTRL_VRFBG_STBY (1 << 10)
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#define MC13783_REGCTRL_VVIB_EN (1 << 11)
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#define MC13783_REGCTRL_VRF1_EN (1 << 12)
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#define MC13783_REGCTRL_VRF1_STBY (1 << 13)
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#define MC13783_REGCTRL_VRF1_MODE (1 << 14)
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#define MC13783_REGCTRL_VRF2_EN (1 << 15)
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#define MC13783_REGCTRL_VRF2_STBY (1 << 16)
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#define MC13783_REGCTRL_VRF2_MODE (1 << 17)
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#define MC13783_REGCTRL_VMMC1_EN (1 << 18)
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#define MC13783_REGCTRL_VMMC1_STBY (1 << 19)
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#define MC13783_REGCTRL_VMMC1_MODE (1 << 20)
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#define MC13783_REGCTRL_VMMC2_EN (1 << 21)
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#define MC13783_REGCTRL_VMMC2_STBY (1 << 22)
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#define MC13783_REGCTRL_VMMC2_MODE (1 << 23)
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/*
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* Reg Regulator Misc.
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*/
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#define MC13783_REGCTRL_GPO1_EN (1 << 6)
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#define MC13783_REGCTRL_GPO2_EN (1 << 8)
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#define MC13783_REGCTRL_GPO3_EN (1 << 10)
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#define MC13783_REGCTRL_GPO4_EN (1 << 12)
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#define MC13783_REGCTRL_VIBPINCTRL (1 << 14)
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/*
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* Reg Switcher 4
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*/
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#define MC13783_SWCTRL_SW1A_MODE (1 << 0)
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#define MC13783_SWCTRL_SW1A_STBY_MODE (1 << 2)
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#define MC13783_SWCTRL_SW1A_DVS_SPEED (1 << 6)
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#define MC13783_SWCTRL_SW1A_PANIC_MODE (1 << 8)
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#define MC13783_SWCTRL_SW1A_SOFTSTART (1 << 9)
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#define MC13783_SWCTRL_SW1B_MODE (1 << 10)
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#define MC13783_SWCTRL_SW1B_STBY_MODE (1 << 12)
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#define MC13783_SWCTRL_SW1B_DVS_SPEED (1 << 14)
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#define MC13783_SWCTRL_SW1B_PANIC_MODE (1 << 16)
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#define MC13783_SWCTRL_SW1B_SOFTSTART (1 << 17)
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#define MC13783_SWCTRL_PLL_EN (1 << 18)
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#define MC13783_SWCTRL_PLL_FACTOR (1 << 19)
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/*
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* Reg Switcher 5
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*/
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#define MC13783_SWCTRL_SW2A_MODE (1 << 0)
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#define MC13783_SWCTRL_SW2A_STBY_MODE (1 << 2)
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#define MC13783_SWCTRL_SW2A_DVS_SPEED (1 << 6)
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#define MC13783_SWCTRL_SW2A_PANIC_MODE (1 << 8)
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#define MC13783_SWCTRL_SW2A_SOFTSTART (1 << 9)
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#define MC13783_SWCTRL_SW2B_MODE (1 << 10)
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#define MC13783_SWCTRL_SW2B_STBY_MODE (1 << 12)
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#define MC13783_SWCTRL_SW2B_DVS_SPEED (1 << 14)
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#define MC13783_SWCTRL_SW2B_PANIC_MODE (1 << 16)
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#define MC13783_SWCTRL_SW2B_SOFTSTART (1 << 17)
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#define MC13783_SWSET_SW3 (1 << 18)
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#define MC13783_SWCTRL_SW3_EN (1 << 20)
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#define MC13783_SWCTRL_SW3_STBY (1 << 21)
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#define MC13783_SWCTRL_SW3_MODE (1 << 22)
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/*
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* ADC/Touch
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*/
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#define MC13783_ADC0_LICELLCON (1 << 0)
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#define MC13783_ADC0_CHRGICON (1 << 1)
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#define MC13783_ADC0_BATICON (1 << 2)
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#define MC13783_ADC0_RTHEN (1 << 3)
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#define MC13783_ADC0_DTHEN (1 << 4)
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#define MC13783_ADC0_UIDEN (1 << 5)
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#define MC13783_ADC0_ADOUTEN (1 << 6)
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#define MC13783_ADC0_ADOUTPER (1 << 7)
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#define MC13783_ADC0_ADREFEN (1 << 10)
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#define MC13783_ADC0_ADREFMODE (1 << 11)
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#define MC13783_ADC0_TSMOD0 (1 << 12)
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#define MC13783_ADC0_TSMOD1 (1 << 13)
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#define MC13783_ADC0_TSMOD2 (1 << 14)
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#define MC13783_ADC0_CHRGRAWDIV (1 << 15)
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#define MC13783_ADC0_ADINC1 (1 << 16)
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#define MC13783_ADC0_ADINC2 (1 << 17)
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#define MC13783_ADC0_WCOMP (1 << 18)
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#define MC13783_ADC0_ADCBIS0 (1 << 23)
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#define MC13783_ADC1_ADEN (1 << 0)
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#define MC13783_ADC1_RAND (1 << 1)
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#define MC13783_ADC1_ADSEL (1 << 3)
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#define MC13783_ADC1_TRIGMASK (1 << 4)
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#define MC13783_ADC1_ADA10 (1 << 5)
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#define MC13783_ADC1_ADA11 (1 << 6)
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#define MC13783_ADC1_ADA12 (1 << 7)
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#define MC13783_ADC1_ADA20 (1 << 8)
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#define MC13783_ADC1_ADA21 (1 << 9)
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#define MC13783_ADC1_ADA22 (1 << 10)
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#define MC13783_ADC1_ATO0 (1 << 11)
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#define MC13783_ADC1_ATO1 (1 << 12)
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#define MC13783_ADC1_ATO2 (1 << 13)
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#define MC13783_ADC1_ATO3 (1 << 14)
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#define MC13783_ADC1_ATO4 (1 << 15)
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#define MC13783_ADC1_ATO5 (1 << 16)
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#define MC13783_ADC1_ATO6 (1 << 17)
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#define MC13783_ADC1_ATO7 (1 << 18)
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#define MC13783_ADC1_ATOX (1 << 19)
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#define MC13783_ADC1_ASC (1 << 20)
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#define MC13783_ADC1_ADTRIGIGN (1 << 21)
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#define MC13783_ADC1_ADONESHOT (1 << 22)
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#define MC13783_ADC1_ADCBIS1 (1 << 23)
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#define MC13783_ADC1_CHAN0_SHIFT 5
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#define MC13783_ADC1_CHAN1_SHIFT 8
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#define MC13783_ADC2_ADD10 (1 << 2)
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#define MC13783_ADC2_ADD11 (1 << 3)
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#define MC13783_ADC2_ADD12 (1 << 4)
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#define MC13783_ADC2_ADD13 (1 << 5)
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#define MC13783_ADC2_ADD14 (1 << 6)
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#define MC13783_ADC2_ADD15 (1 << 7)
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#define MC13783_ADC2_ADD16 (1 << 8)
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#define MC13783_ADC2_ADD17 (1 << 9)
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#define MC13783_ADC2_ADD18 (1 << 10)
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#define MC13783_ADC2_ADD19 (1 << 11)
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#define MC13783_ADC2_ADD20 (1 << 14)
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#define MC13783_ADC2_ADD21 (1 << 15)
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#define MC13783_ADC2_ADD22 (1 << 16)
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#define MC13783_ADC2_ADD23 (1 << 17)
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#define MC13783_ADC2_ADD24 (1 << 18)
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#define MC13783_ADC2_ADD25 (1 << 19)
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#define MC13783_ADC2_ADD26 (1 << 20)
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#define MC13783_ADC2_ADD27 (1 << 21)
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#define MC13783_ADC2_ADD28 (1 << 22)
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#define MC13783_ADC2_ADD29 (1 << 23)
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#define MC13783_ADC3_WHIGH0 (1 << 0)
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#define MC13783_ADC3_WHIGH1 (1 << 1)
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#define MC13783_ADC3_WHIGH2 (1 << 2)
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#define MC13783_ADC3_WHIGH3 (1 << 3)
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#define MC13783_ADC3_WHIGH4 (1 << 4)
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#define MC13783_ADC3_WHIGH5 (1 << 5)
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#define MC13783_ADC3_ICID0 (1 << 6)
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#define MC13783_ADC3_ICID1 (1 << 7)
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#define MC13783_ADC3_ICID2 (1 << 8)
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#define MC13783_ADC3_WLOW0 (1 << 9)
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#define MC13783_ADC3_WLOW1 (1 << 10)
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#define MC13783_ADC3_WLOW2 (1 << 11)
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#define MC13783_ADC3_WLOW3 (1 << 12)
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#define MC13783_ADC3_WLOW4 (1 << 13)
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#define MC13783_ADC3_WLOW5 (1 << 14)
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#define MC13783_ADC3_ADCBIS2 (1 << 23)
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#define MC13783_ADC4_ADDBIS10 (1 << 2)
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#define MC13783_ADC4_ADDBIS11 (1 << 3)
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#define MC13783_ADC4_ADDBIS12 (1 << 4)
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#define MC13783_ADC4_ADDBIS13 (1 << 5)
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#define MC13783_ADC4_ADDBIS14 (1 << 6)
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#define MC13783_ADC4_ADDBIS15 (1 << 7)
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#define MC13783_ADC4_ADDBIS16 (1 << 8)
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#define MC13783_ADC4_ADDBIS17 (1 << 9)
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#define MC13783_ADC4_ADDBIS18 (1 << 10)
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#define MC13783_ADC4_ADDBIS19 (1 << 11)
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#define MC13783_ADC4_ADDBIS20 (1 << 14)
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#define MC13783_ADC4_ADDBIS21 (1 << 15)
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#define MC13783_ADC4_ADDBIS22 (1 << 16)
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#define MC13783_ADC4_ADDBIS23 (1 << 17)
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#define MC13783_ADC4_ADDBIS24 (1 << 18)
|
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#define MC13783_ADC4_ADDBIS25 (1 << 19)
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#define MC13783_ADC4_ADDBIS26 (1 << 20)
|
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#define MC13783_ADC4_ADDBIS27 (1 << 21)
|
||
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#define MC13783_ADC4_ADDBIS28 (1 << 22)
|
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#define MC13783_ADC4_ADDBIS29 (1 << 23)
|
||
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#endif /* __LINUX_MFD_MC13783_PRIV_H */
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