67 lines
2.8 KiB
C
67 lines
2.8 KiB
C
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/*
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* Copyright 2005-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_BLACKFIN_H_
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#define _MACH_BLACKFIN_H_
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#define BF561_FAMILY
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#include "bf561.h"
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#include "defBF561.h"
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#include "anomaly.h"
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#if !defined(__ASSEMBLY__)
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#include "cdefBF561.h"
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#endif
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#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
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#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
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#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
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#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
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#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
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#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
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#define SIC_IWR0 SICA_IWR0
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#define SIC_IWR1 SICA_IWR1
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#define SIC_IAR0 SICA_IAR0
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#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
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#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
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#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
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#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
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#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
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#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
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#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
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#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
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#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
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#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
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#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
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#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
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#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
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#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
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#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
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#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
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#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
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#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
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#define BFIN_UART_NR_PORTS 1
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#define OFFSET_THR 0x00 /* Transmit Holding register */
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#define OFFSET_RBR 0x00 /* Receive Buffer register */
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#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
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#define OFFSET_IER 0x04 /* Interrupt Enable Register */
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#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
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#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
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#define OFFSET_LCR 0x0C /* Line Control Register */
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#define OFFSET_MCR 0x10 /* Modem Control Register */
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#define OFFSET_LSR 0x14 /* Line Status Register */
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#define OFFSET_MSR 0x18 /* Modem Status Register */
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#define OFFSET_SCR 0x1C /* SCR Scratch Register */
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#define OFFSET_GCTL 0x24 /* Global Control Register */
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#endif /* _MACH_BLACKFIN_H_ */
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