53 lines
1.8 KiB
C
53 lines
1.8 KiB
C
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/*
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
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#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
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/*
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* Memory-mapped I/O on MX21ADS base board
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*/
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#define MX21ADS_MMIO_BASE_ADDR 0xF5000000
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#define MX21ADS_MMIO_SIZE SZ_16M
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#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
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(MX21ADS_MMIO_BASE_ADDR + (offset))
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#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
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#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
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#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
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#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
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#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
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/* MX21ADS_IO_REG bit definitions */
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#define MX21ADS_IO_SD_WP 0x0001 /* read */
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#define MX21ADS_IO_TP6 0x0001 /* write */
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#define MX21ADS_IO_SW_SEL 0x0002 /* read */
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#define MX21ADS_IO_TP7 0x0002 /* write */
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#define MX21ADS_IO_RESET_E_UART 0x0004
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#define MX21ADS_IO_RESET_BASE 0x0008
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#define MX21ADS_IO_CSI_CTL2 0x0010
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#define MX21ADS_IO_CSI_CTL1 0x0020
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#define MX21ADS_IO_CSI_CTL0 0x0040
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#define MX21ADS_IO_UART1_EN 0x0080
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#define MX21ADS_IO_UART4_EN 0x0100
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#define MX21ADS_IO_LCDON 0x0200
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#define MX21ADS_IO_IRDA_EN 0x0400
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#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
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#define MX21ADS_IO_IRDA_MD0_B 0x1000
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#define MX21ADS_IO_IRDA_MD1 0x2000
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#define MX21ADS_IO_LED4_ON 0x4000
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#define MX21ADS_IO_LED3_ON 0x8000
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#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
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