125 lines
3.4 KiB
C
125 lines
3.4 KiB
C
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#ifndef _ASM_X86_PGTABLE_3LEVEL_H
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#define _ASM_X86_PGTABLE_3LEVEL_H
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/*
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* Intel Physical Address Extension (PAE) Mode - three-level page
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* tables on PPro+ CPUs.
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*
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* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
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*/
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p(%08lx%08lx).\n", \
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__FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %p(%016Lx).\n", \
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__FILE__, __LINE__, &(e), pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %p(%016Lx).\n", \
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__FILE__, __LINE__, &(e), pgd_val(e))
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/* Rules for using set_pte: the pte being assigned *must* be
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* either not present or in a state where the hardware will
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* not attempt to update the pte. In places where this is
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* not possible, use pte_get_and_clear to obtain the old pte
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* value and then use set_pte to update it. -ben
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*/
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static inline void native_set_pte(pte_t *ptep, pte_t pte)
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{
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
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}
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
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}
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
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}
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/*
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* For PTEs and PDEs, we must clear the P-bit first when clearing a page table
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* entry, so clear the bottom half first and enforce ordering with a compiler
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* barrier.
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*/
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static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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ptep->pte_low = 0;
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smp_wmb();
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ptep->pte_high = 0;
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}
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static inline void native_pmd_clear(pmd_t *pmd)
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{
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u32 *tmp = (u32 *)pmd;
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*tmp = 0;
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smp_wmb();
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*(tmp + 1) = 0;
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}
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static inline void pud_clear(pud_t *pudp)
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{
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unsigned long pgd;
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set_pud(pudp, __pud(0));
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/*
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* According to Intel App note "TLBs, Paging-Structure Caches,
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* and Their Invalidation", April 2007, document 317080-001,
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* section 8.1: in PAE mode we explicitly have to flush the
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* TLB via cr3 if the top-level pgd is changed...
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*
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* Make sure the pud entry we're updating is within the
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* current pgd to avoid unnecessary TLB flushes.
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*/
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pgd = read_cr3();
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if (__pa(pudp) >= pgd && __pa(pudp) <
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(pgd + sizeof(pgd_t)*PTRS_PER_PGD))
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write_cr3(pgd);
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}
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#ifdef CONFIG_SMP
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static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
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{
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pte_t res;
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/* xchg acts as a barrier before the setting of the high bits */
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res.pte_low = xchg(&ptep->pte_low, 0);
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res.pte_high = ptep->pte_high;
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ptep->pte_high = 0;
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return res;
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}
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#else
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#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
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#endif
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/*
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* Bits 0, 6 and 7 are taken in the low part of the pte,
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* put the 32 bits of offset into the high part.
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*/
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#define pte_to_pgoff(pte) ((pte).pte_high)
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#define pgoff_to_pte(off) \
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((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
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#define PTE_FILE_MAX_BITS 32
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/* Encode and de-code a swap entry */
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
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#define __swp_type(x) (((x).val) & 0x1f)
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#define __swp_offset(x) ((x).val >> 5)
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#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
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#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } })
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#endif /* _ASM_X86_PGTABLE_3LEVEL_H */
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