178 lines
4.2 KiB
C
178 lines
4.2 KiB
C
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/*
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* linux/arch/arm/kernel/smp_twd.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/jiffies.h>
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#include <linux/clockchips.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/gic.h>
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#define TWD_TIMER_LOAD 0x00
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#define TWD_TIMER_COUNTER 0x04
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#define TWD_TIMER_CONTROL 0x08
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#define TWD_TIMER_INTSTAT 0x0C
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#define TWD_WDOG_LOAD 0x20
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#define TWD_WDOG_COUNTER 0x24
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#define TWD_WDOG_CONTROL 0x28
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#define TWD_WDOG_INTSTAT 0x2C
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#define TWD_WDOG_RESETSTAT 0x30
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#define TWD_WDOG_DISABLE 0x34
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#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
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#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
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#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
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#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
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/* set up by the platform code */
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void __iomem *twd_base;
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static unsigned long twd_timer_rate;
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static void twd_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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unsigned long ctrl;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* timer load already set up */
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ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
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| TWD_TIMER_CONTROL_PERIODIC;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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ctrl = 0;
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}
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__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
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}
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static int twd_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
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ctrl |= TWD_TIMER_CONTROL_ENABLE;
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__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
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__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
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return 0;
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}
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/*
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* local_timer_ack: checks for a local timer interrupt.
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*
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* If a local timer interrupt has occurred, acknowledge and return 1.
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* Otherwise, return 0.
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*/
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int twd_timer_ack(void)
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{
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if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
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__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
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return 1;
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}
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return 0;
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}
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static void __cpuinit twd_calibrate_rate(void)
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{
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unsigned long load, count;
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u64 waitjiffies;
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/*
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* If this is the first time round, we need to work out how fast
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* the timer ticks
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*/
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if (twd_timer_rate == 0) {
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printk(KERN_INFO "Calibrating local timer... ");
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/* Wait for a tick to start */
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waitjiffies = get_jiffies_64() + 1;
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while (get_jiffies_64() < waitjiffies)
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udelay(10);
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/* OK, now the tick has started, let's get the timer going */
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waitjiffies += 5;
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/* enable, no interrupt or reload */
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__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
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/* maximum value */
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__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
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while (get_jiffies_64() < waitjiffies)
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udelay(10);
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count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
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twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
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printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
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(twd_timer_rate / 100000) % 100);
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}
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load = twd_timer_rate / HZ;
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__raw_writel(load, twd_base + TWD_TIMER_LOAD);
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}
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/*
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* Setup the local clock events for a CPU.
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*/
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void __cpuinit twd_timer_setup(struct clock_event_device *clk)
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{
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unsigned long flags;
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twd_calibrate_rate();
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clk->name = "local_timer";
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clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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clk->rating = 350;
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clk->set_mode = twd_set_mode;
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clk->set_next_event = twd_set_next_event;
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clk->shift = 20;
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clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift);
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clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
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clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
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/* Make sure our local interrupt controller has this enabled */
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local_irq_save(flags);
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get_irq_chip(clk->irq)->unmask(clk->irq);
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local_irq_restore(flags);
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clockevents_register_device(clk);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* take a local timer down
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*/
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void twd_timer_stop(void)
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{
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__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
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}
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#endif
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