90 lines
3.5 KiB
C
90 lines
3.5 KiB
C
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/*
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* stmp37xx: LCDIF register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
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#define REGS_LCDIF_PHYS 0x80030000
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#define REGS_LCDIF_SIZE 0x2000
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#define HW_LCDIF_CTRL 0x0
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#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
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#define BP_LCDIF_CTRL_COUNT 0
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#define BM_LCDIF_CTRL_RUN 0x00010000
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#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
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#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
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#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
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#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
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#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
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#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
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#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
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#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
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#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
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#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
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#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
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#define BM_LCDIF_CTRL_CLKGATE 0x40000000
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#define BM_LCDIF_CTRL_SFTRST 0x80000000
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#define HW_LCDIF_CTRL1 0x10
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#define BM_LCDIF_CTRL1_RESET 0x00000001
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#define BP_LCDIF_CTRL1_RESET 0
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#define BM_LCDIF_CTRL1_MODE86 0x00000002
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#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
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#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
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#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
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#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
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#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
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#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
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#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
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#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
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#define HW_LCDIF_TIMING 0x20
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#define HW_LCDIF_VDCTRL0 0x30
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#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
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#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
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#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
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#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
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#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
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#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
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#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
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#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
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#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
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#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
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#define HW_LCDIF_VDCTRL1 0x40
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#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
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#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
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#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
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#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
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#define HW_LCDIF_VDCTRL2 0x50
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#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
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#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
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#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
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#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
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#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
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#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
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#define HW_LCDIF_VDCTRL3 0x60
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#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
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#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
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#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
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#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
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#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
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