370 lines
11 KiB
C
370 lines
11 KiB
C
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/* arch/arm/mach-msm/qdsp5/adsp.h
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*
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* Copyright (c) 2008 QUALCOMM Incorporated
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* Copyright (C) 2008 Google, Inc.
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* Author: Iliyan Malchev <ibm@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _ARCH_ARM_MACH_MSM_ADSP_H
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#define _ARCH_ARM_MACH_MSM_ADSP_H
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#include <linux/types.h>
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#include <linux/msm_adsp.h>
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#include <mach/msm_rpcrouter.h>
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#include <mach/msm_adsp.h>
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int adsp_pmem_fixup(struct msm_adsp_module *module, void **addr,
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unsigned long len);
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int adsp_pmem_fixup_kvaddr(struct msm_adsp_module *module, void **addr,
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unsigned long *kvaddr, unsigned long len);
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int adsp_pmem_paddr_fixup(struct msm_adsp_module *module, void **addr);
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int adsp_vfe_verify_cmd(struct msm_adsp_module *module,
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unsigned int queue_id, void *cmd_data,
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size_t cmd_size);
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int adsp_jpeg_verify_cmd(struct msm_adsp_module *module,
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unsigned int queue_id, void *cmd_data,
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size_t cmd_size);
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int adsp_lpm_verify_cmd(struct msm_adsp_module *module,
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unsigned int queue_id, void *cmd_data,
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size_t cmd_size);
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int adsp_video_verify_cmd(struct msm_adsp_module *module,
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unsigned int queue_id, void *cmd_data,
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size_t cmd_size);
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int adsp_videoenc_verify_cmd(struct msm_adsp_module *module,
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unsigned int queue_id, void *cmd_data,
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size_t cmd_size);
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struct adsp_event;
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int adsp_vfe_patch_event(struct msm_adsp_module *module,
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struct adsp_event *event);
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int adsp_jpeg_patch_event(struct msm_adsp_module *module,
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struct adsp_event *event);
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struct adsp_module_info {
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const char *name;
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const char *pdev_name;
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uint32_t id;
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const char *clk_name;
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unsigned long clk_rate;
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int (*verify_cmd) (struct msm_adsp_module*, unsigned int, void *,
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size_t);
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int (*patch_event) (struct msm_adsp_module*, struct adsp_event *);
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};
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#define ADSP_EVENT_MAX_SIZE 496
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#define EVENT_LEN 12
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#define EVENT_MSG_ID ((uint16_t)~0)
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struct adsp_event {
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struct list_head list;
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uint32_t size; /* always in bytes */
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uint16_t msg_id;
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uint16_t type; /* 0 for msgs (from aDSP), -1 for events (from ARM9) */
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int is16; /* always 0 (msg is 32-bit) when the event type is 1(ARM9) */
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union {
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uint16_t msg16[ADSP_EVENT_MAX_SIZE / 2];
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uint32_t msg32[ADSP_EVENT_MAX_SIZE / 4];
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} data;
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};
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struct adsp_info {
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uint32_t send_irq;
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uint32_t read_ctrl;
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uint32_t write_ctrl;
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uint32_t max_msg16_size;
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uint32_t max_msg32_size;
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uint32_t max_task_id;
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uint32_t max_module_id;
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uint32_t max_queue_id;
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uint32_t max_image_id;
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/* for each image id, a map of queue id to offset */
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uint32_t **queue_offset;
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/* for each image id, a map of task id to module id */
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uint32_t **task_to_module;
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/* for each module id, map of module id to module */
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struct msm_adsp_module **id_to_module;
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uint32_t module_count;
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struct adsp_module_info *module;
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/* stats */
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uint32_t events_received;
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uint32_t event_backlog_max;
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#if CONFIG_MSM_AMSS_VERSION >= 6350
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/* rpc_client for init_info */
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struct msm_rpc_endpoint *init_info_rpc_client;
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struct adsp_rtos_mp_mtoa_init_info_type *init_info_ptr;
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wait_queue_head_t init_info_wait;
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unsigned init_info_state;
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#endif
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};
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#define RPC_ADSP_RTOS_ATOM_PROG 0x3000000a
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#define RPC_ADSP_RTOS_MTOA_PROG 0x3000000b
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#define RPC_ADSP_RTOS_ATOM_NULL_PROC 0
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#define RPC_ADSP_RTOS_MTOA_NULL_PROC 0
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#define RPC_ADSP_RTOS_APP_TO_MODEM_PROC 2
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#define RPC_ADSP_RTOS_MODEM_TO_APP_PROC 2
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#if CONFIG_MSM_AMSS_VERSION >= 6350
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#define RPC_ADSP_RTOS_ATOM_VERS MSM_RPC_VERS(1,0)
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#define RPC_ADSP_RTOS_MTOA_VERS MSM_RPC_VERS(2,1) /* must be actual vers */
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#define MSM_ADSP_DRIVER_NAME "rs3000000a:00010000"
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#elif (CONFIG_MSM_AMSS_VERSION == 6220) || (CONFIG_MSM_AMSS_VERSION == 6225)
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#define RPC_ADSP_RTOS_ATOM_VERS MSM_RPC_VERS(0x71d1094b, 0)
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#define RPC_ADSP_RTOS_MTOA_VERS MSM_RPC_VERS(0xee3a9966, 0)
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#define MSM_ADSP_DRIVER_NAME "rs3000000a:71d1094b"
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#elif CONFIG_MSM_AMSS_VERSION == 6210
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#define RPC_ADSP_RTOS_ATOM_VERS MSM_RPC_VERS(0x20f17fd3, 0)
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#define RPC_ADSP_RTOS_MTOA_VERS MSM_RPC_VERS(0x75babbd6, 0)
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#define MSM_ADSP_DRIVER_NAME "rs3000000a:20f17fd3"
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#else
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#error "Unknown AMSS version"
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#endif
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enum rpc_adsp_rtos_proc_type {
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RPC_ADSP_RTOS_PROC_NONE = 0,
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RPC_ADSP_RTOS_PROC_MODEM = 1,
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RPC_ADSP_RTOS_PROC_APPS = 2,
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};
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enum {
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RPC_ADSP_RTOS_CMD_REGISTER_APP,
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RPC_ADSP_RTOS_CMD_ENABLE,
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RPC_ADSP_RTOS_CMD_DISABLE,
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RPC_ADSP_RTOS_CMD_KERNEL_COMMAND,
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RPC_ADSP_RTOS_CMD_16_COMMAND,
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RPC_ADSP_RTOS_CMD_32_COMMAND,
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RPC_ADSP_RTOS_CMD_DISABLE_EVENT_RSP,
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RPC_ADSP_RTOS_CMD_REMOTE_EVENT,
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RPC_ADSP_RTOS_CMD_SET_STATE,
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#if CONFIG_MSM_AMSS_VERSION >= 6350
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RPC_ADSP_RTOS_CMD_REMOTE_INIT_INFO_EVENT,
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RPC_ADSP_RTOS_CMD_GET_INIT_INFO,
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#endif
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};
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enum rpc_adsp_rtos_mod_status_type {
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RPC_ADSP_RTOS_MOD_READY,
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RPC_ADSP_RTOS_MOD_DISABLE,
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RPC_ADSP_RTOS_SERVICE_RESET,
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RPC_ADSP_RTOS_CMD_FAIL,
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RPC_ADSP_RTOS_CMD_SUCCESS,
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#if CONFIG_MSM_AMSS_VERSION >= 6350
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RPC_ADSP_RTOS_INIT_INFO,
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RPC_ADSP_RTOS_DISABLE_FAIL,
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#endif
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};
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struct rpc_adsp_rtos_app_to_modem_args_t {
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struct rpc_request_hdr hdr;
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uint32_t gotit; /* if 1, the next elements are present */
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uint32_t cmd; /* e.g., RPC_ADSP_RTOS_CMD_REGISTER_APP */
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uint32_t proc_id; /* e.g., RPC_ADSP_RTOS_PROC_APPS */
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uint32_t module; /* e.g., QDSP_MODULE_AUDPPTASK */
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};
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#if CONFIG_MSM_AMSS_VERSION >= 6350
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enum qdsp_image_type {
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QDSP_IMAGE_COMBO,
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QDSP_IMAGE_GAUDIO,
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QDSP_IMAGE_QTV_LP,
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QDSP_IMAGE_MAX,
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/* DO NOT USE: Force this enum to be a 32bit type to improve speed */
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QDSP_IMAGE_32BIT_DUMMY = 0x10000
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};
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struct adsp_rtos_mp_mtoa_header_type {
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enum rpc_adsp_rtos_mod_status_type event;
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enum rpc_adsp_rtos_proc_type proc_id;
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};
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/* ADSP RTOS MP Communications - Modem to APP's Event Info*/
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struct adsp_rtos_mp_mtoa_type {
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uint32_t module;
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uint32_t image;
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uint32_t apps_okts;
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};
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/* ADSP RTOS MP Communications - Modem to APP's Init Info */
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#define IMG_MAX 8
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#define ENTRIES_MAX 64
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struct queue_to_offset_type {
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uint32_t queue;
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uint32_t offset;
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};
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struct adsp_rtos_mp_mtoa_init_info_type {
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uint32_t image_count;
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uint32_t num_queue_offsets;
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struct queue_to_offset_type queue_offsets_tbl[IMG_MAX][ENTRIES_MAX];
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uint32_t num_task_module_entries;
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uint32_t task_to_module_tbl[IMG_MAX][ENTRIES_MAX];
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uint32_t module_table_size;
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uint32_t module_entries[ENTRIES_MAX];
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/*
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* queue_offsets[] is to store only queue_offsets
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*/
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uint32_t queue_offsets[IMG_MAX][ENTRIES_MAX];
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};
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struct adsp_rtos_mp_mtoa_s_type {
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struct adsp_rtos_mp_mtoa_header_type mp_mtoa_header;
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uint32_t desc_field;
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union {
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struct adsp_rtos_mp_mtoa_init_info_type mp_mtoa_init_packet;
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struct adsp_rtos_mp_mtoa_type mp_mtoa_packet;
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} adsp_rtos_mp_mtoa_data;
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};
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struct rpc_adsp_rtos_modem_to_app_args_t {
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struct rpc_request_hdr hdr;
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uint32_t gotit; /* if 1, the next elements are present */
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struct adsp_rtos_mp_mtoa_s_type mtoa_pkt;
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};
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#else
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struct rpc_adsp_rtos_modem_to_app_args_t {
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struct rpc_request_hdr hdr;
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uint32_t gotit; /* if 1, the next elements are present */
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uint32_t event; /* e.g., RPC_ADSP_RTOS_CMD_REGISTER_APP */
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uint32_t proc_id; /* e.g., RPC_ADSP_RTOS_PROC_APPS */
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uint32_t module; /* e.g., QDSP_MODULE_AUDPPTASK */
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uint32_t image; /* RPC_QDSP_IMAGE_GAUDIO */
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};
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#endif /* CONFIG_MSM_AMSS_VERSION >= 6350 */
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#define ADSP_STATE_DISABLED 0
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#define ADSP_STATE_ENABLING 1
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#define ADSP_STATE_ENABLED 2
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#define ADSP_STATE_DISABLING 3
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#if CONFIG_MSM_AMSS_VERSION >= 6350
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#define ADSP_STATE_INIT_INFO 4
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#endif
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struct msm_adsp_module {
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struct mutex lock;
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const char *name;
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unsigned id;
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struct adsp_info *info;
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struct msm_rpc_endpoint *rpc_client;
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struct msm_adsp_ops *ops;
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void *driver_data;
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/* statistics */
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unsigned num_commands;
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unsigned num_events;
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wait_queue_head_t state_wait;
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unsigned state;
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struct platform_device pdev;
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struct clk *clk;
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int open_count;
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struct mutex pmem_regions_lock;
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struct hlist_head pmem_regions;
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int (*verify_cmd) (struct msm_adsp_module*, unsigned int, void *,
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size_t);
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int (*patch_event) (struct msm_adsp_module*, struct adsp_event *);
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};
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extern void msm_adsp_publish_cdevs(struct msm_adsp_module *, unsigned);
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extern int adsp_init_info(struct adsp_info *info);
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/* Value to indicate that a queue is not defined for a particular image */
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#if CONFIG_MSM_AMSS_VERSION >= 6350
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#define QDSP_RTOS_NO_QUEUE 0xfffffffe
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#else
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#define QDSP_RTOS_NO_QUEUE 0xffffffff
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#endif
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/*
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* Constants used to communicate with the ADSP RTOS
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*/
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#define ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_M 0x80000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_NAVAIL_V 0x80000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_AVAIL_V 0x00000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_CMD_M 0x70000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_CMD_WRITE_REQ_V 0x00000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_CMD_WRITE_DONE_V 0x10000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_CMD_NO_CMD_V 0x70000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_STATUS_M 0x0E000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_NO_ERR_V 0x00000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_NO_FREE_BUF_V 0x02000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_KERNEL_FLG_M 0x01000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_HTOD_MSG_WRITE_V 0x00000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_HTOD_CMD_V 0x01000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M 0x00FFFFFFU
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#define ADSP_RTOS_WRITE_CTRL_WORD_HTOD_CMD_ID_M 0x00FFFFFFU
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/* Combination of MUTEX and CMD bits to check if the DSP is busy */
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#define ADSP_RTOS_WRITE_CTRL_WORD_READY_M 0xF0000000U
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#define ADSP_RTOS_WRITE_CTRL_WORD_READY_V 0x70000000U
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/* RTOS to Host processor command mask values */
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#define ADSP_RTOS_READ_CTRL_WORD_FLAG_M 0x80000000U
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#define ADSP_RTOS_READ_CTRL_WORD_FLAG_UP_WAIT_V 0x00000000U
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#define ADSP_RTOS_READ_CTRL_WORD_FLAG_UP_CONT_V 0x80000000U
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#define ADSP_RTOS_READ_CTRL_WORD_CMD_M 0x60000000U
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#define ADSP_RTOS_READ_CTRL_WORD_READ_DONE_V 0x00000000U
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#define ADSP_RTOS_READ_CTRL_WORD_READ_REQ_V 0x20000000U
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#define ADSP_RTOS_READ_CTRL_WORD_NO_CMD_V 0x60000000U
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/* Combination of FLAG and COMMAND bits to check if MSG ready */
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#define ADSP_RTOS_READ_CTRL_WORD_READY_M 0xE0000000U
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#define ADSP_RTOS_READ_CTRL_WORD_READY_V 0xA0000000U
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#define ADSP_RTOS_READ_CTRL_WORD_CONT_V 0xC0000000U
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#define ADSP_RTOS_READ_CTRL_WORD_DONE_V 0xE0000000U
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#define ADSP_RTOS_READ_CTRL_WORD_STATUS_M 0x18000000U
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#define ADSP_RTOS_READ_CTRL_WORD_NO_ERR_V 0x00000000U
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#define ADSP_RTOS_READ_CTRL_WORD_IN_PROG_M 0x04000000U
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#define ADSP_RTOS_READ_CTRL_WORD_NO_READ_IN_PROG_V 0x00000000U
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#define ADSP_RTOS_READ_CTRL_WORD_READ_IN_PROG_V 0x04000000U
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#define ADSP_RTOS_READ_CTRL_WORD_CMD_TYPE_M 0x03000000U
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#define ADSP_RTOS_READ_CTRL_WORD_CMD_TASK_TO_H_V 0x00000000U
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#define ADSP_RTOS_READ_CTRL_WORD_CMD_KRNL_TO_H_V 0x01000000U
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#define ADSP_RTOS_READ_CTRL_WORD_CMD_H_TO_KRNL_CFM_V 0x02000000U
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#define ADSP_RTOS_READ_CTRL_WORD_DSP_ADDR_M 0x00FFFFFFU
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#define ADSP_RTOS_READ_CTRL_WORD_MSG_ID_M 0x000000FFU
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#define ADSP_RTOS_READ_CTRL_WORD_TASK_ID_M 0x0000FF00U
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/* Base address of DSP and DSP hardware registers */
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#define QDSP_RAMC_OFFSET 0x400000
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#endif /* _ARCH_ARM_MACH_MSM_ADSP_H */
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