348 lines
9.3 KiB
C
348 lines
9.3 KiB
C
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/*
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* (C) Copyright Advanced Micro Devices, Inc. 2002, 2007
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* Copyright (c) 2008-2009 QUALCOMM USA, INC.
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*
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* All source code in this file is licensed under the following license
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can find it at http://www.fsf.org
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*/
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#ifndef _MSM_KGSL_H
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#define _MSM_KGSL_H
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/*context flags */
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#define KGSL_CONTEXT_SAVE_GMEM 1
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#define KGSL_CONTEXT_NO_GMEM_ALLOC 2
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/* generic flag values */
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#define KGSL_FLAGS_NORMALMODE 0x00000000
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#define KGSL_FLAGS_SAFEMODE 0x00000001
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#define KGSL_FLAGS_INITIALIZED0 0x00000002
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#define KGSL_FLAGS_INITIALIZED 0x00000004
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#define KGSL_FLAGS_STARTED 0x00000008
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#define KGSL_FLAGS_ACTIVE 0x00000010
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#define KGSL_FLAGS_RESERVED0 0x00000020
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#define KGSL_FLAGS_RESERVED1 0x00000040
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#define KGSL_FLAGS_RESERVED2 0x00000080
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/* device id */
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enum kgsl_deviceid {
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KGSL_DEVICE_ANY = 0x00000000,
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KGSL_DEVICE_YAMATO = 0x00000001,
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KGSL_DEVICE_G12 = 0x00000002,
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KGSL_DEVICE_MAX = 0x00000002
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};
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struct kgsl_devinfo {
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unsigned int device_id;
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/* chip revision id
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* coreid:8 majorrev:8 minorrev:8 patch:8
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*/
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unsigned int chip_id;
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unsigned int mmu_enabled;
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unsigned int gmem_gpubaseaddr;
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/* if gmem_hostbaseaddr is NULL, we would know its not mapped into
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* mmio space */
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unsigned int gmem_hostbaseaddr;
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unsigned int gmem_sizebytes;
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};
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/* this structure defines the region of memory that can be mmap()ed from this
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driver. The timestamp fields are volatile because they are written by the
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GPU
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*/
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struct kgsl_devmemstore {
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volatile unsigned int soptimestamp;
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unsigned int sbz;
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volatile unsigned int eoptimestamp;
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unsigned int sbz2;
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volatile unsigned int ts_cmp_enable;
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unsigned int sbz3;
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volatile unsigned int ref_wait_ts;
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unsigned int sbz4;
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};
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#define KGSL_DEVICE_MEMSTORE_OFFSET(field) \
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offsetof(struct kgsl_devmemstore, field)
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/* timestamp id*/
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enum kgsl_timestamp_type {
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KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */
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KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/
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KGSL_TIMESTAMP_MAX = 0x00000002,
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};
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/* property types - used with kgsl_device_getproperty */
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enum kgsl_property_type {
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KGSL_PROP_DEVICE_INFO = 0x00000001,
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KGSL_PROP_DEVICE_SHADOW = 0x00000002,
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KGSL_PROP_DEVICE_POWER = 0x00000003,
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KGSL_PROP_SHMEM = 0x00000004,
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KGSL_PROP_SHMEM_APERTURES = 0x00000005,
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KGSL_PROP_MMU_ENABLE = 0x00000006,
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KGSL_PROP_INTERRUPT_WAITS = 0x00000007,
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};
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struct kgsl_shadowprop {
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unsigned int gpuaddr;
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unsigned int size;
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unsigned int flags; /* contains KGSL_FLAGS_ values */
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};
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#ifdef CONFIG_ARCH_MSM7X30
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struct kgsl_platform_data {
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unsigned int high_axi_2d;
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unsigned int high_axi_3d;
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unsigned int max_grp2d_freq;
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unsigned int min_grp2d_freq;
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int (*set_grp2d_async)(void);
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unsigned int max_grp3d_freq;
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unsigned int min_grp3d_freq;
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int (*set_grp3d_async)(void);
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};
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#endif
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/* ioctls */
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#define KGSL_IOC_TYPE 0x09
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/* get misc info about the GPU
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type should be a value from enum kgsl_property_type
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value points to a structure that varies based on type
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sizebytes is sizeof() that structure
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for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo
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this structure contaings hardware versioning info.
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for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop
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this is used to find mmap() offset and sizes for mapping
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struct kgsl_memstore into userspace.
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*/
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struct kgsl_device_getproperty {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int type;
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void *value;
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unsigned int sizebytes;
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};
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#define IOCTL_KGSL_DEVICE_GETPROPERTY \
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_IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty)
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/* read a GPU register.
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offsetwords it the 32 bit word offset from the beginning of the
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GPU register space.
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*/
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struct kgsl_device_regread {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int offsetwords;
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unsigned int value; /* output param */
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};
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#define IOCTL_KGSL_DEVICE_REGREAD \
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_IOWR(KGSL_IOC_TYPE, 0x3, struct kgsl_device_regread)
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/* block until the GPU has executed past a given timestamp
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* timeout is in milliseconds.
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*/
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struct kgsl_device_waittimestamp {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int timestamp;
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unsigned int timeout;
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};
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#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \
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_IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp)
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/* issue indirect commands to the GPU.
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* drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE
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* ibaddr and sizedwords must specify a subset of a buffer created
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* with IOCTL_KGSL_SHAREDMEM_FROM_PMEM
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* flags may be a mask of KGSL_CONTEXT_ values
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* timestamp is a returned counter value which can be passed to
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* other ioctls to determine when the commands have been executed by
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* the GPU.
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*/
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struct kgsl_ringbuffer_issueibcmds {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int drawctxt_id;
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unsigned int ibaddr;
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unsigned int sizedwords;
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unsigned int timestamp; /*output param */
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unsigned int flags;
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};
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#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \
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_IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds)
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/* read the most recently executed timestamp value
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* type should be a value from enum kgsl_timestamp_type
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*/
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struct kgsl_cmdstream_readtimestamp {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int type;
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unsigned int timestamp; /*output param */
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};
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#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \
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_IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
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/* free memory when the GPU reaches a given timestamp.
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* gpuaddr specify a memory region created by a
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* IOCTL_KGSL_SHAREDMEM_FROM_PMEM call
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* type should be a value from enum kgsl_timestamp_type
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*/
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struct kgsl_cmdstream_freememontimestamp {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int gpuaddr;
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unsigned int type;
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unsigned int timestamp;
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};
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#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \
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_IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
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/* create a draw context, which is used to preserve GPU state.
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* The flags field may contain a mask KGSL_CONTEXT_* values
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*/
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struct kgsl_drawctxt_create {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int flags;
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unsigned int drawctxt_id; /*output param */
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};
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#define IOCTL_KGSL_DRAWCTXT_CREATE \
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_IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create)
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/* destroy a draw context */
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struct kgsl_drawctxt_destroy {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int drawctxt_id;
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};
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#define IOCTL_KGSL_DRAWCTXT_DESTROY \
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_IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy)
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/* add a block of pmem or fb into the GPU address space */
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struct kgsl_sharedmem_from_pmem {
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int pmem_fd;
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unsigned int gpuaddr; /*output param */
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unsigned int len;
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unsigned int offset;
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};
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#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \
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_IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem)
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/* remove memory from the GPU's address space */
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struct kgsl_sharedmem_free {
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unsigned int gpuaddr;
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};
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#define IOCTL_KGSL_SHAREDMEM_FREE \
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_IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free)
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struct kgsl_gmem_desc {
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unsigned int x;
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unsigned int y;
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unsigned int width;
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unsigned int height;
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unsigned int pitch;
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};
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struct kgsl_buffer_desc {
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void *hostptr;
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unsigned int gpuaddr;
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int size;
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unsigned int format;
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unsigned int pitch;
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unsigned int enabled;
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};
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struct kgsl_bind_gmem_shadow {
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unsigned int drawctxt_id;
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struct kgsl_gmem_desc gmem_desc;
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unsigned int shadow_x;
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unsigned int shadow_y;
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struct kgsl_buffer_desc shadow_buffer;
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unsigned int buffer_id;
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};
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#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \
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_IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow)
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/* add a block of memory into the GPU address space */
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struct kgsl_sharedmem_from_vmalloc {
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unsigned int gpuaddr; /*output param */
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unsigned int hostptr;
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/* If set from user space then will attempt to
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* allocate even if low watermark is crossed */
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int force_no_low_watermark;
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};
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#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \
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_IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc)
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#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \
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_IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free)
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struct kgsl_drawctxt_set_bin_base_offset {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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unsigned int drawctxt_id;
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unsigned int offset;
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};
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#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \
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_IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset)
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enum kgsl_cmdwindow_type {
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KGSL_CMDWINDOW_MIN = 0x00000000,
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KGSL_CMDWINDOW_2D = 0x00000000,
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KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */
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KGSL_CMDWINDOW_MMU = 0x00000002,
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KGSL_CMDWINDOW_ARBITER = 0x000000FF,
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KGSL_CMDWINDOW_MAX = 0x000000FF,
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};
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/* write to the command window */
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struct kgsl_cmdwindow_write {
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#ifdef CONFIG_ARCH_MSM7X30
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unsigned int device_id;
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#endif
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enum kgsl_cmdwindow_type target;
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unsigned int addr;
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unsigned int data;
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};
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#define IOCTL_KGSL_CMDWINDOW_WRITE \
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_IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write)
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#endif /* _MSM_KGSL_H */
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