102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
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/*
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* arch/arm/mach-l7200/include/mach/serial_l7200.h
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*
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* Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
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*
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* Changelog:
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* 05-09-2000 SJH Created
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*/
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#ifndef __ASM_ARCH_SERIAL_L7200_H
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#define __ASM_ARCH_SERIAL_L7200_H
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#include <mach/memory.h>
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/*
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* This assumes you have a 3.6864 MHz clock for your UART.
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*/
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#define BASE_BAUD 3686400
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/*
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* UART base register addresses
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*/
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#define UART1_BASE (IO_BASE + 0x00044000)
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#define UART2_BASE (IO_BASE + 0x00045000)
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/*
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* UART register offsets
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*/
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#define UARTDR 0x00 /* Tx/Rx data */
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#define RXSTAT 0x04 /* Rx status */
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#define H_UBRLCR 0x08 /* mode register high */
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#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/
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#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/
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#define UARTCON 0x14 /* control register */
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#define UARTFLG 0x18 /* flag register */
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#define UARTINTSTAT 0x1C /* FIFO IRQ status register */
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#define UARTINTMASK 0x20 /* FIFO IRQ mask register */
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/*
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* UART baud rate register values
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*/
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#define BR_110 0x827
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#define BR_1200 0x06e
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#define BR_2400 0x05f
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#define BR_4800 0x02f
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#define BR_9600 0x017
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#define BR_14400 0x00f
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#define BR_19200 0x00b
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#define BR_38400 0x005
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#define BR_57600 0x003
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#define BR_76800 0x002
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#define BR_115200 0x001
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/*
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* Receiver status register (RXSTAT) mask values
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*/
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#define RXSTAT_NO_ERR 0x00 /* No error */
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#define RXSTAT_FRM_ERR 0x01 /* Framing error */
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#define RXSTAT_PAR_ERR 0x02 /* Parity error */
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#define RXSTAT_OVR_ERR 0x04 /* Overrun error */
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/*
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* High byte of UART bit rate and line control register (H_UBRLCR) values
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*/
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#define UBRLCR_BRK 0x01 /* generate break on tx */
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#define UBRLCR_PEN 0x02 /* enable parity */
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#define UBRLCR_PDIS 0x00 /* disable parity */
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#define UBRLCR_EVEN 0x04 /* 1= even parity,0 = odd parity */
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#define UBRLCR_STP2 0x08 /* transmit 2 stop bits */
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#define UBRLCR_FIFO 0x10 /* enable FIFO */
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#define UBRLCR_LEN5 0x60 /* word length5 */
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#define UBRLCR_LEN6 0x40 /* word length6 */
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#define UBRLCR_LEN7 0x20 /* word length7 */
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#define UBRLCR_LEN8 0x00 /* word length8 */
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/*
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* UART control register (UARTCON) values
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*/
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#define UARTCON_UARTEN 0x01 /* Enable UART */
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#define UARTCON_DMAONERR 0x08 /* Mask RxDmaRq when errors occur */
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/*
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* UART flag register (UARTFLG) mask values
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*/
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#define UARTFLG_UTXFF 0x20 /* Transmit FIFO full */
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#define UARTFLG_URXFE 0x10 /* Receiver FIFO empty */
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#define UARTFLG_UBUSY 0x08 /* Transmitter busy */
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#define UARTFLG_DCD 0x04 /* Data carrier detect */
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#define UARTFLG_DSR 0x02 /* Data set ready */
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#define UARTFLG_CTS 0x01 /* Clear to send */
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/*
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* UART interrupt status/clear registers (UARTINTSTAT/CLR) values
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*/
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#define UART_TXINT 0x01 /* TX interrupt */
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#define UART_RXINT 0x02 /* RX interrupt */
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#define UART_RXERRINT 0x04 /* RX error interrupt */
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#define UART_MSINT 0x08 /* Modem Status interrupt */
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#define UART_UDINT 0x10 /* UART Disabled interrupt */
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#define UART_ALLIRQS 0x1f /* All interrupts */
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#endif
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