126 lines
3.3 KiB
C
126 lines
3.3 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Derived from IRIX <sys/SN/nmi.h>, Revision 1.5.
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*
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* Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
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*/
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#ifndef __ASM_SN_NMI_H
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#define __ASM_SN_NMI_H
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#include <asm/sn/addrs.h>
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/*
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* The launch data structure resides at a fixed place in each node's memory
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* and is used to communicate between the master processor and the slave
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* processors.
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*
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* The master stores launch parameters in the launch structure
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* corresponding to a target processor that is in a slave loop, then sends
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* an interrupt to the slave processor. The slave calls the desired
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* function, followed by an optional rendezvous function, then returns to
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* the slave loop. The master does not wait for the slaves before
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* returning.
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*
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* There is an array of launch structures, one per CPU on the node. One
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* interrupt level is used per CPU.
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*/
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#define NMI_MAGIC 0x48414d4d455201
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#define NMI_SIZEOF 0x40
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#define NMI_OFF_MAGIC 0x00 /* Struct offsets for assembly */
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#define NMI_OFF_FLAGS 0x08
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#define NMI_OFF_CALL 0x10
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#define NMI_OFF_CALLC 0x18
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#define NMI_OFF_CALLPARM 0x20
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#define NMI_OFF_GMASTER 0x28
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/*
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* The NMI routine is called only if the complement address is
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* correct.
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*
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* Before control is transferred to a routine, the complement address
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* is zeroed (invalidated) to prevent an accidental call from a spurious
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* interrupt.
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*
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*/
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#ifndef __ASSEMBLY__
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typedef struct nmi_s {
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volatile unsigned long magic; /* Magic number */
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volatile unsigned long flags; /* Combination of flags above */
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volatile void *call_addr; /* Routine for slave to call */
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volatile void *call_addr_c; /* 1's complement of address */
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volatile void *call_parm; /* Single parm passed to call */
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volatile unsigned long gmaster; /* Flag true only on global master*/
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} nmi_t;
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#endif /* !__ASSEMBLY__ */
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/* Following definitions are needed both in the prom & the kernel
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* to identify the format of the nmi cpu register save area in the
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* low memory on each node.
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*/
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#ifndef __ASSEMBLY__
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struct reg_struct {
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unsigned long gpr[32];
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unsigned long sr;
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unsigned long cause;
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unsigned long epc;
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unsigned long badva;
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unsigned long error_epc;
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unsigned long cache_err;
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unsigned long nmi_sr;
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};
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#endif /* !__ASSEMBLY__ */
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/* These are the assembly language offsets into the reg_struct structure */
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#define R0_OFF 0x0
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#define R1_OFF 0x8
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#define R2_OFF 0x10
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#define R3_OFF 0x18
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#define R4_OFF 0x20
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#define R5_OFF 0x28
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#define R6_OFF 0x30
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#define R7_OFF 0x38
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#define R8_OFF 0x40
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#define R9_OFF 0x48
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#define R10_OFF 0x50
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#define R11_OFF 0x58
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#define R12_OFF 0x60
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#define R13_OFF 0x68
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#define R14_OFF 0x70
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#define R15_OFF 0x78
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#define R16_OFF 0x80
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#define R17_OFF 0x88
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#define R18_OFF 0x90
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#define R19_OFF 0x98
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#define R20_OFF 0xa0
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#define R21_OFF 0xa8
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#define R22_OFF 0xb0
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#define R23_OFF 0xb8
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#define R24_OFF 0xc0
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#define R25_OFF 0xc8
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#define R26_OFF 0xd0
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#define R27_OFF 0xd8
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#define R28_OFF 0xe0
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#define R29_OFF 0xe8
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#define R30_OFF 0xf0
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#define R31_OFF 0xf8
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#define SR_OFF 0x100
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#define CAUSE_OFF 0x108
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#define EPC_OFF 0x110
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#define BADVA_OFF 0x118
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#define ERROR_EPC_OFF 0x120
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#define CACHE_ERR_OFF 0x128
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#define NMISR_OFF 0x130
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#endif /* __ASM_SN_NMI_H */
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