463 lines
14 KiB
C
463 lines
14 KiB
C
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/*
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* arch/arm/plat-omap/include/mach/mcbsp.h
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*
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* Defines for Multi-Channel Buffered Serial Port
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*
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* Copyright (C) 2002 RidgeRun, Inc.
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* Author: Steve Johnson
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __ASM_ARCH_OMAP_MCBSP_H
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#define __ASM_ARCH_OMAP_MCBSP_H
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#include <linux/completion.h>
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#include <linux/spinlock.h>
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#include <mach/hardware.h>
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#include <mach/clock.h>
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#define OMAP730_MCBSP1_BASE 0xfffb1000
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#define OMAP730_MCBSP2_BASE 0xfffb1800
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#define OMAP1510_MCBSP1_BASE 0xe1011800
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#define OMAP1510_MCBSP2_BASE 0xfffb1000
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#define OMAP1510_MCBSP3_BASE 0xe1017000
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#define OMAP1610_MCBSP1_BASE 0xe1011800
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#define OMAP1610_MCBSP2_BASE 0xfffb1000
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#define OMAP1610_MCBSP3_BASE 0xe1017000
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#define OMAP24XX_MCBSP1_BASE 0x48074000
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#define OMAP24XX_MCBSP2_BASE 0x48076000
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#define OMAP2430_MCBSP3_BASE 0x4808c000
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#define OMAP2430_MCBSP4_BASE 0x4808e000
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#define OMAP2430_MCBSP5_BASE 0x48096000
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#define OMAP34XX_MCBSP1_BASE 0x48074000
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#define OMAP34XX_MCBSP2_BASE 0x49022000
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#define OMAP34XX_MCBSP3_BASE 0x49024000
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#define OMAP34XX_MCBSP4_BASE 0x49026000
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#define OMAP34XX_MCBSP5_BASE 0x48096000
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#define OMAP44XX_MCBSP1_BASE 0x49022000
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#define OMAP44XX_MCBSP2_BASE 0x49024000
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#define OMAP44XX_MCBSP3_BASE 0x49026000
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#define OMAP44XX_MCBSP4_BASE 0x48074000
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#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
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#define OMAP_MCBSP_REG_DRR2 0x00
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#define OMAP_MCBSP_REG_DRR1 0x02
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#define OMAP_MCBSP_REG_DXR2 0x04
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#define OMAP_MCBSP_REG_DXR1 0x06
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#define OMAP_MCBSP_REG_SPCR2 0x08
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#define OMAP_MCBSP_REG_SPCR1 0x0a
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#define OMAP_MCBSP_REG_RCR2 0x0c
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#define OMAP_MCBSP_REG_RCR1 0x0e
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#define OMAP_MCBSP_REG_XCR2 0x10
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#define OMAP_MCBSP_REG_XCR1 0x12
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#define OMAP_MCBSP_REG_SRGR2 0x14
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#define OMAP_MCBSP_REG_SRGR1 0x16
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#define OMAP_MCBSP_REG_MCR2 0x18
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#define OMAP_MCBSP_REG_MCR1 0x1a
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#define OMAP_MCBSP_REG_RCERA 0x1c
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#define OMAP_MCBSP_REG_RCERB 0x1e
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#define OMAP_MCBSP_REG_XCERA 0x20
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#define OMAP_MCBSP_REG_XCERB 0x22
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#define OMAP_MCBSP_REG_PCR0 0x24
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#define OMAP_MCBSP_REG_RCERC 0x26
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#define OMAP_MCBSP_REG_RCERD 0x28
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#define OMAP_MCBSP_REG_XCERC 0x2A
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#define OMAP_MCBSP_REG_XCERD 0x2C
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#define OMAP_MCBSP_REG_RCERE 0x2E
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#define OMAP_MCBSP_REG_RCERF 0x30
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#define OMAP_MCBSP_REG_XCERE 0x32
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#define OMAP_MCBSP_REG_XCERF 0x34
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#define OMAP_MCBSP_REG_RCERG 0x36
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#define OMAP_MCBSP_REG_RCERH 0x38
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#define OMAP_MCBSP_REG_XCERG 0x3A
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#define OMAP_MCBSP_REG_XCERH 0x3C
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/* Dummy defines, these are not available on omap1 */
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#define OMAP_MCBSP_REG_XCCR 0x00
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#define OMAP_MCBSP_REG_RCCR 0x00
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#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
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#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
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#define AUDIO_MCBSP OMAP_MCBSP1
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#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
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#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
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#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
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defined(CONFIG_ARCH_OMAP4)
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#define OMAP_MCBSP_REG_DRR2 0x00
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#define OMAP_MCBSP_REG_DRR1 0x04
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#define OMAP_MCBSP_REG_DXR2 0x08
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#define OMAP_MCBSP_REG_DXR1 0x0C
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#define OMAP_MCBSP_REG_DRR 0x00
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#define OMAP_MCBSP_REG_DXR 0x08
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#define OMAP_MCBSP_REG_SPCR2 0x10
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#define OMAP_MCBSP_REG_SPCR1 0x14
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#define OMAP_MCBSP_REG_RCR2 0x18
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#define OMAP_MCBSP_REG_RCR1 0x1C
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#define OMAP_MCBSP_REG_XCR2 0x20
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#define OMAP_MCBSP_REG_XCR1 0x24
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#define OMAP_MCBSP_REG_SRGR2 0x28
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#define OMAP_MCBSP_REG_SRGR1 0x2C
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#define OMAP_MCBSP_REG_MCR2 0x30
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#define OMAP_MCBSP_REG_MCR1 0x34
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#define OMAP_MCBSP_REG_RCERA 0x38
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#define OMAP_MCBSP_REG_RCERB 0x3C
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#define OMAP_MCBSP_REG_XCERA 0x40
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#define OMAP_MCBSP_REG_XCERB 0x44
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#define OMAP_MCBSP_REG_PCR0 0x48
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#define OMAP_MCBSP_REG_RCERC 0x4C
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#define OMAP_MCBSP_REG_RCERD 0x50
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#define OMAP_MCBSP_REG_XCERC 0x54
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#define OMAP_MCBSP_REG_XCERD 0x58
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#define OMAP_MCBSP_REG_RCERE 0x5C
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#define OMAP_MCBSP_REG_RCERF 0x60
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#define OMAP_MCBSP_REG_XCERE 0x64
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#define OMAP_MCBSP_REG_XCERF 0x68
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#define OMAP_MCBSP_REG_RCERG 0x6C
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#define OMAP_MCBSP_REG_RCERH 0x70
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#define OMAP_MCBSP_REG_XCERG 0x74
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#define OMAP_MCBSP_REG_XCERH 0x78
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#define OMAP_MCBSP_REG_SYSCON 0x8C
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#define OMAP_MCBSP_REG_THRSH2 0x90
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#define OMAP_MCBSP_REG_THRSH1 0x94
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#define OMAP_MCBSP_REG_IRQST 0xA0
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#define OMAP_MCBSP_REG_IRQEN 0xA4
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#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
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#define OMAP_MCBSP_REG_XCCR 0xAC
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#define OMAP_MCBSP_REG_RCCR 0xB0
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#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
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#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
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#define AUDIO_MCBSP OMAP_MCBSP2
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#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
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#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
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#endif
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/************************** McBSP SPCR1 bit definitions ***********************/
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#define RRST 0x0001
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#define RRDY 0x0002
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#define RFULL 0x0004
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#define RSYNC_ERR 0x0008
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#define RINTM(value) ((value)<<4) /* bits 4:5 */
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#define ABIS 0x0040
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#define DXENA 0x0080
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#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
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#define RJUST(value) ((value)<<13) /* bits 13:14 */
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#define ALB 0x8000
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#define DLB 0x8000
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/************************** McBSP SPCR2 bit definitions ***********************/
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#define XRST 0x0001
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#define XRDY 0x0002
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#define XEMPTY 0x0004
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#define XSYNC_ERR 0x0008
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#define XINTM(value) ((value)<<4) /* bits 4:5 */
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#define GRST 0x0040
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#define FRST 0x0080
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#define SOFT 0x0100
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#define FREE 0x0200
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/************************** McBSP PCR bit definitions *************************/
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#define CLKRP 0x0001
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#define CLKXP 0x0002
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#define FSRP 0x0004
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#define FSXP 0x0008
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#define DR_STAT 0x0010
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#define DX_STAT 0x0020
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#define CLKS_STAT 0x0040
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#define SCLKME 0x0080
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#define CLKRM 0x0100
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#define CLKXM 0x0200
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#define FSRM 0x0400
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#define FSXM 0x0800
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#define RIOEN 0x1000
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#define XIOEN 0x2000
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#define IDLE_EN 0x4000
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/************************** McBSP RCR1 bit definitions ************************/
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#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
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#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
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/************************** McBSP XCR1 bit definitions ************************/
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#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
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#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
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/*************************** McBSP RCR2 bit definitions ***********************/
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#define RDATDLY(value) (value) /* Bits 0:1 */
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#define RFIG 0x0004
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#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
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#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
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#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
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#define RPHASE 0x8000
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/*************************** McBSP XCR2 bit definitions ***********************/
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#define XDATDLY(value) (value) /* Bits 0:1 */
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#define XFIG 0x0004
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#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
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#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
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#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
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#define XPHASE 0x8000
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/************************* McBSP SRGR1 bit definitions ************************/
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#define CLKGDV(value) (value) /* Bits 0:7 */
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#define FWID(value) ((value)<<8) /* Bits 8:15 */
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/************************* McBSP SRGR2 bit definitions ************************/
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#define FPER(value) (value) /* Bits 0:11 */
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#define FSGM 0x1000
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#define CLKSM 0x2000
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#define CLKSP 0x4000
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#define GSYNC 0x8000
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/************************* McBSP MCR1 bit definitions *************************/
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#define RMCM 0x0001
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#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
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#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
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#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
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/************************* McBSP MCR2 bit definitions *************************/
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#define XMCM(value) (value) /* Bits 0:1 */
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#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
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#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
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#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
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/*********************** McBSP XCCR bit definitions *************************/
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#define EXTCLKGATE 0x8000
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#define PPCONNECT 0x4000
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#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
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#define XFULL_CYCLE 0x0800
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#define DILB 0x0020
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#define XDMAEN 0x0008
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#define XDISABLE 0x0001
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/********************** McBSP RCCR bit definitions *************************/
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#define RFULL_CYCLE 0x0800
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#define RDMAEN 0x0008
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#define RDISABLE 0x0001
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/********************** McBSP SYSCONFIG bit definitions ********************/
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#define CLOCKACTIVITY(value) ((value)<<8)
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#define SIDLEMODE(value) ((value)<<3)
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#define ENAWAKEUP 0x0004
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#define SOFTRST 0x0002
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/********************** McBSP DMA operating modes **************************/
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#define MCBSP_DMA_MODE_ELEMENT 0
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#define MCBSP_DMA_MODE_THRESHOLD 1
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#define MCBSP_DMA_MODE_FRAME 2
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/********************** McBSP WAKEUPEN bit definitions *********************/
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#define XEMPTYEOFEN 0x4000
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#define XRDYEN 0x0400
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#define XEOFEN 0x0200
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#define XFSXEN 0x0100
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#define XSYNCERREN 0x0080
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#define RRDYEN 0x0008
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#define REOFEN 0x0004
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#define RFSREN 0x0002
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#define RSYNCERREN 0x0001
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/* we don't do multichannel for now */
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struct omap_mcbsp_reg_cfg {
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u16 spcr2;
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u16 spcr1;
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u16 rcr2;
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u16 rcr1;
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u16 xcr2;
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u16 xcr1;
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u16 srgr2;
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u16 srgr1;
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u16 mcr2;
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u16 mcr1;
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u16 pcr0;
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u16 rcerc;
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u16 rcerd;
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u16 xcerc;
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u16 xcerd;
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u16 rcere;
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u16 rcerf;
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u16 xcere;
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u16 xcerf;
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u16 rcerg;
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u16 rcerh;
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u16 xcerg;
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u16 xcerh;
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u16 xccr;
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u16 rccr;
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};
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typedef enum {
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OMAP_MCBSP1 = 0,
|
||
|
|
OMAP_MCBSP2,
|
||
|
|
OMAP_MCBSP3,
|
||
|
|
OMAP_MCBSP4,
|
||
|
|
OMAP_MCBSP5
|
||
|
|
} omap_mcbsp_id;
|
||
|
|
|
||
|
|
typedef int __bitwise omap_mcbsp_io_type_t;
|
||
|
|
#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
|
||
|
|
#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
|
||
|
|
|
||
|
|
typedef enum {
|
||
|
|
OMAP_MCBSP_WORD_8 = 0,
|
||
|
|
OMAP_MCBSP_WORD_12,
|
||
|
|
OMAP_MCBSP_WORD_16,
|
||
|
|
OMAP_MCBSP_WORD_20,
|
||
|
|
OMAP_MCBSP_WORD_24,
|
||
|
|
OMAP_MCBSP_WORD_32,
|
||
|
|
} omap_mcbsp_word_length;
|
||
|
|
|
||
|
|
typedef enum {
|
||
|
|
OMAP_MCBSP_CLK_RISING = 0,
|
||
|
|
OMAP_MCBSP_CLK_FALLING,
|
||
|
|
} omap_mcbsp_clk_polarity;
|
||
|
|
|
||
|
|
typedef enum {
|
||
|
|
OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
|
||
|
|
OMAP_MCBSP_FS_ACTIVE_LOW,
|
||
|
|
} omap_mcbsp_fs_polarity;
|
||
|
|
|
||
|
|
typedef enum {
|
||
|
|
OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
|
||
|
|
OMAP_MCBSP_CLK_STP_MODE_DELAY,
|
||
|
|
} omap_mcbsp_clk_stp_mode;
|
||
|
|
|
||
|
|
|
||
|
|
/******* SPI specific mode **********/
|
||
|
|
typedef enum {
|
||
|
|
OMAP_MCBSP_SPI_MASTER = 0,
|
||
|
|
OMAP_MCBSP_SPI_SLAVE,
|
||
|
|
} omap_mcbsp_spi_mode;
|
||
|
|
|
||
|
|
struct omap_mcbsp_spi_cfg {
|
||
|
|
omap_mcbsp_spi_mode spi_mode;
|
||
|
|
omap_mcbsp_clk_polarity rx_clock_polarity;
|
||
|
|
omap_mcbsp_clk_polarity tx_clock_polarity;
|
||
|
|
omap_mcbsp_fs_polarity fsx_polarity;
|
||
|
|
u8 clk_div;
|
||
|
|
omap_mcbsp_clk_stp_mode clk_stp_mode;
|
||
|
|
omap_mcbsp_word_length word_length;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Platform specific configuration */
|
||
|
|
struct omap_mcbsp_ops {
|
||
|
|
void (*request)(unsigned int);
|
||
|
|
void (*free)(unsigned int);
|
||
|
|
};
|
||
|
|
|
||
|
|
struct omap_mcbsp_platform_data {
|
||
|
|
unsigned long phys_base;
|
||
|
|
u8 dma_rx_sync, dma_tx_sync;
|
||
|
|
u16 rx_irq, tx_irq;
|
||
|
|
struct omap_mcbsp_ops *ops;
|
||
|
|
#ifdef CONFIG_ARCH_OMAP34XX
|
||
|
|
u16 buffer_size;
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
struct omap_mcbsp {
|
||
|
|
struct device *dev;
|
||
|
|
unsigned long phys_base;
|
||
|
|
void __iomem *io_base;
|
||
|
|
u8 id;
|
||
|
|
u8 free;
|
||
|
|
omap_mcbsp_word_length rx_word_length;
|
||
|
|
omap_mcbsp_word_length tx_word_length;
|
||
|
|
|
||
|
|
omap_mcbsp_io_type_t io_type; /* IRQ or poll */
|
||
|
|
/* IRQ based TX/RX */
|
||
|
|
int rx_irq;
|
||
|
|
int tx_irq;
|
||
|
|
|
||
|
|
/* DMA stuff */
|
||
|
|
u8 dma_rx_sync;
|
||
|
|
short dma_rx_lch;
|
||
|
|
u8 dma_tx_sync;
|
||
|
|
short dma_tx_lch;
|
||
|
|
|
||
|
|
/* Completion queues */
|
||
|
|
struct completion tx_irq_completion;
|
||
|
|
struct completion rx_irq_completion;
|
||
|
|
struct completion tx_dma_completion;
|
||
|
|
struct completion rx_dma_completion;
|
||
|
|
|
||
|
|
/* Protect the field .free, while checking if the mcbsp is in use */
|
||
|
|
spinlock_t lock;
|
||
|
|
struct omap_mcbsp_platform_data *pdata;
|
||
|
|
struct clk *iclk;
|
||
|
|
struct clk *fclk;
|
||
|
|
#ifdef CONFIG_ARCH_OMAP34XX
|
||
|
|
int dma_op_mode;
|
||
|
|
u16 max_tx_thres;
|
||
|
|
u16 max_rx_thres;
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
extern struct omap_mcbsp **mcbsp_ptr;
|
||
|
|
extern int omap_mcbsp_count;
|
||
|
|
|
||
|
|
int omap_mcbsp_init(void);
|
||
|
|
void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
|
||
|
|
int size);
|
||
|
|
void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
|
||
|
|
#ifdef CONFIG_ARCH_OMAP34XX
|
||
|
|
void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
|
||
|
|
void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
|
||
|
|
u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
|
||
|
|
u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
|
||
|
|
int omap_mcbsp_get_dma_op_mode(unsigned int id);
|
||
|
|
#else
|
||
|
|
static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
|
||
|
|
{ }
|
||
|
|
static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
|
||
|
|
{ }
|
||
|
|
static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
|
||
|
|
static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
|
||
|
|
static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
|
||
|
|
#endif
|
||
|
|
int omap_mcbsp_request(unsigned int id);
|
||
|
|
void omap_mcbsp_free(unsigned int id);
|
||
|
|
void omap_mcbsp_start(unsigned int id, int tx, int rx);
|
||
|
|
void omap_mcbsp_stop(unsigned int id, int tx, int rx);
|
||
|
|
void omap_mcbsp_xmit_word(unsigned int id, u32 word);
|
||
|
|
u32 omap_mcbsp_recv_word(unsigned int id);
|
||
|
|
|
||
|
|
int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
|
||
|
|
int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
|
||
|
|
int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
|
||
|
|
int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
|
||
|
|
|
||
|
|
|
||
|
|
/* SPI specific API */
|
||
|
|
void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
|
||
|
|
|
||
|
|
/* Polled read/write functions */
|
||
|
|
int omap_mcbsp_pollread(unsigned int id, u16 * buf);
|
||
|
|
int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
|
||
|
|
int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
|
||
|
|
|
||
|
|
#endif
|