564 lines
12 KiB
C
564 lines
12 KiB
C
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/*
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/gpio.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/common.h>
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#include <mach/imx-uart.h>
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#include <mach/mx3_camera.h>
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#include "devices.h"
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static struct resource uart0[] = {
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{
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.start = UART1_BASE_ADDR,
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.end = UART1_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART1,
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.end = MXC_INT_UART1,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device0 = {
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.name = "imx-uart",
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.id = 0,
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.resource = uart0,
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.num_resources = ARRAY_SIZE(uart0),
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};
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static struct resource uart1[] = {
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{
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.start = UART2_BASE_ADDR,
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.end = UART2_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART2,
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.end = MXC_INT_UART2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device1 = {
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.name = "imx-uart",
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.id = 1,
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.resource = uart1,
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.num_resources = ARRAY_SIZE(uart1),
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};
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static struct resource uart2[] = {
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{
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.start = UART3_BASE_ADDR,
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.end = UART3_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART3,
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.end = MXC_INT_UART3,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device2 = {
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.name = "imx-uart",
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.id = 2,
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.resource = uart2,
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.num_resources = ARRAY_SIZE(uart2),
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};
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#ifdef CONFIG_ARCH_MX31
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static struct resource uart3[] = {
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{
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.start = UART4_BASE_ADDR,
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.end = UART4_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART4,
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.end = MXC_INT_UART4,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device3 = {
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.name = "imx-uart",
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.id = 3,
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.resource = uart3,
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.num_resources = ARRAY_SIZE(uart3),
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};
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static struct resource uart4[] = {
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{
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.start = UART5_BASE_ADDR,
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.end = UART5_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART5,
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.end = MXC_INT_UART5,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device4 = {
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.name = "imx-uart",
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.id = 4,
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.resource = uart4,
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.num_resources = ARRAY_SIZE(uart4),
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};
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#endif /* CONFIG_ARCH_MX31 */
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/* GPIO port description */
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static struct mxc_gpio_port imx_gpio_ports[] = {
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{
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.chip.label = "gpio-0",
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.base = IO_ADDRESS(GPIO1_BASE_ADDR),
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.irq = MXC_INT_GPIO1,
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.virtual_irq_start = MXC_GPIO_IRQ_START,
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}, {
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.chip.label = "gpio-1",
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.base = IO_ADDRESS(GPIO2_BASE_ADDR),
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.irq = MXC_INT_GPIO2,
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.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
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}, {
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.chip.label = "gpio-2",
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.base = IO_ADDRESS(GPIO3_BASE_ADDR),
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.irq = MXC_INT_GPIO3,
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.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
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}
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};
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int __init mxc_register_gpios(void)
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{
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return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
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}
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static struct resource mxc_w1_master_resources[] = {
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{
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.start = OWIRE_BASE_ADDR,
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.end = OWIRE_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mxc_w1_master_device = {
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.name = "mxc_w1",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
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.resource = mxc_w1_master_resources,
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};
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static struct resource mxc_nand_resources[] = {
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{
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.start = 0, /* runtime dependent */
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.end = 0,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_NANDFC,
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.end = MXC_INT_NANDFC,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_nand_device = {
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.name = "mxc_nand",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_nand_resources),
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.resource = mxc_nand_resources,
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};
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static struct resource mxc_i2c0_resources[] = {
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{
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.start = I2C_BASE_ADDR,
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.end = I2C_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_I2C,
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.end = MXC_INT_I2C,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_i2c_device0 = {
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.name = "imx-i2c",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
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.resource = mxc_i2c0_resources,
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};
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static struct resource mxc_i2c1_resources[] = {
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{
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.start = I2C2_BASE_ADDR,
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.end = I2C2_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_I2C2,
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.end = MXC_INT_I2C2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_i2c_device1 = {
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.name = "imx-i2c",
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.id = 1,
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.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
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.resource = mxc_i2c1_resources,
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};
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static struct resource mxc_i2c2_resources[] = {
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{
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.start = I2C3_BASE_ADDR,
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.end = I2C3_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_I2C3,
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.end = MXC_INT_I2C3,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_i2c_device2 = {
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.name = "imx-i2c",
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.id = 2,
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.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
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.resource = mxc_i2c2_resources,
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};
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#ifdef CONFIG_ARCH_MX31
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static struct resource mxcsdhc0_resources[] = {
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{
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.start = MMC_SDHC1_BASE_ADDR,
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.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_MMC_SDHC1,
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.end = MXC_INT_MMC_SDHC1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource mxcsdhc1_resources[] = {
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{
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.start = MMC_SDHC2_BASE_ADDR,
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.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_MMC_SDHC2,
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.end = MXC_INT_MMC_SDHC2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxcsdhc_device0 = {
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.name = "mxc-mmc",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
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.resource = mxcsdhc0_resources,
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};
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struct platform_device mxcsdhc_device1 = {
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.name = "mxc-mmc",
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.id = 1,
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.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
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.resource = mxcsdhc1_resources,
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};
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static struct resource rnga_resources[] = {
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{
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.start = RNGA_BASE_ADDR,
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.end = RNGA_BASE_ADDR + 0x28,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mxc_rnga_device = {
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.name = "mxc_rnga",
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.id = -1,
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.num_resources = 1,
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.resource = rnga_resources,
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};
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#endif /* CONFIG_ARCH_MX31 */
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/* i.MX31 Image Processing Unit */
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/* The resource order is important! */
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static struct resource mx3_ipu_rsrc[] = {
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{
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.start = IPU_CTRL_BASE_ADDR,
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.end = IPU_CTRL_BASE_ADDR + 0x5F,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IPU_CTRL_BASE_ADDR + 0x88,
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.end = IPU_CTRL_BASE_ADDR + 0xB3,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_IPU_SYN,
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.end = MXC_INT_IPU_SYN,
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.flags = IORESOURCE_IRQ,
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}, {
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.start = MXC_INT_IPU_ERR,
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.end = MXC_INT_IPU_ERR,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mx3_ipu = {
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.name = "ipu-core",
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.id = -1,
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.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
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.resource = mx3_ipu_rsrc,
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};
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static struct resource fb_resources[] = {
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{
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.start = IPU_CTRL_BASE_ADDR + 0xB4,
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.end = IPU_CTRL_BASE_ADDR + 0x1BF,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mx3_fb = {
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.name = "mx3_sdc_fb",
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.id = -1,
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.num_resources = ARRAY_SIZE(fb_resources),
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.resource = fb_resources,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct resource camera_resources[] = {
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{
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.start = IPU_CTRL_BASE_ADDR + 0x60,
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.end = IPU_CTRL_BASE_ADDR + 0x87,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mx3_camera = {
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.name = "mx3-camera",
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.id = 0,
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.num_resources = ARRAY_SIZE(camera_resources),
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.resource = camera_resources,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct resource otg_resources[] = {
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{
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.start = MX31_OTG_BASE_ADDR,
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.end = MX31_OTG_BASE_ADDR + 0x1ff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_USB3,
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.end = MXC_INT_USB3,
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.flags = IORESOURCE_IRQ,
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},
|
||
|
|
};
|
||
|
|
|
||
|
|
static u64 otg_dmamask = DMA_BIT_MASK(32);
|
||
|
|
|
||
|
|
/* OTG gadget device */
|
||
|
|
struct platform_device mxc_otg_udc_device = {
|
||
|
|
.name = "fsl-usb2-udc",
|
||
|
|
.id = -1,
|
||
|
|
.dev = {
|
||
|
|
.dma_mask = &otg_dmamask,
|
||
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||
|
|
},
|
||
|
|
.resource = otg_resources,
|
||
|
|
.num_resources = ARRAY_SIZE(otg_resources),
|
||
|
|
};
|
||
|
|
|
||
|
|
/* OTG host */
|
||
|
|
struct platform_device mxc_otg_host = {
|
||
|
|
.name = "mxc-ehci",
|
||
|
|
.id = 0,
|
||
|
|
.dev = {
|
||
|
|
.coherent_dma_mask = 0xffffffff,
|
||
|
|
.dma_mask = &otg_dmamask,
|
||
|
|
},
|
||
|
|
.resource = otg_resources,
|
||
|
|
.num_resources = ARRAY_SIZE(otg_resources),
|
||
|
|
};
|
||
|
|
|
||
|
|
/* USB host 1 */
|
||
|
|
|
||
|
|
static u64 usbh1_dmamask = ~(u32)0;
|
||
|
|
|
||
|
|
static struct resource mxc_usbh1_resources[] = {
|
||
|
|
{
|
||
|
|
.start = MX31_OTG_BASE_ADDR + 0x200,
|
||
|
|
.end = MX31_OTG_BASE_ADDR + 0x3ff,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
}, {
|
||
|
|
.start = MXC_INT_USB1,
|
||
|
|
.end = MXC_INT_USB1,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
struct platform_device mxc_usbh1 = {
|
||
|
|
.name = "mxc-ehci",
|
||
|
|
.id = 1,
|
||
|
|
.dev = {
|
||
|
|
.coherent_dma_mask = 0xffffffff,
|
||
|
|
.dma_mask = &usbh1_dmamask,
|
||
|
|
},
|
||
|
|
.resource = mxc_usbh1_resources,
|
||
|
|
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
|
||
|
|
};
|
||
|
|
|
||
|
|
/* USB host 2 */
|
||
|
|
static u64 usbh2_dmamask = ~(u32)0;
|
||
|
|
|
||
|
|
static struct resource mxc_usbh2_resources[] = {
|
||
|
|
{
|
||
|
|
.start = MX31_OTG_BASE_ADDR + 0x400,
|
||
|
|
.end = MX31_OTG_BASE_ADDR + 0x5ff,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
}, {
|
||
|
|
.start = MXC_INT_USB2,
|
||
|
|
.end = MXC_INT_USB2,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
struct platform_device mxc_usbh2 = {
|
||
|
|
.name = "mxc-ehci",
|
||
|
|
.id = 2,
|
||
|
|
.dev = {
|
||
|
|
.coherent_dma_mask = 0xffffffff,
|
||
|
|
.dma_mask = &usbh2_dmamask,
|
||
|
|
},
|
||
|
|
.resource = mxc_usbh2_resources,
|
||
|
|
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SPI master controller
|
||
|
|
* 3 channels
|
||
|
|
*/
|
||
|
|
static struct resource mxc_spi_0_resources[] = {
|
||
|
|
{
|
||
|
|
.start = CSPI1_BASE_ADDR,
|
||
|
|
.end = CSPI1_BASE_ADDR + SZ_4K - 1,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
}, {
|
||
|
|
.start = MXC_INT_CSPI1,
|
||
|
|
.end = MXC_INT_CSPI1,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource mxc_spi_1_resources[] = {
|
||
|
|
{
|
||
|
|
.start = CSPI2_BASE_ADDR,
|
||
|
|
.end = CSPI2_BASE_ADDR + SZ_4K - 1,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
}, {
|
||
|
|
.start = MXC_INT_CSPI2,
|
||
|
|
.end = MXC_INT_CSPI2,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource mxc_spi_2_resources[] = {
|
||
|
|
{
|
||
|
|
.start = CSPI3_BASE_ADDR,
|
||
|
|
.end = CSPI3_BASE_ADDR + SZ_4K - 1,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
}, {
|
||
|
|
.start = MXC_INT_CSPI3,
|
||
|
|
.end = MXC_INT_CSPI3,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
struct platform_device mxc_spi_device0 = {
|
||
|
|
.name = "spi_imx",
|
||
|
|
.id = 0,
|
||
|
|
.num_resources = ARRAY_SIZE(mxc_spi_0_resources),
|
||
|
|
.resource = mxc_spi_0_resources,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct platform_device mxc_spi_device1 = {
|
||
|
|
.name = "spi_imx",
|
||
|
|
.id = 1,
|
||
|
|
.num_resources = ARRAY_SIZE(mxc_spi_1_resources),
|
||
|
|
.resource = mxc_spi_1_resources,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct platform_device mxc_spi_device2 = {
|
||
|
|
.name = "spi_imx",
|
||
|
|
.id = 2,
|
||
|
|
.num_resources = ARRAY_SIZE(mxc_spi_2_resources),
|
||
|
|
.resource = mxc_spi_2_resources,
|
||
|
|
};
|
||
|
|
|
||
|
|
#ifdef CONFIG_ARCH_MX35
|
||
|
|
static struct resource mxc_fec_resources[] = {
|
||
|
|
{
|
||
|
|
.start = MXC_FEC_BASE_ADDR,
|
||
|
|
.end = MXC_FEC_BASE_ADDR + 0xfff,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
}, {
|
||
|
|
.start = MXC_INT_FEC,
|
||
|
|
.end = MXC_INT_FEC,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
struct platform_device mxc_fec_device = {
|
||
|
|
.name = "fec",
|
||
|
|
.id = 0,
|
||
|
|
.num_resources = ARRAY_SIZE(mxc_fec_resources),
|
||
|
|
.resource = mxc_fec_resources,
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static int mx3_devices_init(void)
|
||
|
|
{
|
||
|
|
if (cpu_is_mx31()) {
|
||
|
|
mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
|
||
|
|
mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
|
||
|
|
mxc_register_device(&mxc_rnga_device, NULL);
|
||
|
|
}
|
||
|
|
if (cpu_is_mx35()) {
|
||
|
|
mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
|
||
|
|
mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
|
||
|
|
otg_resources[0].start = MX35_OTG_BASE_ADDR;
|
||
|
|
otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
|
||
|
|
otg_resources[1].start = MXC_INT_USBOTG;
|
||
|
|
otg_resources[1].end = MXC_INT_USBOTG;
|
||
|
|
mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
|
||
|
|
mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
|
||
|
|
mxc_usbh1_resources[1].start = MXC_INT_USBHS;
|
||
|
|
mxc_usbh1_resources[1].end = MXC_INT_USBHS;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
subsys_initcall(mx3_devices_init);
|